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RX6501

型号：

RX6501

描述：

868.35兆赫混合接收机[ 868.35 MHz Hybrid Receiver ]

品牌：

RFM[ RF MONOLITHICS, INC ]

页数：

10 页

PDF大小：

63 K

下载PDF手册
®
RX6501  
•
•
•
•
•
Designed for Short-Range Wireless Control Applications  
Supports RF Data Transmission Rates Up to 19.2 kbps  
3 V, Low Current Operation plus Sleep Mode  
868.35 MHz  
Hybrid  
Stable, Easy to Use, Low External Parts Count  
Complies with Directive 2002/95/EC (RoHS)  
Receiver  
The RX6501 hybrid receiver is ideal for short-range wireless control applications where robust operation,  
small size, low power consumption and low cost are required. The RX6501 employs RFM’s amplifier-se-  
quenced hybrid (ASH) architecture to achieve this unique blend of characteristics. All critical RF functions are  
contained in the hybrid, simplifying and speeding design-in. The RX6501 is sensitive and stable. A wide dy-  
namic range log detector provides robust performance in the presence of on-channel interference or noise.  
Two stages of SAW filtering provide excellent receiver out-of-band rejection. The RX6501 generates virtually  
no RF emissions, facilitating compliance with ETSI I-ETS 300 220 and similar regulations.  
Rating  
Power Supply and All Input/Output Pins  
Non-Operating Case Temperature  
Value  
-0.3 to +4.0  
-50 to +100  
260  
Units  
V
°C  
SM-20H Case  
Soldering Temperature (10 seconds / 5 cycles max.)  
°C  
Electrical Characteristics  
Characteristic  
Sym  
Notes  
Minimum  
Typical  
Maximum  
Units  
f
Operating Frequency  
868.15  
868.55  
MHz  
o
Modulation Types  
OOK & ASK  
Data Rate  
19.2  
kbps  
Receiver Performance, High Sensitivity Mode  
Sensitivity, 1.2 kbps, 10-3 BER, AM Test Method  
Sensitivity, 1.2 kbps, 10-3 BER, Pulse Test Method  
1
1
2
1
1
2
1
1
-107.5  
-101.5  
2.9  
dBm  
dBm  
mA  
Current, 1.2 kbps (R = 330 K)  
PR  
Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method  
Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method  
-106  
-100  
3.0  
dBm  
dBm  
mA  
Current, 2.4 kbps (R = 330 K)  
PR  
Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method  
Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method  
Current, 19.2 kbps  
-97  
dBm  
dBm  
mA  
-91  
3.1  
Receiver Performance, Low Current Mode  
Sensitivity, 1.2 kbps, 10-3 BER, AM Test Method  
Sensitivity, 1.2 kbps, 10-3 BER, Pulse Test Method  
1
1
2
-104  
-98  
dBm  
dBm  
mA  
Current, 1.2 kbps (R = 2000 K)  
1.65  
PR  
RF Monolithics, Inc.  
RFM Europe  
Phone: (972) 233-2903  
Phone: 44 1963 251383  
Fax: (972) 387-8148  
Fax: 44 1963 251510  
E-mail: info@rfm.com  
http://www.rfm.com  
RX6501-062905  
Page 1 of 10  
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.  
Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 °C)  
Characteristic  
Sym  
Notes  
Minimum  
Typical  
Maximum  
Units  
R
Receiver Out-of-Band Rejection, ±5% fo  
Receiver Ultimate Rejection  
Sleep Mode Current  
3
3
80  
100  
0.7  
dB  
dB  
±5%  
R
ULT  
I
µA  
S
V
Power Supply Voltage Range  
Power Supply Voltage Ripple  
Ambient Operating Temperature  
2.2  
-40  
3.7  
10  
85  
Vdc  
CC  
mV  
P-P  
T
°C  
A
Notes:  
-3  
1. Typical sensitivity data is based on a 10 bit error rate (BER), using DC-balanced data. There are two test methods commonly used to measure  
OOK/ASK receiver sensitivity, the “100% AM” test method and the “Pulse” test method. Sensitivity data is given for both test methods. See Ap-  
pendix 3.8 in the ASH Transceiver Designer’s Guide for the details of each test method, and for sensitivity curves for a 2.2 to 3.7 V supply voltage  
range at five operating temperatures. The application/test circuit and component values are shown on the next page and in the Designer’s Guide.  
2. At low data rates it is possible to adjust the ASH pulse generator to trade-off some receiver sensitivity for lower operating current. Sensitivity  
data and receiver current are given at 1.2 kbps for both high sensitivity operation (R = 330 K) and low current operation (R = 2000 K).  
PR  
PR  
3. Data is given with the ASH radio matched to a 50 ohm load. Matching component values are given on the next page.  
4. See Table 1 on Page 8 for additional information on ASH radio event timing.  
SM-20H Package Drawing  
B
C
D
E
F
ASH Transceiver Pin Out  
GND1  
RFIO  
A
1
20  
VCC1  
AGCCAP  
PKDET  
2
3
4
5
6
7
8
9
19 GND3  
18 CNTRL0  
17 CNTRL1  
16 VCC2  
H
G
BBOUT  
CMPIN  
15 PWIDTH  
14 PRATE  
13 THLD1  
12 THLD2  
mm  
Inches  
Nom  
RXDATA  
TXMOD  
LPFADJ  
Dimension  
Min  
Nom  
Max  
Min  
Max  
A
B
C
9.881  
6.731  
1.778  
1.651  
0.381  
0.889  
3.175  
1.397  
10.033  
6.858  
1.930  
1.778  
0.508  
1.016  
3.302  
1.524  
10.135  
6.985  
2.032  
1.905  
0.635  
1.143  
3.429  
1.651  
.389  
.265  
.070  
.065  
.015  
.035  
.125  
.055  
.395  
.270  
.076  
.070  
.020  
.040  
.130  
.060  
.400  
.275  
.080  
.075  
.025  
.045  
.135  
.065  
10 11  
GND2  
RREF  
D
E
F
G
H
RF Monolithics, Inc.  
RFM Europe  
Phone: (972) 233-2903  
Phone: 44 1963 251383  
Fax: (972) 387-8148  
Fax: 44 1963 251510  
E-mail: info@rfm.com  
http://www.rfm.com  
RX6501-062905  
Page 2 of 10  
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.  
ASH Receiver Application Circuit  
OOK Configuration  
+ 3  
VDC  
CDCB  
+
R TH1  
R/S  
R PW  
R PR  
19  
GND  
18  
CNT  
17  
CNT  
16  
VCC  
15  
14  
13  
12  
NC  
P
P
THLD  
1
LAT  
3
RL0  
RL1  
2
WIDTH RATE  
RFIO  
RREF  
11  
10  
20  
R REF  
TOP VIEW  
LESD  
GND1  
GND2  
1
VCC  
1
RF  
A1  
PK  
DET  
BB  
OUT  
CMP  
IN  
RX  
DATA  
LPF  
ADJ  
NC  
8
2
3
4
5
6
7
9
R LPF  
R BBO  
CRFB1  
+ 3  
VDC  
CBBO  
CLPF  
Data Output  
Receiver Set-Up, 3.0 Vdc, -40 to +85 °C  
Item  
Symbol  
DR  
OOK  
OOK  
ASK  
Units  
Notes  
Nominal NRZ Data Rate  
1.2  
2.4  
19.2  
kbps  
µs  
µs  
µF  
K
see page 1& 2  
NOM  
Minimum Signal Pulse  
Maximum Signal Pulse  
BBOUT Capacitor  
SP  
833.33  
416.67  
1666.68  
0.1  
52.08  
single bit  
4 bits of same value  
±10% ceramic  
±5%  
MIN  
MAX  
BBO  
BBO  
SP  
3333.33  
0.2  
208.32  
C
R
0.015  
BBOUT Resistor  
12  
12  
0
LPFAUX Capacitor  
LPFADJ Resistor  
C
R
0.01  
330  
100  
0
0.0047  
300  
-
µF  
K
±5%  
LPF  
LPF  
REF  
100  
±5%  
RREF Resistor  
R
100  
100  
K
±1%  
THLD1 Resistor  
R
R
0
0
330  
K
±1%, typical values  
±5%  
TH1  
PRATE Resistor  
R
330  
330  
K
PR  
PWIDTH Resistor  
270 to GND  
270 to GND  
270 to GND  
4.7  
K
±5%  
PW  
DC Bypass Capacitor  
RF Bypass Capacitor 1  
Antenna Tuning Inductor  
Shunt Tuning/ESD Inductor  
C
4.7  
27  
4.7  
27  
µF  
pF  
nH  
nH  
tantalum  
DCB  
C
27  
±5% NPO  
50 ohm antenna  
50 ohm antenna  
RFB1  
L
10  
10  
10  
AT  
L
100  
100  
100  
ESD  
CAUTION: Electrostatic Device. Observe precautions when handling.  
RF Monolithics, Inc.  
RFM Europe  
Phone: (972) 233-2903  
Phone: 44 1963 251383  
Fax: (972) 387-8148  
Fax: 44 1963 251510  
E-mail: info@rfm.com  
http://www.rfm.com  
RX6501-062905  
Page 3 of 10  
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.  
An incoming RF signal is first filtered by a narrow-band SAW filter, and is  
then applied to RFA1. The pulse generator turns RFA1 ON for 0.5 µs. The  
amplified signal from RFA1 emerges from the SAW delay line at the input  
to RFA2. RFA1 is now switched OFF and RFA2 is switched ON for 0.55 µs,  
amplifying the RF signal further. The ON time for RFA2 is usually set at 1.1  
times the ON time for RFA1, as the filtering effect of the SAW delay line  
stretches the signal pulse from RFA1 somewhat. As shown in the timing di-  
agram, RFA1 and RFA2 are never on at the same time, assuring excellent  
receiver stability. Note that the narrow-band SAW filter eliminates sampling  
sideband responses outside of the receiver passband, and the SAW filter  
and delay line act together to provide very high receiver ultimate rejection.  
ASH Receiver Theory of Operation  
Introduction  
RFM’s RX6500 series amplifier-sequenced hybrid (ASH) receivers are  
specifically designed for short-range wireless control and data communica-  
tion applications. The receivers provide robust operation, very small size,  
low power consumption and low implementation cost. All critical RF func-  
tions are contained in the hybrid, simplifying and speeding design-in. The  
ASH receiver can be readily configured to support a wide range of data  
rates and protocol requirements. The receiver features virtually no RF  
emissions, making it easy to certify to short-range (unlicensed) radio regu-  
lations.  
Amplifier-sequenced receiver operation has several interesting character-  
istics that can be exploited in system design. The RF amplifiers in an am-  
plifier-sequenced receiver can be turned on and off almost instantly,  
allowing for very quick power-down (sleep) and wake-up times. Also, both  
RF amplifiers can be off between ON sequences to trade-off receiver noise  
figure for lower average current consumption. The effect on noise figure  
can be modeled as if RFA1 is on continuously, with an attenuator placed in  
Amplifier-Sequenced Receiver Operation  
The ASH receiver’s unique feature set is made possible by its system ar-  
chitecture. The heart of the receiver is the amplifier- sequenced receiver  
section, which provides more than 100 dB of stable RF and detector gain  
without any special shielding or decoupling provisions. Stability is achieved  
by distributing the total RF gain over time. This is in contrast to a superhet-  
erodyne receiver, which achieves stability by distributing total RF gain over  
multiple frequencies.  
front of it with a loss equivalent to 10*log (RFA1 duty factor), where the  
10  
duty factor is the average amount of time RFA1 is ON (up to 50%). Since  
an amplifier-sequenced receiver is inherently a sampling receiver, the  
overall cycle time between the start of one RFA1 ON sequence and the  
start of the next RFA1 ON sequence should be set to sample the narrowest  
RF data pulse at least 10 times. Otherwise, significant edge jitter will be  
added to the detected data pulse.  
Figure 1 shows the basic block diagram and timing cycle for an amplifier-  
sequenced receiver. Note that the bias to RF amplifiers RFA1 and RFA2  
are independently controlled by a pulse generator, and that the two ampli-  
fiers are coupled by a surface acoustic wave (SAW) delay line, which has  
a typical delay of 0.5 µs.  
ASH Receiver Block Diagram & Timing Cycle  
Antenna  
Detector &  
Low-Pass  
Filter  
SAW  
Delay Line  
Data  
Out  
SAW Filter  
RFA1  
RFA2  
P1  
P2  
Pulse  
Generator  
RF Input  
RF Data Pulse  
tPW1  
tPRI  
P1  
tPRC  
RFA1 Out  
Delay Line  
Out  
tPW2  
P2  
Figure 1  
RF Monolithics, Inc.  
RFM Europe  
Phone: (972) 233-2903  
Phone: 44 1963 251383  
Fax: (972) 387-8148  
Fax: 44 1963 251510  
E-mail: info@rfm.com  
http://www.rfm.com  
RX6501-062905  
Page 4 of 10  
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.  
RX6501 ASH Receiver Block Diagram  
RFA1  
CN TRL1  
CN TRL0  
VCC1: Pin 2  
VCC2: Pin 16  
GND1: Pin 1  
GND2: Pin 10  
GND3: Pin 19  
17  
18  
Power  
Down  
Control  
Bias Control  
NC:  
Pin 8  
RREF: Pin 11  
CMPIN: Pin 6  
NC:  
NC:  
Pin 4  
Pin 12  
Antenna  
Log  
BBOUT  
3
RFIO  
20  
SAW  
CR Filter  
SAW  
Delay Line  
Low-Pass  
Filter  
RFA1  
RFA2  
Detector  
BB  
5
6
7
DS1  
RXDATA  
C BBO  
ESD  
9
LPFADJ  
Choke  
Ref  
Thld  
R LPF  
Threshold  
Control  
THLD1  
13  
11 RREF  
R TH1  
R REF  
Pulse Generator  
& RF Amp Bias  
PRATE 14  
R PR  
15 PWIDTH  
R PW  
Figure 2  
RX6500 Series ASH Receiver Block Diagram  
a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with  
a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/  
dB slope and peak-to-peak signal level are proportionately less. The de-  
tected signal is riding on a 1.1 Vdc level that varies somewhat with supply  
voltage, temperature, etc. BBOUT is coupled to the CMPIN pin or to an ex-  
ternal data recovery process (DSP, etc.) by a series capacitor. The correct  
value of the series capacitor depends on data rate, data run length, and  
other factors as discussed in the ASH Transceiver Designer’s Guide.  
Figure 2 is the general block diagram of the RX6500 series ASH receiver.  
Please refer to Figure 2 for the following discussions.  
Antenna Port  
The only external RF components needed for the receiver are the antenna  
and its matching components. Antennas presenting an impedance in the  
range of 35 to 72 ohms resistive can be satisfactorily matched to the RFIO  
pin with a series matching coil and a shunt matching/ESD protection coil.  
Other antenna impedances can be matched using two or three compo-  
nents. For some impedances, two inductors and a capacitor will be re-  
quired. A DC path from RFIO to ground is required for ESD protection.  
When the receiver is placed in the power-down (sleep) mode, the output  
impedance of BBOUT becomes very high. This feature helps preserve the  
charge on the coupling capacitor to minimize data slicer stabilization time  
when the receiver switches out of the sleep mode.  
Receiver Chain  
Data Slicers  
The output of the SAW filter drives amplifier RFA1. The output of RFA1  
drives the SAW delay line, which has a nominal delay of 0.5 µs.  
The CMPIN pin drives data slicer DS1, which convert the analog signal  
from BBOUT back into a digital stream. Data slicer DS1 is a capacitively-  
coupled comparator with provisions for an adjustable threshold. The  
threshold, or squelch, offsets the comparator’s slicing level from 0 to 90  
mV, and is set with a resistor between the RREF and THLD1 pins. This  
threshold allows a trade-off between receiver sensitivity and output noise  
density in the no-signal condition. For best sensitivity, the threshold is set  
to 0. In this case, noise is output continuously when no signal is present.  
This, in turn, requires the circuit being driven by the RXDATA pin to be able  
to process noise (and signals) continuously.  
The second amplifier, RFA2, provides 51 dB of gain below saturation. The  
output of RFA2 drives a full-wave detector with 19 dB of threshold gain. The  
onset of saturation in each section of RFA2 is detected and summed to pro-  
vide a logarithmic response. This is added to the output of the full-wave de-  
tector to produce an overall detector response that is square law for low  
signal levels, and transitions into a log response for high signal levels. This  
combination provides excellent threshold sensitivity and more than 70 dB  
of detector dynamic range. In combination with the 30 dB of AGC range in  
RFA1, more than 100 dB of receiver dynamic range is achieved.  
This can be a problem if RXDATA is driving a circuit that must “sleep” when  
data is not present to conserve power, or when it its necessary to minimize  
false interrupts to a multitasking processor. In this case, noise can be great-  
ly reduced by increasing the threshold level, but at the expense of sensitiv-  
ity. The best 3 dB bandwidth for the low-pass filter is also affected by the  
threshold level setting of DS1. The bandwidth must be increased as the  
threshold is increased to minimize data pulse-width variations with signal  
amplitude.  
The detector output drives a gyrator filter. The filter provides a three-pole,  
0.05 degree equiripple low-pass response with excellent group delay flat-  
ness and minimal pulse ringing. The 3 dB bandwidth of the filter can be set  
from 4.5 kHz to 1.8 MHz with an external resistor.  
The filter is followed by a base-band amplifier which boosts the detected  
signal to the BBOUT pin. When the receiver RF amplifiers are operating at  
RF Monolithics, Inc.  
RFM Europe  
Phone: (972) 233-2903  
Phone: 44 1963 251383  
Fax: (972) 387-8148  
Fax: 44 1963 251510  
E-mail: info@rfm.com  
http://www.rfm.com  
RX6501-062905  
Page 5 of 10  
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.  
Receiver Pulse Generator and RF Amplifier Bias  
Sleep and Wake-Up Timing  
The receiver amplifier-sequence operation is controlled by the Pulse Gen-  
erator & RF Amplifier Bias module, which in turn is controlled by the  
PRATE and PWIDTH input pins, and the Power Down (sleep) Control Sig-  
nal from the Bias Control function.  
The maximum transition time from the receive mode to the power-down  
(sleep) mode t is 10 µs after CNTRL1 and CNTRL0 are both low (1 µs  
RS  
fall time).  
The maximum transition time t from the sleep mode to the receive mode  
SR  
In the low data rate mode, the interval between the falling edge of one  
RFA1 ON pulse to the rising edge of the next RFA1 ON pulse tPRI is set  
by a resistor between the PRATE pin and ground. The interval can be ad-  
justed between 0.1 and 5 µs. In the high data rate mode (selected at the  
PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50%  
duty cycle. In this case, the start-to-start period tPRC for ON pulses to  
RFA1 are controlled by the PRATE resistor over a range of 0.1 to 1.1 µs.  
is 3*t  
, where t  
is the BBOUT-CMPIN coupling-capacitor time con-  
BBC  
BBC  
stant. When the operating temperature is limited to 60 °C, the time required  
to switch from sleep to receive is dramatically less for short sleep times, as  
less charge leaks away from the BBOUT- CMPIN coupling capacitor.  
Pulse Generator Timing  
In the low data rate mode, the interval t  
ON pulse to the first RF amplifier and the rising edge of the next ON pulse  
to the first RF amplifier is set by a resistor R between the PRATE pin and  
ground. The interval can be adjusted between 0.1 and 5 µs with a resistor  
between the falling edge of an  
PRI  
In the low data rate mode, the PWIDTH pin sets the width of the ON pulse  
PR  
t
to RFA1 with a resistor to ground (the ON pulse width t  
to RFA2  
PW1  
PW2  
is set at 1.1 times the pulse width to RFA1 in the low data rate mode). The  
ON pulse width t can be adjusted between 0.55 and 1 µs. However,  
in the range of 51 K to 2000 K. The value of the R is given by:  
PR  
PW1  
R
= 404* t  
+ 10.5, where t  
is in µs, and R is in kilohms  
when the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF  
amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data  
rate operation. In this case, the RF amplifiers are controlled by the PRATE  
resistor as described above.  
PR  
PRI  
PRI PR  
In the high data rate mode (selected at the PWIDTH pin) the receiver RF  
amplifiers operate at a nominal 50%-50% duty cycle. In this case, the peri-  
od t  
from the start of an ON pulse to the first RF amplifier to the start of  
PRC  
the next ON pulse to the first RF amplifier is controlled by the PRATE re-  
sistor over a range of 0.1 to 1.1 µs using a resistor of 11 K to 220 K. In this  
Both receiver RF amplifiers are turned off by the Power Down Control Sig-  
nal, which is invoked in the sleep mode.  
case R is given by:  
PR  
Receiver Mode Control  
R
= 198* t  
- 8.51, where t  
is in µs and R is in kilohms  
PRC PR  
PR  
PRC  
The receiver operating modes – receive and power-down (sleep), are con-  
trolled by the Bias Control function, and are selected with the CNTRL1 and  
CNTRL0 control pins. Setting CNTRL1 and CNTRL0 both high place the  
unit in the receive mode. Setting CNTRL1 and CNTRL0 both low place the  
unit in the power-down (sleep) mode. CNTRL1 and CNTRL0 are CMOS  
compatible inputs. These inputs must be held at a logic level; they cannot  
be left unconnected.  
In the low data rate mode, the PWIDTH pin sets the width of the ON pulse  
to the first RF amplifier t with a resistor R to ground (the ON pulse  
PW1  
PW  
width to the second RF amplifier t  
is set at 1.1 times the pulse width to  
PW2  
the first RF amplifier in the low data rate mode). The ON pulse width t  
PW1  
can be adjusted between 0.55 and 1 µs with a resistor value in the range  
of 200 K to 390 K. The value of R  
is given by:  
PW  
R
= 404* t  
- 18.6, where t  
is in µs and R  
is in kilohms  
PW  
Receiver Event Timing  
PW  
PW1  
PW1  
However, when the PWIDTH pin is connected to Vcc through a 1 M resis-  
tor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating  
high data rate operation. In this case, the RF amplifiers are controlled by  
the PRATE resistor as described above.  
Receiver event timing is summarized in Table 1. Please refer to this table  
for the following discussions.  
Turn-On Timing  
The maximum time t required for the receive function to become opera-  
PR  
LPF Group Delay  
tional at turn on is influenced by two factors. All receiver circuitry will be op-  
erational 5 ms after the supply voltage reaches 2.2 Vdc. The BBOUT-  
CMPIN coupling-capacitor is then DC stabilized in 3 time constants  
The low-pass filter group delay is a function of the filter 3 dB bandwidth,  
which is set by a resistor R  
to ground at the LPFADJ pin. The minimum  
LPF  
3 dB bandwidth f  
hms.  
= 1445/R , where f  
is in kHz, and R  
is in kilo-  
LPF  
(3*  
). The total turn-on time to stable receiver operation for a 10 ms  
LPF  
LPF  
LPF  
tBBC  
power supply rise time is:  
The maximum group delay t  
= 1750/f  
= 1.21*R , where t  
is in  
FGD  
t
= 15 ms + 3*t  
FGD  
LPF  
LPF  
PR  
BBC  
µs, f  
in kHz, and R  
in kilohms.  
LPF  
LPF  
RF Monolithics, Inc.  
RFM Europe  
Phone: (972) 233-2903  
Phone: 44 1963 251383  
Fax: (972) 387-8148  
Fax: 44 1963 251510  
E-mail: info@rfm.com  
http://www.rfm.com  
RX6501-062905  
Page 6 of 10  
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.  
Receiver Event Timing, 3.0 Vdc, -40 to +85 °C  
Event  
Symbol  
Time  
+ 15 ms  
BBC  
Min/Max  
Test Conditions  
Notes  
Turn On to Receive  
t
t
t
3*t  
max  
10 ms supply voltage rise time  
time until receiver operational  
PR  
SR  
RS  
Sleep to RX  
3*t  
max  
max  
1 µs CNTRL0/CNTROL 1 rise times  
time until receiver operational  
BBC  
RX to Sleep  
10 µs  
1 µs CNTRL0/CNTROL 1 fall times time until receiver is in power-down mode  
PRATE Interval  
t
0.1 to 5 µs  
range  
range  
range  
range  
range  
max  
low data rate mode  
low data rate mode  
low data rate mode  
high data rate mode  
high data rate mode  
user selected mode  
user selected mode  
user selected mode  
user selected mode  
user selected mode  
user selected  
PRI  
PWIDTH RFA1  
t
t
0.55 to 1 µs  
PW1  
PW2  
PWIDTH RFA2  
1.1*t  
PW1  
PRATE Cycle  
t
0.1 to 1.1 µs  
PRC  
PWIDTH High (RFA1 & RFA2)  
LPF Group Delay  
LPF 3 dB Bandwidth  
BBOUT-CMPIN Time Constant  
t
0.05 to 0.55 µs  
PWH  
t
1750/f  
t
in µs, f  
in kHz  
LPF  
FGD  
LPF  
FGD  
f
1445/R  
min  
f
in kHz, R in kilohms  
LPF  
user selected  
LPF  
LPF  
LPF  
t
0.064*C  
min  
t
in µs, C in pF  
BBO  
user selected  
BBC  
BBO  
BBC  
Table 1  
RF Monolithics, Inc.  
RFM Europe  
Phone: (972) 233-2903  
Phone: 44 1963 251383  
Fax: (972) 387-8148  
Fax: 44 1963 251510  
E-mail: info@rfm.com  
http://www.rfm.com  
RX6501-062905  
Page 7 of 10  
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.  
Pin Descriptions  
Pin  
Name  
Description  
1
GND1  
VCC1  
GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces.  
VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF capacitor,  
which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information.  
2
3
4
RFA1  
NC  
This pin should be left unconnected.  
BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor C  
for internal  
BBO  
data slicer operation. The time constant t  
for this connection is:  
BBC  
t
= 0.064*C  
, where t  
is in µs and C  
is in pF  
BBO  
BBC  
BBO  
BBC  
A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between t  
and  
BBC  
1.8*t  
with variations in supply voltage, temperature, etc. The optimum time constant in a given circumstance will  
BBC  
depend on the data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. A com-  
mon criteria is to set the time constant for no more than a 20% voltage droop during SP . For this case:  
MAX  
C
= 70*SP  
, where SP  
is the maximum signal pulse width in µs and C  
is in pF  
BBO  
BBO  
MAX  
MAX  
5
BBOUT  
The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output  
impedance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal  
changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and  
peak-to-peak signal level are proportionately less. The signal at BBOUT is riding on a 1.1 Vdc value that varies somewhat  
with supply voltage and temperature, so it should be coupled through a capacitor to an external load. A load impedance of  
50 K to 500 K in parallel with no more than 10 pF is recommended. When an external data recovery process is used with  
AGC, BBOUT must be coupled to the external data recovery process and CMPIN by separate series coupling capacitors.  
The AGC reset function is driven by the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the  
output impedance of this pin becomes very high, preserving the charge on the coupling capacitor.  
This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input impedance  
of this pin is 70 K to 100 K.  
6
CMPIN  
RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available from  
this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin becomes high  
impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite logic state when this pin  
is high impedance. If a pull-up resistor is used, the positive supply end should be connected to a voltage no greater than  
Vcc + 200 mV.  
7
8
RXDATA  
NC  
This pin may be left unconnected or may be grounded.  
This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R  
ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth f  
MHz. The resistor value is determined by:  
between this pin and  
from 4.5 kHz to 1.8  
LPF  
LPF  
R
= 1445/ f , where R  
is in kilohms, and f  
is in kHz  
LPF  
9
LPFADJ  
LPF  
LPF  
LPF  
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between f  
and 1.3*  
LPF  
f
with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase  
LPF  
response. The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting.  
10  
11  
12  
GND2  
RREF  
NC  
GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.  
RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1%  
resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less  
than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less  
that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF.  
This pin should be left unconnected.  
The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor R  
to RREF. The threshold is  
TH1  
increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The acceptable  
range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:  
13  
THLD1  
R
= 1.11*V, where R  
is in kilohms and the threshold V is in mV  
TH1  
TH1  
A ±1% resistor tolerance is recommended for the THLD1 resistor.  
RF Monolithics, Inc.  
RFM Europe  
Phone: (972) 233-2903  
Phone: 44 1963 251383  
Fax: (972) 387-8148  
Fax: 44 1963 251510  
E-mail: info@rfm.com  
http://www.rfm.com  
RX6501-062905  
Page 8 of 10  
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.  
Pin  
Name  
Description  
The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to  
the first RF amplifier t  
is set by a resistor R between this pin and ground. The interval t  
can be adjusted between  
PRI  
PRI  
PR  
0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of R is given by:  
PR  
R
= 404* t  
+ 10.5, where t  
is in µs, and R is in kilohms  
PRI PR  
PR  
PRI  
A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifi-  
ers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period t from start-  
PRC  
14  
PRATE  
to-start of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resis-  
tor of 11 K to 220 K. In this case the value of R is given by:  
PR  
R
= 198* t  
- 8.51, where t  
is in µs and R is in kilohms  
PRC PR  
PR  
PRC  
A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional  
amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than  
5 pF to maintain stability.  
The PWIDTH pin sets the width of the ON pulse to the first RF amplifier t  
with a resistor R  
to ground (the ON pulse  
PW  
PW1  
width to the second RF amplifier t  
is set at 1.1 times the pulse width to the first RF amplifier). The ON pulse width t  
PW1  
PW2  
can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of R  
is given by:  
PW  
R
= 404* t  
- 18.6, where t  
is in µs and R  
is in kilohms  
PW  
PW  
PW1  
PW1  
15  
PWIDTH  
A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate  
at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are con-  
trolled by the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and  
this node to less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the  
1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode.  
VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capacitor, which  
may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor.  
16  
17  
VCC2  
CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive mode.  
CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a high-impedance input  
(CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or  
greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic  
high requires a maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be  
held at a logic level; it cannot be left unconnected.  
CNTRL1  
CNTRL0 is used with CNTRL1 to control the receiver modes. CNTRL0 is a high-impedance input (CMOS compatible). An  
input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a  
logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum  
source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic level; it can-  
not be left unconnected.  
18  
19  
20  
CNTRL0  
GND3  
RFIO  
GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.  
RFIO is the receiver RF input pin. This pin is connected directly to the SAW filter transducer. Antennas presenting an  
impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series matching coil and  
a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For  
some impedances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD pro-  
tection.  
RF Monolithics, Inc.  
RFM Europe  
Phone: (972) 233-2903  
Phone: 44 1963 251383  
Fax: (972) 387-8148  
Fax: 44 1963 251510  
E-mail: info@rfm.com  
http://www.rfm.com  
RX6501-062905  
Page 9 of 10  
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.  
.435  
.370  
.345  
.305  
.265  
.225  
.185  
.145  
.105  
.065  
.09  
0.000  
Dimensions in inches.  
SM-20H PCB Pad Layout  
Note: Specifications subject to change without notice.  
RF Monolithics, Inc.  
RFM Europe  
Phone: (972) 233-2903  
Phone: 44 1963 251383  
Fax: (972) 387-8148  
Fax: 44 1963 251510  
E-mail: info@rfm.com  
http://www.rfm.com  
RX6501-062905  
Page 10 of 10  
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.  
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