Power Supply Considerations for Atmel®
Capacitive-touch ICs
1. Introduction
This application note discusses the dedicated power supply arrangement for Atmel
capacitive touch-sensitive integrated circuits (QT™ ICs).
Power Supply
Considerations
for QT ICs
2. Why Do I Need a Special Power Supply?
QT ICs derive their internal reference from the Vdd power supply. It is therefore
important to ensure that Vdd is stable and free of electrical noise. The proprietary drift
compensation algorithms of the QT IC are designed to overcome long-term drift.
Nevertheless, transient spikes of ±±1 mV can cause erratic behaviour such as false
key activations, stuck keys, and loss of touch detection.
ApplicationNote
QTAN0015
A simple and inexpensive regulator circuit eliminates these potential problems.
3. General Recommendations
Do:
• Use a dedicated regulator to power the QT IC.
• Place the regulator as close as possible to the QT IC.
• Use a GROUND plane under the regulator and under the Vss pins of the QT IC.
• For PCBs with a GROUND plane layer, extend the plane under communications
circuits, any oscillator or crystal, and also decoupling capacitors.
• Place a 1.± µF decoupling capacitor in close physical proximity to each Vdd pin.
Don’t:
• Share Vdd with other logic circuitry or light-emitting diodes (LED).
• Use long power and GROUND traces between the regulator and the QT IC.
• Extend the GROUND plane beneath the sense pins of the QT IC, Cs capacitors,
Rs resistors, or any sense line traces.
4. Low Drop-out (LDO) Regulator
QT ICs are optimized for low power operation. To conserve power, the device mostly
operates in an ultra-low-power sleep mode in which minimal current (µA) is drawn.
Periodically, the QT IC wakes up to perform sampling and communication routines
that consume mA of current.
The poor load step response of some LDO regulators is well-known, often resulting in
significant output transients when the load increases from µA to mA, causing erratic
sensor operation. Care must be taken in the selection and use of LDO regulators.
Figure 4-± shows the circuit for a Seiko S-8±7 series LDO regulator.
±1713A–AT42–±1/18
