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EZ80F915050MOD

型号：

EZ80F915050MOD

描述：

eZ80F91模块结构紧凑，高性能的以太网模块[ eZ80F91 Module compact, high-performance Ethernet module ]

品牌：

ZILOG[ ZILOG, INC. ]

页数：

34 页

PDF大小：

505 K

下载PDF手册
eZ80F915050MOD  
eZ80F91 Module  
Product Specification  
PS019310-0904  
PRELIMINARY  
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126  
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com  
This publication is subject to replacement by a later edition. To determine whether  
a later edition exists, or to request copies of publications, contact:  
ZiLOG Worldwide Headquarters  
532 Race Street  
San Jose, CA 95126  
Telephone: 408.558.8500  
Fax: 408.558.8300  
www.ZiLOG.com  
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other  
products and/or service names mentioned herein may be trademarks of the companies with which  
they are associated.  
Document Disclaimer  
©2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,  
applications, or technology described is intended to suggest possible uses and may be superseded.  
ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF  
ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS  
DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY  
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR  
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval  
ZiLOG, use of information, devices, or technology as critical components of life support systems is  
not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document  
under any intellectual property rights.  
PS019310-0904  
P R E L I M I N A R Y  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
iii  
Revision History  
Each instance in Table 1 reflects a change to this document from its previous revi-  
sion. To see more detail, click the appropriate link in the table.  
Table 1. Revision History of this Document  
Revision  
Level  
Page  
#
Date  
Section  
Description  
July 2004  
10  
Formatted to current publication standards  
All  
12  
Ethernet PHY and Part number change to AMD MII.  
RJ45 Connector  
section  
Bill of Materials for Part number change to internal crystal at jumper  
22  
the eZ80F91  
Module  
location Y3.  
PS019310-0904  
P R E L I M I N A R Y  
Revision History  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
iv  
Table of Contents  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii  
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v  
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi  
The eZ80F91 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
eZ80F91 Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Peripheral Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Ethernet PHY and RJ45 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Fast Buffer (U10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
IrDA Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Module Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
PS019310-0304  
P R E L I M I N A R Y  
Table of Contents  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
v
List of Figures  
Figure 1. eZ80F91 Module Functional Block Diagram . . . . . . . . . . . . . . . . . . . 3  
Figure 2. eZ80F91 Module Peripheral Bus Connector Pin Configuration—JP1 4  
Figure 3. eZ80F91 Module I/O Connector Pin Configuration—JP2 . . . . . . . . . 8  
Figure 4. Bus Contention Without the eZ80F91 Module Fast Buffer Feature . 15  
Figure 5. Physical Dimensions of the eZ80F91 Module . . . . . . . . . . . . . . . . . 18  
Figure 6. eZ80F91 Module—Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Figure 7. eZ80F91 Module—Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Figure 8. eZ80F91 Module Schematic Diagram, #1 of 3—Connectors  
and Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Figure 9. eZ80F91 Module Schematic Diagram, #2 of 3—CPU and PHY . . . 26  
Figure 10. eZ80F91 Module Schematic Diagram, #3 of 3—Module Memory . . 27  
PS019310-0304  
P R E L I M I N A R Y  
List of Figures  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
vi  
List of Tables  
Table 1. Revision History of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii  
Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* . . . . . . . 5  
Table 3. eZ80F91 Module I/O Connector Pin Identification* . . . . . . . . . . . . . . . . 8  
Table 4. eZ80F91 Ethernet Module MII Resistor Configuration. . . . . . . . . . . . . 12  
Table 5. Flash Memory Programming Signals and Jumpers . . . . . . . . . . . . . . . 16  
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Table 7. Bill of Materials for the eZ80F91 Module . . . . . . . . . . . . . . . . . . . . . . . 22  
PS019310-0304  
P R E L I M I N A R Y  
List of Tables  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
1
The eZ80F91 Module  
The eZ80F91 Module is a compact, high-performance Ethernet module specially  
designed for the rapid development and deployment of embedded systems  
requiring control and Internet/Intranet connectivity.  
This expandable module is powered by ZiLOG’s latest power-efficient, high-  
speed, optimized pipeline architecture eZ80F91 microcontroller, a member of  
ZILOG’s family of eZ80Acclaim! Flash Microcontrollers.  
The eZ80F91 is a high-speed single-cycle instruction-fetch microcontroller, which  
can operate with a clock speed of 50MHz. It can operate in Z80-compatible  
addressing mode (64KB) or full 24-bit addressing mode (16MB).  
The rich peripheral set of the eZ80F91 Module makes it suitable for a variety of  
applications, including industrial control, IrDA connectivity, communication, secu-  
rity, automation, point-of-sale terminals, and embedded networking applications.  
Module Features  
•
Factory-default operating clock frequency at 50MHz  
•
•
•
•
•
•
•
•
10/100 Base-T Ethernet PHY with RJ45 connector  
512KB fast SRAM  
256KB on-chip Flash memory  
1MB off-chip NOR Flash memory  
Battery-backed Real-Time Clock  
I/O connector provides 32 general-purpose 5V-tolerant I/O pinouts  
ZiLOG’s industry-leading IrDA transceiver—ZiLOG ZHX1810  
Onboard connector provides I/O bus for external peripheral connections (IRQ,  
CS, 24 address, 8 data)  
•
•
•
•
Low-cost connection to carrier board via two 2x30pin headers  
Small footprint 63.5mm x 78.7mm  
3.3V power supply  
Standard operating temperature range: 0ºC to +70ºC  
PS019310-0904  
P R E L I M I N A R Y  
The eZ80F91 Module  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
2
eZ80F91 Controller Features  
•
•
•
•
The eZ80F91 device contains 256KB of Flash memory and 8KB of SRAM  
®
Single-cycle instruction fetch, high-performance, pipelined eZ80 CPU core  
10/100 Mbps Ethernet MAC with 8KB frame buffer  
Low power features including SLEEP mode, HALT mode, and selective peripher-  
al power-down control  
•
Two UARTs with independent baud rate generators and support for 9-bit opera-  
tion  
•
•
•
•
•
SPI with independent clock generator  
2
I C with independent clock generator  
Infrared Data Association (IrDA)-compliant infrared encoder/decoder  
®
New DMA-like eZ80 instructions for efficient block data transfer  
External interface with 4 chip selects, individual wait state generators, and an ex-  
ternal WAIT input pin — supports Intel- and Motorola-style buses  
•
•
Flexible-priority vectored interrupts (both internal and external) and interrupt con-  
troller  
Real-time clock with on-chip 32KHz oscillator, selectable 50/60Hz input, and sep-  
arate VDD pin for battery backup  
•
•
•
•
•
•
•
Four 16-bit Counter/Timers with prescalers and direct input/output drive  
Watch-Dog Timer  
32 bits of general-purpose I/O  
JTAG and ZDI debug interfaces  
144-pin LQFP package  
3.0–3.6V supply voltage with 5V tolerant inputs  
Standard operating temperature range: 0ºC to +70ºC  
Block Diagram  
Figure 1 provides a block diagram of the eZ80F91 Module.  
PS019310-0904  
P R E L I M I N A R Y  
The eZ80F91 Module  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
3
Figure 1. eZ80F91 Module Functional Block Diagram  
PS019310-0904  
P R E L I M I N A R Y  
The eZ80F91 Module  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
4
Pin Description  
Peripheral Bus Connector  
Figure 2 illustrates the pin layout of the 60-pin Peripheral Bus Connector (JP1) of  
®
the eZ80F91 Module. The eZ80 Development Platform, however, features a 50-  
pin connector. The eZ80F91 Module is designed to interface pin 60 of its JP1 con-  
®
nector to pin 50 of the eZ80 Development Platform’s JP1 connector so that pins  
®
1–10 of the eZ80F91 Module overlap the edge of the eZ80 Development Plat-  
form. Table 2 identifies the pins and their functions.  
Figure 2. eZ80F91 Module  
Peripheral Bus Connector Pin Configuration—JP1  
PS019310-0904  
P R E L I M I N A R Y  
Pin Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
5
Note:  
All signals with an overline are active Low. For example, B/W, for which  
WORD is active Low, and B/W, for which BYTE is active Low.  
Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification*  
Pull  
Pin # Symbol  
Up/Down* Signal Direction Comments  
1
2
3
4
5
6
7
Reserved  
Reserved  
Reserved  
Reserved  
TRSTN  
Input  
Input  
Reset for On-Chip Instrumentation (OCI).  
Reserved  
F91_WE  
PU 10KΩ  
A Low enables a Write to on-chip Flash  
memory. If this pin is unconnected, on-chip  
Flash memory is write-protected.  
8
Reserved  
GND  
9
V
/Ground (0V).  
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
V
3.3V supply input pin.  
CC  
A6  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
A0  
A10  
A3  
GND  
V
/Ground (0V).  
SS  
V
3.3V supply input pin.  
CC  
A8  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
A7  
A13  
A9  
A15  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019310-0904  
P R E L I M I N A R Y  
Pin Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
6
Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* (Continued)  
Pull  
Pin # Symbol  
Up/Down* Signal Direction Comments  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
A14  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
A18  
A16  
A19  
GND  
A2  
V
/Ground (0V).  
SS  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
A1  
A11  
A12  
A4  
A20  
A5  
A17  
Reserved  
DIS_Flash  
PU 10KΩ  
Input  
A Low disables onboard Flash memory.  
Flash is enabled if DIS_Flash is not  
connected; CMOS Input 3.3V (5V tolerant).  
37  
38  
39  
40  
41  
42  
43  
44  
45  
A21  
Bidirectional  
V
3.3V supply input pin.  
CC  
A22  
A23  
CS0  
CS1  
CS2  
D0  
Bidirectional  
Bidirectional  
Output  
Output  
Output  
PU 4kΩ  
PU 4kΩ  
Bidirectional  
Bidirectional  
D1  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019310-0904  
P R E L I M I N A R Y  
Pin Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
7
Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* (Continued)  
Pull  
Pin # Symbol  
Up/Down* Signal Direction Comments  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
D2  
PU 4kΩ  
PU 4kΩ  
PU 4kΩ  
PU 4kΩ  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
D3  
D4  
D5  
GND  
D7  
V
V
/Ground (0V).  
/Ground (0V).  
SS  
PU 4kΩ  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
D6  
MREQ  
IORQ  
GND  
RD  
SS  
Bidirectional  
Bidirectional  
Output  
WR  
INSTRD  
BUSACK  
BUSREQ  
Output  
PU 2kΩ  
Input  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
I/O Connector  
Figure 3 illustrates the pin layout of the 60-pin I/O Connector (JP2) of the eZ80F91  
®
Module. The eZ80 Development Platform, however, features a 50-pin connector.  
The eZ80F91 Module is designed to interface pin 60 of its JP2 connector to pin 50  
®
of the eZ80 Development Platform’s JP2 connector so that pins 1–10 of the  
®
eZ80F91 Module overlap the edge of the eZ80 Development Platform  
identifies the pins and their functions.  
. Table 3  
PS019310-0904  
P R E L I M I N A R Y  
Pin Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
8
Figure 3. eZ80F91 Module  
I/O Connector Pin Configuration—JP2  
Table 3. eZ80F91 Module I/O Connector Pin Identification*  
Pull  
Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
1
2
3
4
PA7  
PA6  
PA5  
PA4  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019310-0904  
P R E L I M I N A R Y  
Pin Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
9
Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued)  
Pull Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
5
PA3  
PA2  
PA1  
PA0  
Bidirectional  
6
Bidirectional  
7
Bidirectional  
8
Bidirectional  
9
V
3.3V supply input pin.  
V /Ground (0V).  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
GND  
PB7  
PB6  
PB5  
PB4  
PB3  
PB2  
PB1  
PB0  
GND  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC0  
PD7  
PD6  
SS  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
V
/Ground (0V).  
SS  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019310-0904  
P R E L I M I N A R Y  
Pin Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
10  
Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued)  
Pull Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
V /Ground (0V).  
SS  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
GND  
PD5  
Bidirectional  
PD4  
PD 4kΩ  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Output  
PD3  
PD2  
PD1  
PD0  
TDO  
JTAG Data Output pin.  
JTAG Data Input pin.  
TDI/ZDA  
GND  
Input  
V
/Ground (0V).  
SS  
TRIGOUT  
TCK/ZCL  
Output  
Active High trigger event indicator.  
PU 10KΩ Input  
JTAG Input. High on reset enables ZDI mode; Low on  
reset enables OCI debug.  
42  
43  
TMS  
PU 10KΩ Input  
JTAG Test Mode Select Input.  
RTC_V  
RTC supply. For proper operation of the eZ80F91  
Module, this pin must be connected to the same  
power source that powers the module (as is done on  
the ZiLOG development platform).  
DD  
44  
45  
46  
47  
48  
49  
EZ80CLK  
Output  
Synchronous CPU clock output.  
2
2
I CSCL  
PU 4kΩ  
PU 4kΩ  
Bidirectional  
I C Bus Clock.  
GND  
V
/Ground (0V).  
SS  
2
2
I CSDA  
Bidirectional  
Power  
I C Data Clock.  
V /Ground (0V).  
SS  
GND  
FlashWE  
PU 10KΩ Input  
A Low enables a Write to external Flash memory boot  
block area. If this pin is unconnected, the Flash  
memory boot block area is write-protected.  
50  
GND  
V
/Ground (0V).  
SS  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019310-0904  
P R E L I M I N A R Y  
Pin Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
11  
Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued)  
Pull Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
51  
CS3  
Output  
Used on the eZ80190, eZ80L92, eZ80F92, eZ80F93  
devices and connected to the CS8900 EMAC.  
52  
DIS_IRDA  
PU 10KΩ Input  
A Low disables the onboard IRDA transceiver to use  
PC0/PC1 UART pins externally.  
53  
54  
RESET  
WAIT  
PU 2kΩ  
PU 2kΩ  
Bidirectional  
Input  
Reset Output from module or push-button reset.  
Driving the WAIT pin Low forces the CPU to provide  
additional clock cycles for an external peripheral or  
external memory to complete its Read or Write opera-  
tion.  
55  
56  
57  
V
3.3V supply input pin.  
CC  
GND  
V
/Ground (0V).  
SS  
HALT_SLP  
Output, Active A Low on this pin indicates that the CPU enters either  
Low  
HALT or SLEEP mode because of execution of either  
a HALT or SLP instruction.  
58  
NMI  
PU 10KΩ SchmittTrigger The NMI input is a higher priority input than the  
Input, Active  
Low  
maskable interrupts. It is always recognized at the  
end of an instruction, regardless of the state of the  
interrupt enable control bits. This input includes a  
Schmitt trigger to allow RC rise times. This external  
NMI signal is combined with an internal NMI signal  
generated from the WDT block before being con-  
nected to the NMI input of the CPU.  
59  
60  
V
3.3V supply input pin.  
CC  
Reserved  
NC  
Reserved—No Connection.  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS019310-0904  
P R E L I M I N A R Y  
Pin Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
12  
Onboard Component Description  
Logic-Level I/Os  
The I/O connector features 32 general-purpose 3.3V CMOS I/O pins that can be  
used as outputs or inputs interfacing to external logic. All I/Os are 5V tolerant.  
Some of the General-Purpose I/O pins support dual mode functions (SPI, Timer I/O,  
UARTs and bit I/O with edge- or level-triggered interrupt functions on each pin). For  
more information on eZ80F91 dual modes, please refer to the eZ80F91 Product  
Specification (PS0192).  
Onboard Battery Backup  
An onboard Panasonic VL-1220-1VC 3V Lithium battery powers the 32kHz Real-  
Time Clock when external power is removed. The battery is charged through  
diode CR1 and resistor R28 when external power is applied to the board.  
Ethernet PHY and RJ45 Connector  
The eZ80F91 Ethernet Module contains Advanced Micro Devices’ Am79C874  
Media-Independent Interface (MII) and a HALO RJ45 with integrated magnetics  
(transformer and common-mode chokes) and two LED indicators.  
The MII enables different modes of Ethernet communication, configurable by  
resistors R19, R21, R23, and R24. The eZ80F91 Ethernet Module is shipped with  
all four resistors installed. Table 4, which lists the available resistor settings, is  
excerpted from the Am79C874 data sheet published by AMD.  
Table 4. eZ80F91 Ethernet Module MII Resistor Configuration  
R24  
R19  
R23  
R21  
Full-  
ANEG (Tech[2]) (Tech[1]) (Tech[0]) Speed Duplex ANEG-EN Capabilities  
ANEG  
1
1
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
OUT  
IN  
Yes  
No  
Yes  
No  
No  
No  
No  
All  
Disabled  
Disabled  
Disabled  
10HD  
100HD  
IN  
OUT  
No  
No  
Notes:  
1. MII Register 0 (Speed and Duplex Bits) must be set by a MAC to achieve a link.  
2. When autonegotiation is enabled, these bits can be written but will be ignored by PHY.  
3. The advertised abilities of MII Register 4 cannot exceed the abilities of MII Register 1. Autonegotiation should  
always be enabled.  
PS019310-0904  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
13  
Table 4. eZ80F91 Ethernet Module MII Resistor Configuration (Continued)  
R19 R23 R21 Full-  
R24  
ANEG (Tech[2]) (Tech[1]) (Tech[0]) Speed Duplex ANEG-EN Capabilities  
ANEG  
IN  
IN  
OUT  
IN  
OUT  
IN  
No  
Yes  
No  
No  
Yes  
No  
No  
No  
100HD  
All  
Disabled  
Disabled  
Disabled  
Disabled  
Disabled  
Enabled  
Enabled  
Enabled  
Enabled  
Enabled  
Enabled  
Enabled  
Enabled  
1
1
IN  
OUT  
OUT  
OUT  
OUT  
IN  
IN  
IN  
OUT  
IN  
No  
10FD  
IN  
OUT  
OUT  
IN  
No  
No  
No  
100FD  
100FD  
None  
IN  
OUT  
IN  
No  
No  
No  
2
2
2
2
2
2
2
3
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
Notes:  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
IN  
IN  
OUT  
IN  
10HD  
IN  
OUT  
OUT  
IN  
100HD  
100HD, 10HD  
None  
IN  
OUT  
IN  
OUT  
OUT  
OUT  
OUT  
IN  
OUT  
IN  
10FD/HD  
100FD/HD  
All  
OUT  
OUT  
OUT  
1. MII Register 0 (Speed and Duplex Bits) must be set by a MAC to achieve a link.  
2. When autonegotiation is enabled, these bits can be written but will be ignored by PHY.  
3. The advertised abilities of MII Register 4 cannot exceed the abilities of MII Register 1. Autonegotiation should  
always be enabled.  
Ethernet LEDs  
The Ethernet connection is provided by the HALO RJ45 connector. It contains two  
green LEDs that are located next to each other on the eZ80F91 Module. When  
PHY is receiving data, the left LED is on. When the PHY is transmitting data, the  
right LED is on.  
Fast Buffer (U10)  
The eZ80F91 Module’s fast buffer (see Figure 1 on page 3) exists to prevent bus  
contention that will occur because of slow turn-off time of the module’s external  
Flash and the fast bus turn-around time of the eZ80F91 (generic feature of the  
®
eZ80 family when it is used in native mode).  
Below is a short explanation of the problem related to bus contention when using  
®
eZ80 family of the microprocessors in native eZ80 mode. Refer to Figure 4 on  
PS019310-0904  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
14  
page 15 while reading the following discussion. Also see the eZ80F91 Product  
Specification (PS0192) for further details.  
Bus contention occurs when two or more devices drive a common bus. The  
eZ80F91's CS0 drives the Flash CE. After the access to Flash, CS0 is driven High  
a maximum of 8.8ns after the next rising edge of the Clock (T6, Figure 4). The  
Flash turn-off time (T ) is 25ns, which is the time from OE or CE going High to  
OD  
the Flash output drivers going into High-Z mode. In other words, after the end of  
the eZ80F91 Read access to Flash, it takes 8.8ns+25ns = 33.8ns before Flash  
stops driving the data bus. At this point, the eZ80F91 device is already well into  
the next bus cycle.  
Assume that the next cycle is Memory Write. During the Memory Write cycle, Data  
(output) from the eZ80F91 device is valid not later than T3 = 7.5ns, and the Write  
pulse is asserted not later than 4.5ns after the falling edge of the Clock (14.5ns  
from the Rising edge if Clock is 50MHz). It means that during T  
= (33.8ns –  
CON  
7.5ns) = 26.3ns; two devices drive the common Data Bus—the eZ80F91 device  
and Flash. In turn, data that is being written during the Write operation might be  
corrupted. The part used to isolate a slow Flash data bus from a fast eZ80F91 bus  
has 5.5ns turn-off time, which reduces 25ns part of the T  
to 5.5ns. As a result,  
CON  
bus contention still occurs, but its duration is not 26.3ns, as the following equation  
shows:  
Time of contention = (8.8ns - 7.5ns + 5.5ns) = 6.8ns  
Data being written is not corrupted because the Write pulse is not yet asserted.  
PS019310-0904  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
15  
Figure 4. Bus Contention Without the eZ80F91 Module Fast Buffer Feature  
Memory  
The eZ80F91 Module contains external Flash memory, and the eZ80F91 MCU  
contains internal Flash memory. To allow Read/Write access to Flash memory on  
the eZ80F91 Module, there are two signals provided, on connectors JP1 and JP2.  
A jumper JP3 on the module enables programming of on-chip Flash.  
There is also a signal that duplicates the function of this jumper. Table 5 describes  
the states of the signals and the status of the jumper for different modes.  
PS019310-0904  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
16  
Table 5. Flash Memory Programming Signals and Jumpers  
Signal/Jumper  
Function  
Controls Read/Write access to eZ80F91 Module external Flash When Low, access  
memory is enabled  
Controls Write operations to the boot block of eZ80F91 Module When Low, Write is  
external Flash memory enabled  
State/Status  
DIS_FLASH  
FlashWE  
JP3  
Controls Write access to eZ80F91 MCU on-chip Flash memory When IN, Write is  
enabled  
F91_WE  
Controls Write access to eZ80F91 MCU on-chip Flash memory When Low, Write is  
enabled  
The eZ80F91 Module’s external Flash memory has an access time of 100ns. At  
least five wait states must be added to the cycle when accessing external Flash at  
the 50MHz clock speed. eZ80F91 MCU on-chip Flash is faster; its minimum  
access time is 60ns, which requires only three wait states at 50MHz.  
There is 512KB of fast SRAM on the eZ80F91 Module. Access time is 12ns,  
which requires one wait-state access. The eZ80F91 on-chip SRAM can be used  
with zero wait states.  
IrDA Transceiver  
An onboard IrDA transceiver (ZiLOG ZHX1810) is connected to PD0 (TX), PD1  
(RX), and PD2 (Shutdown, R_SD). The IrDA transceiver is of the LED type  
870nm Class 1.  
The receiver supply current is 90–150µA and the transmitter supply current is  
260mA when the LED is active.The IrDA transceiver is accessible via the IrDA  
controller attached to UART0 on the eZ80F91 device. The UART0 console and  
the IrDA transceiver cannot be used simultaneously.  
To use the UART0 for console or to save power, the transceiver can be disabled  
by the software or by an off-board signal when using the proper jumper selection.  
The transceiver is disabled by setting PD2 (IR_SD) High or by pulling the  
DIS_IRDA pin on the I/O connector Low. The shutdown is used for power savings.  
To enable the IrDA transceiver, DIS_IRDA is left floating and PD2 is set to Low.  
Reset Generator  
The onboard Reset Generator Chip performs reliable Power-On Reset. The chip  
generates a reset pulse with a duration of 200ms if the power supply drops below  
PS019310-0904  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
17  
2.93V. This reset pulse ensures that the board always starts in a defined condi-  
tion. The RESET pin on the I/O connector reflects the status of the RESET line. It  
is a bidirectional pin for resetting external peripheral components or for resetting  
the eZ80F91 Module with a low-impedance output (e.g. a 100-Ohm pushbutton).  
Serial Interface Ports  
The CPU contains two UARTs with programmable baud rate generators. UART0  
is connected to GPIO PD[0:7] on the I/O connector. UART1 is connected to GPIO  
PC[0:7] on the I/O connector.  
Do not connect an RS-232 interface without level shifters. There are no  
RS232-level shifters on the eZ80F91 Module.  
Note:  
Physical Dimensions  
The footprint of the eZ80F91 Module PCB is 63.5mmx78.7cm. With an RJ-45  
Ethernet connector, the overall height is 25mm. See Figure 5.  
PS019310-0904  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
18  
16.5 mm  
56.0 mm  
eZ80F91 MODULE  
JP1  
JP2  
2
1
1
R15  
R23  
R16  
R24  
R25  
R14  
R21  
R13  
R19  
R28  
U6  
+
P2  
R17  
R18  
R36  
R22  
R20  
CR1  
JP3  
ISO  
VL1  
U8  
Y2  
78.7 mm  
U5  
C22  
U1  
R37  
U4  
Y3  
C12  
C11  
R3  
C3  
R10  
R6  
U2  
C1  
C42  
R29  
U3  
31.8 mm  
63.5 mm  
Figure 5. Physical Dimensions of the eZ80F91 Module  
PS019310-0904  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
19  
Figure 6 illustrates the top layer silkscreen of the eZ80F91 Module.  
JP1  
JP2  
eZ80F91 MODULE  
2
1
1
R15  
R23  
R16  
R24  
R25  
R14  
R21  
R13  
R19  
R28  
U6  
+
P2  
R17  
R18  
R36  
R22  
R20  
CR1  
JP3  
ISO  
VL1  
U8  
Y2  
U5  
C22  
R37  
U1  
Y3  
U4  
C12  
C11  
R3  
C1  
C3  
R10  
R6  
C42  
U2  
R29  
U3  
Figure 6. eZ80F91 Module—Top Layer  
PS019310-0904  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
20  
Figure 7 illustrates the bottom layer silkscreen of the eZ80F91 Module.  
JP2  
JP1  
R35  
R34  
DJP 2002  
1
2
C4  
C7  
C16  
C14  
C39  
C51  
C50  
R11  
R33  
R32  
C15  
R31  
C17  
C49  
C48  
C44  
C45  
C47  
C46  
C34  
C35  
C26  
C33  
C29  
C27  
U9  
L1  
C32  
C9  
C38  
C28  
C5  
R26  
C23  
R8  
R7  
R2  
C6  
C37  
R1  
R30  
R12  
R5  
C41  
MADE IN U.S.A.  
ZiLOG FAB: 98C0879-001 REV A  
C2  
Figure 7. eZ80F91 Module—Bottom Layer  
Absolute Maximum Ratings  
Stresses greater than those listed in Table 6 can cause permanent damage to the  
device. These ratings are stress ratings only. Operation of the device at any con-  
dition outside those indicated in the operational sections of these specifications is  
not implied. Exposure to absolute maximum rating conditions for extended peri-  
ods may affect device reliability. For improved reliability, unused inputs should be  
tied to one of the supply voltages (VDD or VSS).  
Table 6. Absolute Maximum Ratings  
Parameter  
Min  
0
Max  
+70  
+85  
90%  
3.6  
Units  
ºC  
Standard operating temperature  
Storage temperature  
–45  
25%  
—
ºC  
Operating Humidity (RH @ 50ºC)  
Operating Voltage  
V
PS019310-0904  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
21  
Document Number Description  
The Document Control Number that appears in the footer of each page of this  
document contains unique identifying attributes, as indicated in the following  
table:  
PS  
Product Specification  
Unique Document Number  
Revision Number  
0193  
10  
0904  
Month and Year Published  
Change Log  
Rev  
Date  
Purpose  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
December 2002 Original issue  
January 2003  
February 2003  
June 2003  
Minor content revision  
Minor content revision  
Minor content revision  
Minor content revision  
Hyperlink correction  
June 2003  
August 2003  
December 2003 Typo correction  
December 2003 Correction to BOM  
March 2004  
Correction to schematic  
September 2004 Corrections to PHY section  
PS019310-0904  
P R E L I M I N A R Y  
Document Number Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
22  
Module Bill of Materials  
Table 7 lists the installed components of the eZ80F91 Module.  
Table 7. Bill of Materials for the eZ80F91 Module  
Jumper  
Part Number Part Name  
Qty. Location Manufacturer  
Prime Technologies  
Alliance Semi.  
98C0879-001 Fab, eZ80F91 Module, Rev. B  
1
—
35-0180-12  
35-0016-05  
35-0720-10  
35-0719-00  
ZHX1810  
IC, SRAM, 512Kx8, 12ns, 3V, 36-SOJ  
IC, 74LVC04, 3.3V, GATE, 14-SOIC  
IC, Flash, 1Mx8, 100ns, 3V, 40-TSSOP  
IC, MAX6328, RESET, SOT-23  
1
U8  
AS7C34096-12JC  
1
1
1
1
1
U1  
U9  
U3  
U2  
U4  
Texas Instruments  
SN74LVC04AD  
Micron Technologies  
MT28F008B3VG-10B  
Maxim Inc.  
MAX6328UR29-T  
IC, IR Transceiver, Low Profile  
ZiLOG Inc.  
ZHX1810MV115THTR  
35-0062-01  
IC, 74LCX32, LV, QUAD OR, 14-TSSOP  
Fairchild Semi.  
74LCX32MTC  
35-0022-01  
eZ80F91  
IC, AM7C874, PHY XCVR, 80QFP  
IC, eZ80F91, 50MHZ, 144VQFP  
IC, 74CBTLV3861PWR, 24-TSSOP  
1
1
1
U6  
U5  
AMD AM79C874VC  
ZiLOG Inc. eZ80F91  
35-0731-00  
U10  
Texas Instruments  
SN74CBTLV3861PWR  
48-1013-01  
17-2005-70  
17-2005-66  
Diode, TVS Array, XCVR Prot, 8-SOIC  
CAP, 1000pF, 50V, Ceramic Chip, 0603  
CAP, 0.1µF, 16V, Ceramic Chip, 0603  
1
U9  
Semtec  
LCDA15C-6  
15 C13, C14, Panasonic  
C31-43 ECJ-1VC1H561J  
28  
C2,10, Kemet Inc.  
C15-30, C0603C104K5RAC  
C44-53  
17-2005-54  
17-2005-83  
17-2005-63  
CAP, 0.01µF, 50V, Ceramic Chip, 0603  
CAP, 0.33µF, 16V, Ceramic Chip, 0603  
CAP, 560pF, 50V, Ceramic Chip, 0603  
1
1
1
C3  
C1  
C6  
Panasonic  
ECJ-1VB1C103K  
Panasonic  
ECJ-1VF1C334Z  
Panasonic  
ECJ-1VC1H563K  
PS019310-0904  
P R E L I M I N A R Y  
Document Number Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
23  
Table 7. Bill of Materials for the eZ80F91 Module (Continued)  
Jumper  
Part Number Part Name  
Qty. Location Manufacturer  
17-2001-03  
17-2001-05  
17-2001-20  
17-2001-01  
48-0051-00  
16-9005-33  
46-3001-03  
CAP, 12pF, 50V, Ceramic Chip, 0603  
4
2
1
1
1
1
C9, C11, Panasonic  
C12  
ECJ-1VC1H120J  
CAP, 22PF, 50V, CER CHIP, 0603  
CAP, 270PF, 50V, CER CHIP, 0603  
CAP, 5PF, 50V, CER CHIP, 0603  
DIODE, 1N5817, RCTFR  
C4, C7 PANASONIC  
ECJ-1VC1H220J  
C5  
PANASONIC  
ECJ-1VC1H271J  
C8  
PANASONIC  
ECJ-1VC1H050C  
CR1  
L1  
MOTOROLA  
1N5817  
INDUCTOR, 3.3µH, 20%, 1210 SMD  
Resistor, 10KΩ, 1%, 1/16W, 0603 SMT  
PANASONIC  
ELJ-PA3R3MF  
15 R3, 8, 10, Sprague  
R12-18, 420CK472X2PD  
R20, 25,  
29, 30, 37  
46-3000-00  
Resistor, 0Ω, 1%, 1/16W, 0603 SMT  
4
R19, 21,  
23, 24  
"
46-3000-71  
46-3000-35  
46-3000-02  
46-3000-32  
Resistor, 2.21KΩ, 1%, 1/16W, 0603 SMT  
Resistor, 68Ω, 1%, 1/16W, 0603 SMT  
RES, 2.2Ω, 1%, 1/16W, 0603 SMT  
RES, 49.9Ω, 1%, 1/16W, 0603 SMT  
2
1
1
4
R5, R6  
R3  
"
"
"
"
R4  
R11, 31,  
32, 33  
46-3000-63  
46-3000-56  
46-3001-34  
46-3000-47  
46-3000-51  
46-3001-75  
23-0000-25  
RES, 1KΩ, 1%, 1/16W, 0603 SMT  
RES, 499Ω,1%, 1/16W, 0603 SMT  
RES, 200KΩ, 1%, 1/16W, 0603 SMT  
RES, 221Ω, 1%, 1/16W, 0603 SMT  
RES, 332Ω, 1%, 1/16W, 0603 SMT  
RES, 10MΩ, 1%, 1/16W, 0603 SMT  
XTAL, 25.0000MHz, SER/RESN, HC49S  
1
1
1
1
2
1
1
R22  
R26  
"
"
"
"
"
"
R27  
R28  
R34, R35  
R38  
Y1  
CITIZEN  
HC49US25.000MABJ  
23-0000-50  
XTAL, 50.0000MHz, SER/RESN, HC49S  
1
Y2  
CITIZEN  
HC49US50.000MABJ  
PS019310-0904  
P R E L I M I N A R Y  
Document Number Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
24  
Table 7. Bill of Materials for the eZ80F91 Module (Continued)  
Jumper  
Part Number Part Name  
Qty. Location Manufacturer  
23-0006-00  
21-0907-01  
21-0055-02  
Internal crystal, 32.768KHz, SER/RESN,  
TF case  
1
1
2
Y3  
Fox NC-38  
Connector, RJ45, Fast jack,10/100 Base-T  
P2  
Halo Electronics  
HFJ11-2450E-L11  
Connector, HDR/PIN, .025SQ, double row  
JP1, JP2 Harwin  
(backside) M-20-976-3622  
PS019310-0904  
P R E L I M I N A R Y  
Document Number Description  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
Schematics  
25  
Figures 8 through 10 diagram the layout of the eZ80F91 Module. Ethernet circuiting devices are not loaded on the  
eZ80F91 Module. However, these devices appear in the following schematics for reference purposes.  
VCCVCC  
A[0..23]  
D[0..7]  
A[0..23]  
D[0..7]  
U1A  
Connector 1  
Connector 2  
JP2  
R1  
-F91_WP  
R2  
4.7K  
-F91_WE  
1
2
-F91_WP  
JP1  
-CS[0..3]  
4.7K  
-CS[0..3]  
PA7  
PA5  
PA3  
PA1  
VCC  
PB7  
PB5  
PB3  
PB1  
PA6  
PA4  
PA2  
PA0  
GND  
PB6  
PB4  
PB2  
PB0  
PC7  
PC5  
PC3  
PC1  
PD7  
GND  
PD4  
PD2  
PD0  
TDI  
TRIGOUT  
TMS  
EZ80CLK  
74LCX04  
TSSOP14  
1
3
5
7
9
2
4
6
8
1
3
5
7
9
2
4
6
8
IICSDA  
IICSCL  
IICSDA  
IICSCL  
R37  
10K  
IICSDA  
IICSCL  
-TRSTN  
-F91_WE  
GND  
A6  
A10  
GND  
A8  
A13  
A15  
A18  
A19  
A2  
A11  
A4  
VCC  
A0  
A3  
VCC  
A7  
A9  
A14  
A16  
GND  
A1  
A12  
A20  
A17  
-DIS_FLASH  
VCC  
A23  
-CS1  
D0  
D2  
D4  
GND  
D6  
-IOREQ  
-RD  
CLK_OUT  
EZ80CLK  
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
CLK_OUT  
VCC  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
-DIS_FLASH  
JP3  
-DIS_FLASH  
1
2
R3  
C1  
GND  
PC6  
-FLASHWE  
RTC_VDD  
PA[0..7]  
PC4  
PC2  
PC0  
PD6  
PD5  
PD3  
PD1  
TDO  
R4  
68R  
WR_EN  
-FLASHWE  
RTC_VDD  
PA[0..7]  
330nF  
U2  
2R7  
5
1
2
4
3
6
VCC  
LEDA  
TXD  
SD  
(MMA 0204)  
A5  
PB[0..7]  
PB[0..7]  
A21  
A22  
-CS0  
-CS2  
D1  
D3  
D5  
PD0  
PC[0..7]  
GND  
PC[0..7]  
IRDA_SD  
PD1  
TCK  
RTC_VDD  
IICSCL  
IICSDA  
-FLASHWE  
-CS3  
-RESET  
VCC  
PD[0..7]  
43  
45  
47  
PD[0..7]  
VCC  
RXD  
GND  
-RESE  
T
GND  
-RESET  
49  
-DIS_IRDA  
-WAIT  
GND  
-RD  
-WR  
D7  
51  
53  
55  
57  
59  
-RD  
-WR  
-MREQ  
ZHX181  
0
GND  
-HALT_SL  
VCC  
P
-IOREQ  
-MREQ  
-INSTRD  
R5  
2.2K  
R6  
2.2K  
-WR  
-BUSACK  
-INSTRD  
-BUSREQ  
-NMI  
-IOREQ  
-MREQ  
-INSTRD  
-WAIT  
-HALT_SL  
-WAIT  
-WAIT  
P
HEADER 30x2/SM  
HEADER 30x2/SM  
-HALT_SL  
P
-BUSREQ  
-BUSACK  
-BUSREQ  
VCC VCC  
-BUSREQ  
-BUSACK  
-NMI  
-NMI  
R7  
R8  
10K  
VCC  
10K  
U1B  
U4A  
TDI  
TD  
TRIGOUT  
1
TDI  
TDO  
O
R20  
10K  
3
4
3
2
TRIGOUT  
TCK  
TMS  
TCK  
TM  
S
74LCX04  
TSSOP14  
U1F  
74LCX32  
TSSOP14  
U4D  
-TRST  
N
-TRST  
N
12  
13  
R9  
4.7K  
VCC  
13  
12  
11  
VCC  
74LCX04  
TSSOP14  
74LCX32  
TSSOP14  
GND  
GND  
R12  
10K  
VCC  
R10  
10K  
U3  
U1C  
U4B  
DISABLE_IRDA  
-DIS_IRDA  
C2  
0.1µF  
-RESET  
5
6
4
5
2
RESET  
IRDA_SD  
open-drain  
6
PD2  
=
IR_SD  
74LCX04  
TSSOP14  
C3  
0.01µF  
74LCX32  
TSSOP14  
MAX6328UR29  
SOT-23-L3  
VCC  
alternative: Maxim MAX6802UR29D3  
VCC  
VCC  
GND  
GND  
GND  
Figure 8. eZ80F91 Module Schematic Diagram, #1 of 3—Connectors and Miscellaneous  
PS019310-0904  
P R E L I M I N A R Y  
Schematics  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
26  
GND  
D[0:7]  
A[0:23]  
U5  
VCC  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
39  
40  
41  
42  
43  
44  
45  
46  
1
2
3
4
5
8
9
10  
11  
12  
13  
16  
17  
18  
19  
20  
21  
24  
25  
26  
27  
28  
29  
30  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
R13 R14 R15  
R16 R17  
10K  
R18  
10K  
10K  
10K  
10K  
VCC  
U6  
R19  
R23  
0
10K 0.1%  
1
2
3
5
7
8
9
14  
15  
16  
17  
18  
19  
20  
43  
53  
54  
55  
56  
PCSB  
ISODEF  
ISO  
REFCLK  
BURN_IN  
RST  
PWRDN  
PHYAD4_0RXD-  
PHYAD3_10RXD+  
PHYAD2_10TXD++  
PHYAD1_10TXD-  
PHYAD0_10TXD--  
GPIO0_10TXD--  
GPIO1_TP125  
INTR  
TECH_SEL2  
TECH_SEL1  
TECH_SEL0  
ANEGA  
0
A8  
A9  
R21  
R24  
0
0
-WAIT  
-BUSREQ  
-NMI  
54  
57  
56  
-WAIT  
-BUSREQ  
-NMI  
WAIT  
A9  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
-RESET  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
R22 1K  
72  
61  
44  
45  
46  
47  
48  
57  
58  
BUSREQ  
NMI  
IBREF  
RPTR  
GND  
TM  
TCK  
TDI  
S
R25 10K  
66  
67  
69  
71  
TM  
S
TMS  
TCK  
TDI  
LEDSPD0_LEDBTA_FXSEL  
LECOL_SCRAMEN  
TCK  
TDI  
-TRSTN  
-TRST  
N
TRSTN  
-LEDR  
X
LEDRX_LEDSEL  
-RESET  
-F91_WP  
MDI0  
MDC  
RXCLK  
55  
21  
22  
30  
-RESE  
T
RESET  
WP  
MDIO  
MDC  
RXCLK  
LEDTX_LEDBTB  
144  
-F91_WP  
-LEDLNK  
LEDLNK_LED_10LNK  
LESPD1_LEDTXA_CLK25EN  
LEDDPX_LEDTXB  
CRS  
COL  
RXD3  
RXD2  
RXD1  
RXD0  
124  
125  
135  
137  
141  
140  
139  
138  
136  
131  
23  
24  
25  
26  
MII_CRS  
MII_COL  
RXD3  
RXD2  
RXD1  
RXD0  
TXD3  
126  
127  
128  
129  
130  
132  
142  
143  
MII_TXD3  
MII_TXD2  
MII_TXD1  
MII_TXD0  
MII_TXEN  
MII_TXER  
MII_MDC  
MII_MDIO  
RXER  
RXDV  
RXD  
RXD  
RXD  
RXD  
TXD2  
TXD1  
TXD0  
TXEN  
TXER  
MDC  
MDI0  
MII_RXER  
MII_RXDV  
MII_RXD3  
MII_RXD2  
MII_RXD1  
MII_RXD0  
MII_RXCLK  
MII_TXCLK  
C6  
GND  
3
2
1
0
C4  
RXDV  
RXER  
TXCLK  
18pF  
29  
31  
33  
62  
68  
67  
66  
69  
70  
74  
75  
77  
78  
RXDV  
RXER_RXD4  
TXCLK_PCSBPCLK  
TEST3_SDI+  
TEST2  
TEST1_FXR+  
TEST0_FXR-  
FXT+  
0.056µF  
C5  
R26  
499  
RXCL  
TXCL  
K
K
TXD3  
TXD2  
TXD1  
TXD0  
Y1  
25 MHz  
40  
39  
38  
37  
TXD3  
TXD2  
TXD1  
TXD0  
220pF  
-IORQ  
-MREQ  
-RD  
49  
50  
51  
52  
58  
33  
34  
35  
36  
-IORQ  
-MREQ  
-RD  
-WR  
-BUSACK  
-CS0  
-CS1  
-CS2  
-CS3  
IORQ  
MRQ  
RD  
WR  
BUSACK  
CS0  
CS1  
CS2  
CS3  
FXT-  
XTL-  
XTL+  
TX+  
C7  
18pF  
83  
FILT_IN  
GND  
VCC  
-WR  
Y2  
TXEN  
TXER  
COL  
85  
86  
34  
32  
41  
42  
XOUT  
XIN  
TXEN  
TXER_TXD4  
COL  
TX-  
-CS0  
-CS1  
-CS2  
-CS3  
50MHz  
64  
63  
RX+  
RX-  
CRS  
C17  
0.1µF  
CRS  
R27  
SCL  
SDA  
110  
109  
AM79C87  
4
IICSCL  
IICSDA  
SCL  
SDA  
L1  
200K  
6
14  
22  
31  
47  
59  
81  
87  
88  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
PLL_VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
P2  
R11  
49.9  
PA7  
PA6  
PA5  
PA4  
PA3  
PA2  
PA1  
PA0  
C8  
121  
120  
119  
118  
117  
116  
115  
114  
PA7_PWM3  
PA6_PWM2_EC1  
PA5_PWM1_TOUT1  
PA4_PWM0_TOUT0  
PA3_PWM3_OC3  
PA2_PWM2_OC2  
PA1_PWM1_OC1  
PA0_PWM0_OC0  
GND  
C9  
1
4
2
5pF  
TX+  
TXCT  
TX-  
3.3µH  
10pF  
VCC  
C44  
C45  
C46  
C47  
C48  
R32  
49.9  
0.1µF  
0.1µF  
0.1µF  
0.1µF  
0.1µF  
VCC  
R31 49.9  
3
5
6
RX+  
RXCT  
RX-  
R34  
R35  
330  
330  
C10  
0.1µF  
98  
PA[0:7]  
PB[0:7]  
PC[0:7]  
PB7  
PB6  
PB5  
PB4  
PB3  
PB2  
PB1  
PB0  
C49  
0.1µF  
C50  
0.1µF  
GND  
C51  
0.1µF  
C52  
0.1µF  
C53  
0.1µF  
R33  
C15  
0.1µF  
49.9  
C16  
0.1µF  
112  
122  
133  
107  
106  
105  
104  
103  
102  
101  
100  
8
PB7_MOSI  
PB6_MISO  
PB4_ICB3  
PB4_ICA3  
PB3_SCK  
PB2_SS  
PB0_IC1  
GND  
VCC  
9
10  
11  
12  
AN1  
CT1  
AN2  
CT2  
Put caps between pairs of U6, 10:11, 51:52, 59:65  
and 71:73 as close to the pins as possible  
RTC_VDD  
RTC_VDD  
VCC  
7
15  
23  
32  
38  
48  
60  
64  
72  
82  
84  
89  
99  
108  
113  
123  
134  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
PLL_VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
PB0_IC0_EC0  
-LEDRX  
HFJ11-2450E-L11  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC0  
CR1  
1N5817  
97  
96  
95  
94  
93  
92  
91  
90  
PC7_RI1  
PC6_DCD1  
PC5_DSR1  
PC4_DTR1  
PC3_CTS1  
PC2_RTS1  
PC1_RXD1  
PC0_TXD1  
-LEDLNK  
VCC  
R28  
22  
0
C31  
0.001µF  
C32  
0.001µF  
C33  
0.001µF  
C34  
0.001µF  
C35  
0.001µF  
C36  
0.001µF  
C37  
0.001µF  
C38  
0.001µF  
C39  
0.001µF  
C40  
0.001µF  
C41  
0.001µF  
C42  
C43  
0.001µF  
GND  
0.001µF  
PD7  
PD6  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
80  
79  
78  
77  
76  
75  
74  
73  
PD7_RI0  
PD6_DCD0  
PD5_DSR0  
PD4_DTR0  
PD3_CTS0  
Y3  
32.768KHz  
C18  
0.1µF  
C19  
0.1µF  
C20  
0.1µF  
C21  
0.1µF  
C22  
0.1µF  
C23  
0.1µF  
C24  
0.1µF  
C25  
0.1µF  
C26  
0.1µF  
C27  
0.1µF  
C28  
0.1µF  
C29  
0.1µF  
C30  
0.1µF  
VL1  
PD2_RTS0  
VCC  
R38  
10M  
63  
62  
61  
RTC_VDD  
RTC_XOUT  
RTC_XIN  
PD1_RXD0_IRRXD  
PD0_TXD0_IRTXD  
PD[0:7]  
65  
111  
53  
70  
68  
-HALT_SL  
CLK_OUT  
-INSTRD  
TDO  
P
HALT_SLP  
PHI  
INSTRD  
TDO  
TRIGOUT  
VCC  
VCC  
VCC  
GND  
C11  
12pF  
C12  
12pF  
GND  
GND  
TRIGOUT  
EZ80F91  
GND  
Figure 9. eZ80F91 Module Schematic Diagram, #2 of 3—CPU and PHY  
PS019310-0904  
P R E L I M I N A R Y  
Schematics  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
27  
U8  
A18  
A0  
A1  
A2  
A3  
-CS1  
D0  
D1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
A0  
A1  
A2  
A3  
N.C.  
A18  
A17  
A16  
A15  
OE  
I/O7  
I/O6  
VSS  
VDD  
I/O5  
I/O4  
A14  
A13  
A12  
A11  
A10  
N.C.  
A16  
A15  
A14  
A13  
-RD  
D7  
A4  
-CS1  
-CS1  
CE  
I/O0  
I/O1  
VDD  
VSS  
I/O2  
I/O3  
WE  
A5  
A6  
A7  
A8  
A9  
VCC  
VCC  
D6  
VCC  
D2  
D3  
-WR  
A12  
A9  
A6  
A4  
D5  
D4  
A11  
A8  
A10  
A7  
A5  
C13  
0.001uF  
A17  
512KB x 8 SRAM  
SOJ36.400  
D[0:7]  
VCC  
A[0..23]  
A[0..23]  
A[0:23]  
U9  
U10  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
DFLASH0  
DFLASH1  
DFLASH2  
DFLASH3  
DFLASH4  
DFLASH5  
DFLASH6  
DFLASH7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
21  
20  
19  
18  
17  
16  
15  
14  
8
7
36  
6
5
4
3
2
1
40  
13  
37  
25  
26  
27  
28  
32  
33  
34  
35  
2
5
6
3
4
7
8
11  
14  
17  
18  
21  
22  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
1B1  
1A1  
1A2  
1A3  
1A4  
1A5  
2A1  
2A2  
2A3  
2A4  
2A5  
1B2  
1B3  
1B4  
1B5  
2B1  
2B2  
2B3  
2B4  
2B5  
9
10  
15  
16  
19  
20  
23  
VCC  
A8  
A9  
A8  
A9  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
-CSFLASH  
-RD  
-WR  
-RESET  
-WP  
22  
24  
9
10  
12  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
CE  
OE  
WE  
RP  
C14  
0.001µF  
1
13  
1OE  
2OE  
-CSFLASH  
74CBTLV3384  
SO24.300  
WP  
11  
VCC  
VPP  
A21  
A20  
29  
38  
N.C.  
N.C.  
VCC  
Flash 1Mx8 3.3V  
TSOP40.20MM  
MT28F008B3VG  
R29  
10K  
U4C  
9
U1D  
9
-CS0  
-CSFLASH  
8
-DIS_FLASH  
-FLASH_EN  
8
10  
-DIS_FLASH  
74LCX32  
TSSOP14  
-RD  
-RD  
74LCX04  
TSSOP14  
-WR  
-WR  
VCC  
VCC  
-CS0  
-CS0  
VCC  
GND  
R30  
10K  
-RESET  
-RESET  
U1E  
GND  
-FLASHWE  
-WP  
11  
10  
-FLASHWE  
74LCX04  
TSSOP14  
Figure 10. eZ80F91 Module Schematic Diagram, #3 of 3—Module Memory  
PS019310-0904  
P R E L I M I N A R Y  
Schematics  
eZ80F915050MOD  
eZ80F91 Module Product Specification  
28  
Customer Feedback Form  
The eZ80F91 Module Product Specification  
If you experience any problems while operating this product, or if you note any inaccuracies  
while reading this Product Specification, please copy and complete this form, then mail or fax it to  
ZiLOG (see Return Information, below). We also welcome your suggestions!  
Customer Information  
Name  
Country  
Phone  
Fax  
Company  
Address  
City/State/Zip  
Email  
Product Information  
Serial # or Board Fab #/Rev. #  
Software Version  
Document Number  
Host Computer Description/Type  
Return Information  
ZiLOG  
System Test/Customer Support  
532 Race Street  
San Jose, CA 95126  
Phone: (408) 558-8500  
Fax: (408) 558-8536  
ZiLOG Customer Support  
Problem Description or Suggestion  
Provide a complete description of the problem or your suggestion. If you are reporting a specific  
problem, include all steps leading up to the occurrence of the problem. Attach additional pages  
as necessary.  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
PS019310-0904  
P R E L I M I N A R Y  
Customer Feedback Form  
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