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IXLD02SI

型号：

IXLD02SI

描述：

差2A超快激光二极管驱动器[ Differential 2A Ultra Fast Laser Diode Driver ]

品牌：

IXYS[ IXYS CORPORATION ]

页数：

6 页

PDF大小：

164 K

下载PDF手册
IXLD02SI  
Differential 2A Ultra Fast Laser Diode Driver  
General Description  
Features  
TheIXLD02isanultrahigh-speeddifferentiallaserdiode  
driver. The IXLD02 is designed specifically to drive single  
junction laser diodes in a differential fashion. A Q output and  
a Q-Bar output are provided via a low inductance multi-pin  
topology. These two signals make their transitions at the  
same time with transition times in the picoseconds. This  
technique provides the highest possible slew rate across  
the diode. In addition the IXLD02 is capable of currents  
exceeding 2A.  
• Ultra Fast Pulsed Current Source  
• High Output Currents >2A Peak  
• 17MHzMaxOperatingFrequency  
• <1.5ns Minimum Pulse Width  
• 600ps Rise And Fall Times  
• Pulse Width and Frequency Agile  
• RealTimeElectronicProgrammingof  
Current and Pulse Width  
• LowInductanceHighPowerPackage  
Design  
Theseperformancefeaturesarecombinedwithfrequency  
agility to a maximum operating frequency of 17MHz, a  
minimum pulse width of <1.5ns and rise and fall times of  
approximately 600ps. In addition, the pulse width and the  
current programming can be modulated in real time to  
>10MHz. The IXLD02 is assembled in a high power SO-28  
surfacemountpackage.  
• Simultaneous Frequency, Pulse Width  
and Amplitude Modulation  
Applications  
• HighSpeedLaserDiodeDrivers  
• High Power Ultra Fast Line Drivers  
• DifferentialPowerDrivers  
For additional operational instructions, see the IXLD02  
Evaluation Board application note on the DEI web site at  
www.directedenergy.com  
• HighPowerPulseGenerators  
• HighSpeedHighFrequencyModulators  
Figure 1 - Functional Diagram  
Copyright © Directed Energy, Inc. 2002, 2003  
First Release  
IXLD02SI  
Absolute Maximum Ratings (Note 1)  
Name  
VDD  
Definition  
Logic supply input voltage  
Min  
-0.4  
Typ  
Max  
5.5  
Units Test Conditions  
V
VDDA  
Analog bias supply input voltage  
-0.4  
5.5  
V
VTT  
IBI  
Internal bias voltage input  
Internal bias current input  
Applied IBI terminal voltage  
-0.4  
-10  
VDDA/2 VDDA+.5  
V
mA  
V
0.1  
10  
VIBI  
-0.4  
VDDin+0.5  
Pulse width programming  
IPW  
VIPW  
IOP  
-10  
-0.4  
-10  
0.1  
10  
VDDin+0.5  
10  
mA  
V
current input  
Applied IPW terminal voltage  
Output current programming  
1
mA  
input  
VIOP  
VPDN  
VRST  
VFIN  
VOUT  
VOUT  
Applied IOP terminal voltage  
Power-down logic input  
Reset logic input  
Pulse frequency logic input  
Pulse current true output  
OUT terminal voltage  
-0.4  
-0.4  
-0.4  
-0.4  
-0.1  
-0.4  
VDDin+0.5  
VDDin+0.5  
VDDin+0.5  
VDDin+0.5  
3
V
V
V
V
Amps  
V
9
Pulse current complement  
OUTB  
VOUTB  
-0.1  
-0.4  
3
9
Amps  
output  
OUTB terminal voltage  
V
Measured at the  
bottom of the  
oC  
TC  
Device Case Temperature  
-40  
25  
85  
SO28 package  
heat slug insert.  
SO28 package  
Package power dissipation @  
TC=85C  
PD  
32  
2
Watts  
oC/W  
heat slug insert  
held at TC=85oC.  
Thermal resistance, junction to  
case  
RTHJC  
TJ  
TS  
Junction Temperature  
Storage temperature  
150  
150  
oC  
oC  
-55  
Lead temperature (soldering, 10  
TL  
300  
oC  
sec)  
Note 1: Operating the device beyond parameters with listed “Absolute Maximum Ratings” may cause permanent  
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not  
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.  
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures  
when handling and assembling this component.  
Ordering Information  
Part Number Package Type Temp. Range  
Grade  
IXLD02SI  
28-Pin SOIC  
Industrial  
-40 C to +85 C  
°
°
2
IXLD02SI  
Recommended Operating Conditions  
Unless otherwise noted, VDD=VDDA=5V, TC=25C  
Name  
Definition  
Min  
Typ  
Max Units  
Test Conditions  
VDD Logic supply input voltage  
VDDA Analog bias supply input voltage  
VTT Internal bias voltage input  
RVTT VTT terminal resistance  
4.5  
4.5  
2
5.5  
5.5  
3
V
V
V
VDDA/2  
50  
Measured with Zin>10meg DVM.  
30  
70 Kohms Measured with VDDin=VDDA=0V.  
IIBI Internal bias current input range  
10  
100  
300  
uA External current source between  
VDDA and IBI terminal.  
VIBI Measured IBI terminal voltage  
0.6  
-1  
1.7  
400  
V
IIBI=100uA.  
IIPW Pulse width programming current input  
range.  
VIPW Measured IPW terminal voltage  
100  
uA External current source between  
VDDA and IPW terminal.  
0.6  
0
1.7  
3
V
IIPW=100uA.  
tPW IOUT=2A peak, Output current pulse width  
1
1
ns IIBI=400uA, IIPW=300uA, IIOP=1mA.  
IIOP OUT and OUTB output current, IOUT  
,
mA External current source between  
programming current.  
VDDA and IBI terminals.  
IBI=100uA.  
VIOP Measured IOP terminal voltage  
0.6  
1.7  
V
IOUT/IIOP Output current to programming current gain  
1800  
2000  
2200  
I/I IIOP=1mA, VOUT=VOUTB=10V.  
VIH Logic input high threshold for PDN, RST, & 0.7*VDD  
FIN inputs.  
V
V
VIL Logic input high threshold for PDN, RST, &  
.3*VDD  
10  
FIN inputs.  
ILIN Logic input bias current for PDN, RST, &  
FIN inputs.  
-10  
uA For logic inputs, PDN, RST, & FIN  
held at:-0.5V<VLIN<VDD  
tPDN IXLD02 power down delay, VPDN logical low  
to high transition.  
50  
30  
ns  
IXLD02 power up delay, VPDN logical high to  
ns  
low transition.  
tRST IXLD02 reset logic delay, VRST logical low to  
high transition.  
100  
100  
50  
ns  
IXLD02 reset logic delay, VRST logical low to  
high transition.  
ns  
tFIN IXLD02 pulse frequency input, VFIN, logical  
low to high transition to IOUT pulse delay.  
fFINmax Maximum pulse frequency, FIN, logic input.  
ns IIBI=400uA, IIPW=300uA, IIOP=1mA..  
MHz IIBI=400uA, IIPW=300uA, IIOP=1mA..  
17  
IOUT Peak true pulse current output.  
1.6  
2
2.4  
Amps IIBI=400uA, IIPW=300uA, IIOP=1mA.,  
VOUT=VOUTB=10V.  
tR  
tF  
Rise time  
Fall time  
600  
600  
ps  
ps  
TONDLY On-time propagation delay  
TOFFDLY Off-time propagation delay  
PWmax Pulse width maximum  
30  
30  
ns  
ns  
us  
ps  
>1  
Tj  
Jitter  
<300  
VOUT OUT terminal voltage  
8
0
8
12  
0.4  
12  
V
IIBI=400uA, IIPW=300uA, IIOP=1mA,  
1.4A<IOUT<2.6A peak.  
IOUTB Minimum complement pulse current output.  
VOUTB OUTB terminal voltage  
0.2  
Amps IIBI=400uA, IIPW=300uA, IIOP=1mA.,  
VOUT=VOUTB=10V.  
V
IIBI=400uA, IIPW=300uA, IIOP=1mA,  
0A<IOUT<0.6A minimum.  
3
IXLD02SI  
Pin Configurations And Package Outline  
NOTE: Bottom-side heat sinking metalization is connected to ground  
Pin Description  
Pins Nam e  
Description  
1,2,  
This pin is a high current, low inductance pin designed to accept peaks  
VDD  
13, 14  
of 2Amps at 5V.  
This is a low current analog power input. Circuit com ponents sensitive  
to the noise present on VDD in are supplied by this pin.  
3
4
5
VDDA  
VTT This pin is the 1/2VDDA internal analog com parator reference point.  
Low current, low noise analog return. Noise sensitive circuit  
GNDA  
components are returned here.  
The current, IIBI, flowing into the IBI pin acts as a baseline current with  
6
7
IBI  
respect to IIPW current to com pensate for internal delays. See Figure 2.  
A current, IIOP, into the IOP pin program s the laser diode output  
IOP switches, pin 19 through pin 24. The program ratio is 1:1000X. This  
m eans a 1m A current will produce 1Am p. See Figure 2.  
A current, IIPW , flowing into the IPW pin determ ines the output current  
pulse width, tPW , with respect to IIBI. If IIPW =IIBI, the pulse width is 0. As  
8
IPW  
IIPW approaches IIBI but less than IIBI, the pulse width becom es non-  
zero. See Figure 2 for tPW as a function of IIBI and IIPW  
.
A TTL high on this pin will power down the device so that only leakage  
PDN current will flow from VDD to DGND. A TTL low will turn on the device  
within 30ns. See Figure 3.  
9
A system reset pin, which initializes the device so that it starts in a  
10  
11  
RST  
predeterm ined initial state.  
This pin is the return for the input logic, IIBI, IIO P, and IIPW currents. It is  
DGND internally connected to the other grounds, AGND or GND, through the  
substrate.  
W ith PDN low, a positive edge of a TTL compatible signal here will  
produce the pulse current output available at the OUT and a  
12  
FIN  
complem ent of it at OUTb pins. Refer to Figure 3 for FIN and PDN  
tim ing.  
15, 16,  
17, 18,  
25, 26,  
27, 28  
GND Output ground pins designed for low inductance.  
19, 20.  
21  
True laser diode drive output current. Designed for low inductance and  
OUT  
output voltage compliance to +12V.  
22, 23,  
24  
Com plem entary laser diode drive output current. Designed for low  
OUTb  
inductance and output voltage compliance to +12V.  
4
IXLD02SI  
Figure 2 - Programmed IOUT pulse width, tPW as a function of IIPW and IIBI  
Figure 2 is an illustration of the pulse width vs. programming current. The programming current is typically a DC  
level, however it could just as well be a time varying signal. The bandwidth of this portion of the IXLD02 is equivalent  
to the maximum operating frequency of 17MHz. For the fastest response time this pin should be driven from a low  
sourceimpedance.  
Figure 3 - Control Gate Timing Diagram  
Figure 3 is a timing chart for the IXLD02. The proper gating of the IXLD02 is extremely important. The device is  
capable of 2A of current and may consume in excess of 3A during the pulse. If the supply voltage is at 7V with 3A of  
current, the total power dissipated is 21W. Therefore ample heat sinking must be provided, and/or the duty cycle  
must be limited so that the power dissipation capability of the device is not exceeded.  
The Power Up Gate (PDN) is applied to activate the device. Time interval “A” can be >30ns. At the end of this time  
period the control gate “B” (FIN), can be applied. The range of “B” is from 1ns to several µs. The maximum frequency  
1/C is approximately 17MHz.  
5
IXLD02SI  
Figure 4 - Duty Cycle  
Figure 4 illustrates the Duty Cycle (DC), FIN and PDN relation ships. The PDN command must be in a TTL “High”  
state 30ns prior to the first FIN pulse. It must stay in this state for the duration of the laser light burst, T1 to T2.  
T2 − T1  
The Duty cycle is defined as: DC =  
T3 − T1  
Power in the IC is:  
Total dc Power X DC  
Figure 5 - IPW And IOP Modulation  
Figure 5 illustrates the simultaneous modulation of both the IPW control current and the IOP control current. The FIN  
frequency in this figure is held constant. At T0 the IPW and the IOP signals are near zero, both begin to ramp up at  
T1 and reach their maximums at T2. As illustrated, the output current rises in amplitude with the increasing IOP and  
the pulse width widens with the IPW ramp.  
An additional mode of modulation can be added to the two above by also modulating the frequency of the FIN signal.  
This will allow three mode of simultaneous modulation. The three modes do not have to be used together; each is  
fully independent. The obvious caveat is that the pulse width must be consistent with the chosen frequency. This  
agility provides the designer with a broad range of design choices.  
Directed Energy, Inc.  
An IXYS Company  
2401 Research Blvd. Ste. 108  
Ft. Collins, CO 80526  
Tel: 970-493-1901; Fax: 970-493-1903  
e-mail: deiinfo@directedenergy.com  
www.directedenergy.com  
Doc #9200-0258 Rev 2  
6
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