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XTR101BG

型号：

XTR101BG

描述：

高精度，低漂移的4-20mA两线制变送器[ Precision, Low Drift 4-20mA TWO-WIRE TRANSMITTER ]

品牌：

TI[ TEXAS INSTRUMENTS ]

页数：

25 页

PDF大小：

736 K

下载PDF手册
XTR101  
SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
Precision, Low Drift  
4-20mA TWO-WIRE TRANSMITTER  
FD EATURES  
DESCRIPTION  
INSTRUMENTATION AMPLIFIER INPUT:  
− Low Offset Voltage, 30µV max  
− Low Voltage Drift, 0.75µV/°C max  
− Low Nonlinearity, 0.01% max  
The XTR101 is  
a microcircuit, 4-20mA, two-wire  
transmitter containing a high accuracy instrumentation  
amplifier (IA), a voltage-controlled output current source,  
and dual-matched precision current reference. This  
combination is ideally suited for remote signal conditioning  
of a wide variety of transducers such as thermocouples,  
RTDs, thermistors, and strain gauge bridges. State-of-the-  
art design and laser-trimming, wide temperature range  
operation, and small size make it very suitable for  
industrial process control applications. In addition, the  
optional external transistor allows even higher precision.  
D
TRUE TWO-WIRE OPERATION:  
− Power and Signal on One Wire Pair  
− Current Mode Signal Transmission  
− High Noise Immunity  
D
D
D
D
DUAL MATCHED CURRENT SOURCES  
WIDE SUPPLY RANGE: 11.6V to 40V  
SPECIFICATION RANGE: −40°C to +85°C  
The two-wire transmitter allows signal and power to be  
supplied on a single wire pair by modulating the  
power-supply current with the input signal source. The  
transmitter is immune to voltage drops from long runs and  
noise from motors, relays, actuators, switches,  
transformers, and industrial equipment. It can be used by  
OEMs producing transmitter modules or by data  
acquisition system manufacturers.  
SMALL DIP-14 PACKAGE, CERAMIC AND  
PLASTIC  
AD PPLICATIONS  
INDUSTRIAL PROCESS CONTROL:  
− Pressure Transmitters  
IREF1  
Optional  
IREF2  
− Temperature Transmitters  
− Millivolt Transmitters  
External  
10  
Transistor  
+VCC  
8
3
11  
e1  
−
D
D
D
D
D
D
D
RESISTANCE BRIDGE INPUTS  
THERMOCOUPLE INPUTS  
5
6
RTD INPUTS  
12(1)  
XTR101  
Span  
B
CURRENT SHUNT (mV) INPUTS  
PRECISION DUAL CURRENT SOURCES  
AUTOMATED MANUFACTURING  
4
e2  
+
9
POWER/PLANT ENERGY SYSTEM  
MONITORING  
13(1)  
E
14  
7
2
IOUT  
1
Optional  
Offset Null  
NOTE: (1) Pins 12 and 13 are used for optional BW control.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢃ ꢉꢆꢉ ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑꢊꢍꢋ ꢊꢒ ꢓꢔ ꢎ ꢎ ꢕꢋꢑ ꢐꢒ ꢍꢌ ꢖꢔꢗ ꢘꢊꢓ ꢐꢑꢊ ꢍꢋ ꢙꢐ ꢑꢕꢚ ꢀꢎ ꢍꢙꢔ ꢓꢑꢒ  
ꢓ ꢍꢋ ꢌꢍꢎ ꢏ ꢑꢍ ꢒ ꢖꢕ ꢓ ꢊ ꢌꢊ ꢓ ꢐ ꢑꢊ ꢍꢋꢒ ꢖ ꢕꢎ ꢑꢛꢕ ꢑꢕ ꢎ ꢏꢒ ꢍꢌ ꢆꢕꢜ ꢐꢒ ꢇꢋꢒ ꢑꢎ ꢔꢏ ꢕꢋꢑ ꢒ ꢒꢑ ꢐꢋꢙ ꢐꢎ ꢙ ꢝ ꢐꢎ ꢎ ꢐ ꢋꢑꢞꢚ  
ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ  
Copyright 1986-2004, Texas Instruments Incorporated  
www.ti.com  
ꢠ ꢆ ꢁ ꢡꢢ ꢡ  
www.ti.com  
SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
This integrated circuit can be damaged by ESD. Texas  
Instruments recommends that all integrated circuits be  
(1)  
ABSOLUTE MAXIMUM RATINGS  
Power Supply, +V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V  
handledwith appropriate precautions. Failure to observe  
CC  
proper handling and installation procedures can cause damage.  
Input Voltage, e or e . . . . . . . . . . . . . . . . . . . . ≥ V  
OUT  
, ≤ +V  
1
2
CC  
Storage Temperature Range, Ceramic . . . . . . . . . −55°C to +165°C  
Plastic . . . . . . . . . . −55°C to +125°C  
Lead Temperature (soldering, 10s) G, P . . . . . . . . . . . . . . . +300°C  
(wave soldering, 3s) U . . . . . . . . . . . . . . +260°C  
ESD damage can range from subtle performance degradation to  
complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could  
cause the device not to meet its published specifications.  
Output Short-Circuit Duration . . . . . . . Continuous +V  
to I  
CC  
OUT  
ORDERING INFORMATION  
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +165°C  
SPECIFIED  
TEMPERATURE  
RANGE  
(1)  
PACKAGE-  
LEAD  
PACKAGE  
DESIGNATOR  
PACKAGE  
MARKING  
Stresses above these ratings may cause permanent damage.  
PRODUCT  
(1)  
Exposure to absolute maximum conditions for extended periods  
may degrade device reliability. These are stress ratings only, and  
functional operation of the device at these or any other conditions  
beyond those specified is not supported.  
XTR101AG  
XTR101BG  
Ceramic  
DIP-14  
JD  
XTR101  
−40°C to +85°C  
Plastic  
DIP-14  
N
XTR101AP  
XTR101AU  
SO-16  
DW  
(1)  
For the most current package and ordering information, see the Package  
Option Addendum located at the end of this data sheet.  
PIN CONFIGURATION  
Top View  
DIP Top View  
SO  
1
2
3
4
5
6
7
8
Zero Adjust  
Zero Adjust  
16 Zero Adjust  
15  
1
2
3
4
5
6
7
14  
Zero Adjust  
Zero Adjust  
Zero Adjust  
Bandwidth  
13 Bandwidth  
12 B Control  
−
In  
14 B Control  
13 IREF2  
−
In  
SOL−16  
Surface−Mount  
+In  
Span  
Span  
Out  
DIP  
11  
10  
9
+In  
Span  
Span  
Out  
IREF2  
IREF1  
E
12  
11  
10  
9
IREF1  
E
+VCC  
NC  
8
+VCC  
NC  
NC = No Connection  
2
ꢠ ꢆꢁ ꢡꢢ ꢡ  
www.ti.com  
SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
ELECTRICAL CHARACTERISTICS  
At T = +25°C, +V  
= 24VDC, and R = 100Ω with external transistor connected, unless otherwise noted.  
A
CC  
L
XTR101AG  
XTR101BG  
XTR101AP  
XTR101AU  
TYP  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
MIN  
MAX  
PARAMETER  
CONDITIONS  
UNIT  
OUTPUT AND LOAD CHARACTERISTICS  
Current  
Linear Operating Region  
Derated Performance  
4
20  
22  
38  
10  
20  
∗
∗
∗
∗
∗
6
∗
∗
∗
∗
∗
19  
20  
∗
∗
∗
∗
∗
19  
mA  
mA  
3.8  
Current Limit  
28  
∗
2.5  
8
31  
31  
8.5  
∗
mA  
Offset Current Error  
vs Temperature  
Full-Scale Output Current  
Error  
I
, I = 4mA  
O
3.9  
10.5  
8.5  
10.5  
µA  
ppm, FS/°C  
OS  
∆I /∆T  
OS  
Full-Scale = 20mA  
15  
20  
40  
40  
15  
30  
∗
∗
∗
30  
60  
∗
∗
∗
30  
60  
∗
∗
∗
µA  
VDC  
Ω
Power-Supply Voltage  
V
, Pins 7 and 8,  
CC  
Compliance  
+11.6  
∗
∗
∗
(1)  
At V  
= +24V,  
CC  
Load Resistance  
600  
1400  
I
= 20mA  
O
At V  
= +40V,  
CC  
Ω
I
= 20mA  
O
SPAN  
Output Current Equation  
R in Ω, e and e in V  
S 1 2  
+ 4mA ) ƪ0.016ampsńvolt ) ǒ40ńR Ǔƫǒe2 1Ǔ  
I
* e  
O
S
Span Equation  
vs Temperature  
R
in Ω  
A/V  
S + ƪ0.016ampsńvolt ) ǒ40ńRSǓƫ  
S
Excluding TCR of R  
30  
100  
0
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
ppm/°C  
S
(2)  
Untrimmed Error  
ε
−5  
−2.5  
∗
∗
∗
∗
∗
%
%
%
%
SPAN  
Nonlinearity  
Hysteresis  
Dead Band  
ε
0.01  
NONLINEARITY  
0
0
∗
∗
∗
∗
∗
∗
INPUT CHARACTERISTICS  
Impedance: Differential  
Common-Mode  
0.4 3  
10 3  
∗
∗
∗
∗
GΩ pF  
GΩ pF  
V
∗
∗
(3)  
1
Voltage Range, Full-Scale  
Offset Voltage  
∆e = (e − e )  
0
1
∗
∗
∗
0.75  
∗
∗
∗
∗
∗
∗
2
V
30  
0.75  
125  
60  
60  
1.5  
20  
0.35  
∗
30  
∗
∗
100  
∗
∗
100  
∗
µV  
µV/°C  
dB  
OS  
vs Temperature  
∆V /∆T  
∆V /PSRR = V  
∗
OS  
Power-Supply Rejection  
Bias Current  
Error  
OS  
110  
122  
∗
122  
∗
CC  
I
150  
1
∗
∗
∗
20  
∗
∗
∗
∗
∗
∗
∗
∗
∗
nA  
B
vs Temperature  
∆I /∆T  
0.30  
10  
∗
∗
∗
nA/°C  
nA  
B
Offset Current  
I
30  
0.3  
∗
∗
∗
OSI  
/∆T  
vs Temperature  
∆I  
0.1  
∗
∗
∗
nA/°C  
OSI  
Common-Mode  
DC  
90  
4
100  
∗
∗
∗
∗
∗
∗
∗
∗
∗
dB  
V
(4)  
Rejection  
Common-Mode Range  
e
and e with Respect to Pin 7  
6
∗
∗
∗
1
2
CURRENT SOURCES  
Magnitude  
1
∗
∗
0.2  
∗
0.2  
mA  
%
Accuracy  
V
= 24V,  
CC  
0.1  
7
0.02  
5
V
− V  
PIN 10, 11  
= 19V,  
0.06  
0.075  
50  
0.37  
0.37  
PIN 8  
R
2
= 5kΩ, see Figure 5  
vs Temperature  
50  
3
80  
30  
∗
∗
∗
∗
∗
∗
∗
∗
∗
ppm/°C  
ppm/V  
vs V  
CC  
vs Time  
8
∗
ppm/month  
Compliance Voltage Ratio  
Match  
With Respect to  
Pin 7 Tracking  
0
V
− 3.5  
∗
∗
∗
0.04  
∗
∗
∗
0.088  
∗
∗
∗
0.088  
V
CC  
0.01  
4
0.0  
6
0.00  
9
Accuracy  
(1 − I  
/I  
) × 100%  
0.031  
0.031  
%
REF1 REF2  
vs Temperature  
15  
10  
∗
∗
ppm/°C  
ppm/V  
vs V  
CC  
vs Time  
10  
1
∗
∗
∗
∗
∗
15  
∗
∗
15  
ppm/month  
MΩ  
Output Impedance  
10  
20  
TEMPERATURE RANGE  
Specification  
−40  
−55  
−55  
+85  
+125  
+165  
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
°C  
°C  
°C  
Operating  
−40  
−55  
+85  
+125  
−40  
−55  
+85  
+125  
Storage  
∗
Same as XTR101AG.  
See the Typical Characteristics.  
Span error shown is untrimmed and may be adjusted to zero.  
(1)  
(2)  
(3)  
e
and e are signals on the −In and +In terminals with respect to the output, pin 7. While the maximum permissible ∆e is 1V, it is primarily intended for much lower signal levels, for  
1
2
instance, 10mV or 50mV full-scale for the XTR101A and XTR101B grades, respectively. 2mV FS is also possible with the B grade, but accuracy will degrade due to possible errors  
in the low value span resistance and very high amplification of offset, drift, and noise.  
Offset voltage is trimmed with the application of a 5V common-mode voltage. Thus, the associated common-mode error is removed. See the Application Information section.  
(4)  
3
ꢠ
ꢆ
ꢁ
ꢡ
ꢢ
ꢡ
www.ti.com  
SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
TYPICAL CHARACTERISTICS  
At T = +25°C and V  
= 24VDC, unless otherwise noted.  
A
CC  
STEP RESPONSE  
SPAN vs FREQUENCY  
25  
20  
15  
10  
5
80  
CC = 0  
Ω
RS = 25  
∞
=
RS  
60  
40  
Ω
Ω
R
S = 100  
Ω
RS = 25  
RS = 400  
Ω
S = 2k  
R
∞
=
RS  
20  
0
0
0
200  
400  
600  
800  
1000  
100  
1k  
10k  
100k  
1M  
µ
Time ( s)  
Frequency (Hz)  
FULL−SCALE INPUT VOLTAGE vs RS  
RS (kΩ )  
COMMON−MODE REJECTION vs FREQUENCY  
0
2
4
6
8
120  
100  
80  
60  
40  
20  
0
0.08  
0.8  
0.6  
0.4  
0.06  
0.04  
0.02  
0
0 to 800mV and  
Ω
0 to 8k scale  
0.2  
0
0 to 80mV (low−level signals)  
and 0 to 400 scale  
Ω
0.1  
1
10  
100  
1k  
10k  
100k  
0
100  
200  
300  
400  
RS (Ω)  
Frequency (Hz)  
BANDWIDTH vs PHASE COMPENSATION  
POWER−SUPPLY REJECTION vs FREQUENCY  
100k  
10k  
1k  
140  
120  
100  
80  
60  
40  
20  
0
∞
=
RS  
Ω
RS = 400  
Ω
RS = 100  
100  
10  
1
Ω
RS = 25  
0.1  
1
10  
100  
1k  
10k  
100k  
1M  
0.1  
10  
100  
1k  
10k  
100k  
1M  
10M  
Bandwidth Control, CC (pF)  
Frequency (Hz)  
4
ꢠ ꢆꢁ ꢡꢢ ꢡ  
www.ti.com  
SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
TYPICAL CHARACTERISTICS (continued)  
At T = +25°C, V  
DD  
= +3.3V, and V = +3.3V, unless otherwise noted.  
IO  
A
INPUT VOLTAGE NOISE DENSITY vs FREQUENCY  
INPUT CURRENT NOISE DENSITY vs FREQUENCY  
60  
50  
40  
30  
20  
10  
0
6
5
4
3
2
1
0
1
10  
100  
1k  
10k  
100k  
1
10  
100  
1k  
10k  
100k  
Frequency (Hz)  
Frequency (Hz)  
OUTPUT CURRENT NOISE DENSITY vs FREQUENCY  
6
5
4
3
2
1
0
1
10  
100  
1k  
10k  
100k  
Frequency (Hz)  
5
ꢠ ꢆ ꢁ ꢡꢢ ꢡ  
www.ti.com  
SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
Examination of the transfer function shows that IO has a  
lower range-limit of 4mA when eIN = e2 − e1 = 0V. This 4mA  
is composed of 2mA quiescent current exiting pin 7 plus  
2mA from the current sources. The upper range limit of IO  
is set to 20mA by the proper selection of RS based on the  
upper range limit of eIN. Specifically, RS is chosen for a  
16mA output current span for the given full-scale input  
voltage span.  
THEORY OF OPERATION  
A simplified schematic of the XTR101 is shown in Figure 1.  
Basically, the amplifiers A1 and A2 act as a single  
power-supply instrumentation amplifier controlling a  
current source, A3 and Q1. Operation is determined by an  
internal feedback loop. e1 applied to pin 3 will also appear  
at pin 5, and similarly, e2 will appear at pin 6. Therefore, the  
current in RS (the span setting resistor) will be  
IS = (e2 − e1)/RS = eIN/RS. This current combines with the  
current I3 to form I1. The circuit is configured such that I2  
is 19 times I1. From this point, the derivation of the transfer  
function is straightforward but lengthy. The result is shown  
in Figure 1.  
amps  
volt  
40  
RS  
ǒ Ǔ  
Ǔ
eIN full−scale + 16mA.  
ǒ
For example, 0.016  
)
Note that since IO is unipolar, e2 must be kept larger than  
e1 (that is, e2 ≥ e1 or eIN ≥ 0). Also note that in order not to  
exceed the output upper range limit of 20mA, eIN must be  
kept less than 1V when RS = ∞ and proportionately less as  
RS is reduced.  
eIN  
−
+
RS  
(e2)  
(e1)  
IS  
5
6
I3  
I4  
R3  
R4  
Ω
Ω
1.25k  
1.25k  
+VCC  
+VCC  
+VCC  
8
D1  
IB1  
A1  
A2  
(e1)  
−
In3  
eIN  
IB2  
VPS  
+In4  
(e2)  
µ
100 A  
IO  
7
Q1  
+
+VCC  
eL  
RL  
+VCC  
2mA  
−
I1  
R1  
A3  
Ω
1k  
Ω
52.6  
R2  
I2  
IO  
Voltage−Controlled  
Current Source  
10  
11  
IREF1  
IREF2  
Ω
2.5k  
amps  
volt  
40  
I
+ 4mA )  
ǒ
0.016  
)
Ǔ
e
e
+ e * e  
IN, IN 2 1  
O
R
S
Figure 1. Simplified Schematic of the XTR101  
6
ꢠ ꢆꢁ ꢡꢢ ꢡ  
www.ti.com  
SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
OPTIONAL EXTERNAL TRANSISTOR  
INSTALLATION AND  
The optional external transistor, when used, is connected  
in parallel with the XTR101 internal transistor. The purpose  
is to increase accuracy by reducing heat change inside the  
XTR101 package as the output current spans from  
4-20mA. Under normal operating conditions, the internal  
transistor is never completely turned off, as shown in  
Figure 2. This maintains frequency stability with varying  
external transistor characteristics and wiring capacitance.  
The actual current sharing between internal and external  
transistors is dependent on two factors:  
OPERATING INSTRUCTIONS  
BASIC CONNECTION  
See Figure 1 for the basic connection of the XTR101. A  
difference voltage applied between input pins 3 and 4 will  
cause a current of 4-20mA to circulate in the two-wire  
output loop (through RL, VPS, and D1). For applications  
requiring moderate accuracy, the XTR101 operates very  
cost-effectively with just its internal drive transistor. For  
more demanding applications (high accuracy in high gain),  
an external NPN transistor can be added in parallel with  
the internal one. This keeps the heat out of the XTR101  
package and minimizes thermal feedback to the input  
stage. Also, in such applications where the eIN full-scale  
is small (< 50mV) and RSPAN is small (< 150Ω), caution  
should be taken to consider errors from the external span  
circuit plus high amplification of offset drift and noise.  
1. relative geometry of emitter areas, and  
2. relative package dissipation (case size and thermal  
conductivity).  
For best results, the external device should have a larger  
base-emitter area and smaller package. It will, upon  
turn-on, take about [0.95(IO − 3.3mA)]mA. However, it will  
heat faster and take a greater share after a few seconds.  
4mA  
20mA  
16mA  
+VCC  
8
Ω(2)  
750  
12V, 200mW  
3.5mA  
0.5mA  
B
QEXT 23.6V, 377mW  
2N2222(1)  
12  
XTR101  
QINT 18mW  
Other Suitable Types  
Package  
Type  
VPS  
40V  
9
E
TO−225  
TO−220  
TO−220  
2N4922  
TIP29B  
TIP31B  
Ω
210  
3.47V, 60mW  
1.5mA  
Quiescent  
0.95V, 17mW  
IOUT  
Ω
52.6  
7
11  
Short−Circuit  
Worst−Case  
RL  
250  
10  
Ω
1mA  
1mA  
2mA  
18mA  
20mA  
NOTES: (1) An external transistor is used in the manufacturing test circuit for testing electrical specifications.  
(2) This resistor is required for the 2N2222 with VPS > 24V to limit power dissipation.  
Figure 2. Power Calculation of the XTR101 with an External Transistor  
7
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SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
Although any NPN of suitable power rating will operate  
with the XTR101, two readily available transistors are  
recommended:  
MAJOR POINTS TO CONSIDER WHEN  
USING THE XTR101  
1. The leads to RS should be kept as short as possible  
to reduce noise pick-up and parasitic resistance.  
1. 2N2222 in the TO-18 package. For power-supply  
voltages above 24V, a 750Ω, 1/2W resistor should be  
connected in series with the collector. This will limit the  
power dissipation to 377mW under the worst-case  
conditions; see Figure 2. Thus, the 2N2222 will safely  
operate below its 400mW rating at the upper  
temperature of +85°C. Heat sinking the 2N2222 will  
result in greatly reduced accuracy improvement and  
is not recommended.  
2. +VCC should be bypassed with a 0.01µF capacitor as  
close to the unit as possible (pin 8 to pin 7).  
3. Always keep the input voltages within their range of  
linear operation, +4V to +6V (e1 and e2 measured with  
respect to pin 7).  
4. The maximum input signal level (eINFS) is 1V with  
RS = ∞ and proportionally less as RS decreases.  
5. Always return the current references (pins 10 and 11)  
to the output (pin 7) through an appropriate resistor. If  
the references are not used for biasing or excitation,  
connect them together to pin 7. Each reference must  
have between 0V and +(VCC − 4V) with respect to  
pin 7.  
2. TIP29B in the TO-220 package. This transistor will  
operate over the specified temperature and output  
voltage range without a series collector resistor. Heat  
sinking the TIP29B will result in slightly less accuracy  
improvement. It can be done, however, when  
mechanical constraints require it.  
6. Always choose RL (including line resistance) so that  
the voltage between pins 7 and 8 (+VCC) remains  
within the 11.6V to 40V range as the output changes  
between the 4-20mA range (as shown in Figure 4).  
ACCURACY WITH AND WITHOUT AN  
EXTERNAL TRANSISTOR  
7. It is recommended that a reverse polarity protection  
diode (D1 in Figure 1) be used. This will prevent  
damage to the XTR101 caused by a momentary (such  
as a transient) or long-term application of the wrong  
polarity of voltage between pins 7 and 8.  
The XTR101 has been tested in a circuit using an external  
transistor. The relative difference in accuracy with and  
without an external transistor is shown in Figure 3. Notice  
that a dramatic improvement in offset voltage change with  
supply voltage is evident for any value of load resistor.  
8. Consider PC board layout which minimizes parasitic  
capacitance, especially in high gain.  
30  
25  
20  
15  
10  
60  
50  
40  
30  
20  
∆
Span = IO = 16mA  
1500  
1250  
Without External Transistor  
−
VPS 11.6V  
RL max =  
20mA  
Ω
RL = 100  
1000  
750  
500  
250  
0
Ω
RL = 600  
Ω
RL = 1k  
Operating  
Region  
With External Transistor  
RL = 600  
5
0
10  
0
Ω
RL = 1k  
Ω
Ω
RL = 100  
10  
20  
30  
40  
VCC (V)  
0
10  
20  
30  
40  
50  
60  
Power−Supply Voltage, VPS (V)  
Figure 3. Thermal Feedback Due to Change in  
Output Current  
Figure 4. Power-Supply Operating Range  
8
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SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
SELECTING THE R  
RSPAN is chosen so that a given full-scale input span  
(eINFS) will result in the desired full-scale output span of  
S
11  
D1  
10  
e1  
3
5
−
8
∆IOFS  
:
4−20mA  
−
eIN  
+
RS  
amps  
volt  
2mA  
40  
RS  
XTR101  
Adj.  
6
ǒ
Ǔ)  
ǒ Ǔ  
ƪ 0.016  
ƫ
DeIN + DIO + 16mA.  
µ
0.01 F  
+
+
24V  
RL  
eL  
−
−
Solving for RS:  
7
e2  
14  
+
2
4
Ω
1M  
R2  
+
1
IO  
40  
RS +  
e’2  
DI ńDeIN * 0.016 amps  
Offset  
Adjust  
O
volt  
(1)  
µ
0.01 F  
amps  
volt  
For example, if ∆eINFS = 100mV for ∆IOFS = 16mA,  
40  
I
+ 4mA )  
ǒ
2
0.016  
)
Ǔ
e
IN  
Ω
2.5k  
O
R
S
e
+ e  
2mA  
+5V  
IN  
40  
40  
0.16 * 0.016  
RS +  
+
ǒ
Ǔ
16mAń100mV * 0.016  
Figure 5. Basic Connection for Floating Voltage  
Source  
40  
0.144  
+
+ 278W  
See the Typical Characteristics for a plot of RS vs ∆eINFS  
.
D1  
11  
Note that in order not to exceed the 20mA upper range  
limit, eIN must be less than 1V when RS = ∞ and  
proportionately smaller as RS decreases.  
e1  
3
5
10  
−
8
1mA 1mA  
+
eIN  
−
BIASING THE INPUTS  
RS  
XTR101  
µ
0.01 F  
Because the XTR operates from a single supply, both e1  
and e2 must be biased approximately 5V above the  
voltage at pin 7 to assure linear response. This is easily  
done by using one or both current sources and an external  
resistor, R2. Figure 5 shows the simplest case—a floating  
voltage source eȀ2. The 2mA from the current sources  
flows through the 2.5kΩ value of R2 and both e1 and e2 are  
raised by the required 5V with respect to pin 7. For linear  
operation the constraint is:  
6
+
+
24V  
RL  
eL  
−
−
4
7
+
14  
2
e2  
+
Ω
100k  
1
Offset  
Adjust  
e2  
RT  
Ω
1M  
R2  
2.5k  
−
Ω
2mA  
+5V  
amps  
volt  
40  
R
I
+ 4mA )  
ǒ
+ eȀ + 1mA   R  
2 T  
0.016  
)
Ǔ
e
IN  
Alternate circuitry  
shown in Figure 8.  
O
S
+4V ≤ e1 ≤ +6V  
+4V ≤ e2 ≤ +6V  
e
IN  
µ
0.01 F  
Figure 6. Basic Connection for Resistive Source  
CMV AND CMR  
The offset adjustment is used to remove the offset voltage  
of the input amplifier. When the input differential voltage  
(eIN) equals zero, adjust for 4mA output.  
The XTR101 is designed to operate with a nominal 5V  
common-mode voltage at the input and will function  
properly with either input operating over the range of 4V to  
6V with respect to pin 7. The error caused by the 5V CMV  
is already included in the accuracy specifications.  
Figure 6 shows a similar connection for a resistive  
transducer. The transducer could be excited either by one  
(as shown) or both current sources. Also, the offset  
adjustment has higher resolution compared to Figure 5.  
If the inputs are biased at some other CMV, then an input  
offset error term is (CMV − 5)/CMRR, where CMR is in dB,  
and CMRR is in V/V.  
9
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SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
SIGNAL SUPPRESSION AND ELEVATION  
In some applications, it is desired to have suppressed zero  
range (input signal elevation) or elevated zero range (input  
signal suppression). This is easily accomplished with the  
XTR101 by using the current sources to create the  
suppression/elevation voltage. The basic concept is  
shown in Figure 7 and Figure 8(a). In this example, the  
sensor voltage is derived from RT (a thermistor, RTD, or  
other variable resistance element) and excited by one of  
the 1mA current sources. The other current source is used  
to create the elevated zero range voltage. Figure 8(b), (c),  
and (d) show some of the possible circuit variations. These  
circuits have the desirable feature of noninteractive span  
and suppression/elevation adjustments.  
−
−
1mA  
1mA  
1mA  
1mA  
eIN  
eIN  
+
+
+
+
e’2  
+
RT  
V4  
R4  
e’2  
−
RT  
+
−
V4  
R4  
−
−
2mA  
2mA  
−
eIN = (e’2 V4)  
eIN = (e’2 + V4)  
×
V4 = 1mA R4  
×
e’2 = 1mA RT  
×
V4 = 1mA R4  
×
e’2 = 1mA RT  
(a) Elevated Zero Range  
(b) Suppressed Zero Range  
Note: It is not recommended to use the optional offset  
voltage null (pins 1, 2, and 14) for elevation/suppression.  
This trim capability is used only to null the amplifier’s input  
offset voltage. In many applications the already low offset  
voltage (typically 20µV) will not need to be nulled at all.  
Adjusting the offset voltage to non-zero values will disturb  
the voltage drift by 0.3µV/°C per 100µV or induced offset.  
2mA  
−
2mA  
e’2  
−
eIN  
eIN  
+
+
−
+
+
V4  
R4  
+
+
V4  
R4  
e’2  
−
−
−
20  
Span Adjust  
2mA  
2mA  
−
e
IN = (e’2 V4)  
eIN = (e’2 + V4)  
×
×
V4 = 2mA R4  
V4 = 2mA R4  
15  
(c) Elevated Zero Range  
(d) Suppressed Zero Range  
Figure 8. Elevation and Suppression Circuits  
10  
Suppressed  
Zero  
Range  
Elevated  
Zero  
Range  
APPLICATION INFORMATION  
5
0
The small size, low offset voltage and drift, excellent  
linearity, and internal precision current sources make the  
XTR101 ideal for a variety of two-wire transmitter  
applications. It can be used by OEMs producing different  
types of transducer transmitter modules and by data  
acquisition systems manufacturers who gather transducer  
data. Current-mode transmission greatly reduces noise  
interference. The two-wire nature of the device allows  
economical signal conditioning at the transducer. Thus the  
XTR101 is, in general, very suitable for individualized and  
special-purpose applications.  
−
0 +  
eIN (V)  
Figure 7. Elevation and Suppression Graph  
10  
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EXAMPLE 1  
An RTD transducer is shown in Figure 9.  
e1  
D1  
11  
3
10  
−
Given a process with temperature limits of +25°C and  
+150°C, configure the XTR101 to measure the  
temperature with a platinum RTD which produces 100Ω at  
0°C and 200Ω at +266°C (obtained from standard RTD  
tables). Transmit 4mA for +25°C and 20mA for +150°C.  
8
5
−
RS  
eIN  
XTR101  
µ
0.01 F  
+
6
4
+
+
24V  
RL  
eL  
COMPUTING RS:  
−
−
+
7
+
R4  
The sensitivity of the RTD is ∆R/∆T = 100Ω/266°C. When  
excited with a 1mA current source for a 25°C to 150°C  
range (a 125°C span), the span of eIN is  
1mA × (100Ω/266°C) × 125°C = 47mV = ∆eIN.  
e2  
RT  
V4  
−
+
e’2  
−
R2  
40  
From Equation 1, RS +  
DI ńDeIN * 0.016 amps  
O
volt  
µ
0.01 F  
40  
16mAń47mV * 0.016AńV  
40  
0.3244  
RS +  
+
+ 123.3W  
Figure 9. Circuit for Example 1  
Span adjustment (calibration) is accomplished by  
trimming RS.  
EXAMPLE 2  
A thermocouple transducer is shown in Figure 10.  
COMPUTING R4:  
Given a process with temperature (T1) limits of 0°C and  
+1000°C, configure the XTR101 to measure the  
temperature with a type J thermocouple that produces a  
58mV change for 1000°C change. Use a semiconductor  
diode for cold junction compensation to make the  
measurement relative to 0°C. This is accomplished by  
supplying a compensating voltage (VR6) equal to that  
normally produced by the thermocouple with its cold  
junction (T2) at ambient. At a typical ambient of +25°C, this  
is 1.28mV (obtained from standard thermocouple tables  
with reference junction of 0°C). Transmit 4mA for T1 = 0°C  
and 20mA for T1 = +1000°C. Note: eIN = e2 − e1 indicates  
that T1 is relative to T2.  
o
(
)
At ) 25 C, eȀ2 + 1mA RT ) DRT  
100W  
o
+ 1mAƪ100W )  
  25 Cƫ  
266oC  
(
)
+ 1mA 109.4W + 109.4mV  
In order to make the lower range limit of 25°C correspond  
to the output lower range limit of 4mA, the input circuitry  
shown in Figure 9 is used.  
eIN, the XTR101 differential input, is made 0 at 25°C or:  
eȀ2 C * V4  
o
25  
thus, V4 + eȀ2 C + 109.4mV  
o
25  
V4  
1mA  
109.4mV  
1mA  
R4 +  
+
+ 109.4W  
1mA  
D
1mA  
R5  
COMPUTING R2 AND CHECKING CMV:  
Ω
2k  
11  
3
10  
−
At ) 25oC, eȀ2 + 109.4mV  
8
o
(
)
At ) 150 C, eȀ2 + 1mA RT ) DRT  
R6  
+
e1  
−
Ω
51  
100W  
o
+ 1mAƪ100W )  
+ 156.4mV  
  150 Cƫ  
eIN  
XTR101  
266oC  
Thermocouple  
TTC  
7
4
Since both eȀ2 and V4 are small relative to the desired 5V  
common-mode voltage, they may be ignored in computing  
R2 as long as the CMV is met.  
+
+
e2  
−
µ
0.01 F  
VTC  
−
+
V4  
R4  
Ω
2.5k  
Temperature T1  
5V  
R2 +  
+ 2.5kW  
Temperature T2 = TD  
2mA  
e2 min + 5V ) 0.1094V  
e2 max + 5V ) 0.1564V  
e1 + 5V ) 0.1094V  
The 4V to 6V CMV  
requirement is met.  
Figure 10. Thermocouple Input Circuit with Two  
Temperature Regions and Diode (D) Cold  
Junction Compensation  
ǁ
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ESTABLISHING RS:  
R5 is chosen as 2kΩ to be much larger than the resistance  
of the diode. Solving for R6 yields 51Ω.  
The input full-scale span is 58mV (∆eINFS = 58mV).  
RS is found from Equation 1.  
40  
RS +  
DI ńDeIN * 0.016 amps  
1mA  
O
volt  
40  
16mAń58mV * 0.016AńV  
40  
0.2599  
+
+
+ 153.9W  
+
R5  
V5  
−
+
VD  
−
SELECTING R4:  
D
+
R4 is chosen to make the output 4mA at TTC = 0°C  
(VTC = −1.28mV) and TD = +25°C (VD = 0.6V); see  
Figure 10.  
R6  
V6  
−
VTC will be −1.28mV when TTC = 0°C and the reference  
junction is at +25°C. e1 must be computed for the condition  
of TD = +25°C to make eIN = 0V.  
VD 25 C + 600mV  
o
Figure 11. Cold Junction Compensation Circuit  
THERMOCOUPLE BURN-OUT INDICATION  
51  
2051  
ǒ Ǔ+ 14.9mV  
e1 25 C + 600mV  
o
eIN + e2 * e1 + VTC ) V4 * e1  
In process control applications it is desirable to detect  
when a thermocouple has burned out. This is typically  
done by forcing the two-wire transmitter current to either  
limit when the thermocouple impedance goes very high.  
The circuits of Figure 16 and Figure 17 inherently have  
downscale indication. When the impedance of the  
thermocouple gets very large (open) the bias current  
flowing into the + input (large impedance) will cause IO to  
go to its lower range limit value (about 3.8mA). If upscale  
indication is desired, the circuit of Figure 18 should be  
used. When TC opens, the output will go to its upper range  
limit value (about 25mA or higher).  
With eIN = 0 and VTC = −1.28mV,  
V4 + e1 ) eIN * VTC  
(
)
+ 14.9mV ) 0V * * 1.28mV  
(
)
1mA R4 + 16.18mV  
R4 + 16.18W  
COLD JUNCTION COMPENSATION:  
A temperature reference circuit is shown in Figure 11.  
The diode voltage has the form:  
IDIODE  
ISAT  
KT  
q
OPTIONAL INPUT OFFSET VOLTAGE TRIM  
VD +  
ln  
The XTR101 has provisions for nulling the input offset  
voltage associated with the input amplifiers. In many  
applications the already low offset voltages (30µV max for  
the B grade and 60µV max for the A grade) will not need  
to be nulled at all. The null adjustment can be done with a  
potentiometer at pins 1, 2, and 14; see Figure 5 and  
Figure 6. Either of these two circuits may be used.  
NOTE: It is not recommended to use this input offset  
voltage nulling capability for elevation or suppression. See  
the Signal Suppression and Elevation section for the  
proper techniques.  
Typically at T2 = +25°C, VD = 0.6V and ∆VD/∆T = −2mV/°C.  
R5 and R6 form a voltage divider for the diode voltage VD.  
The divider values are selected so that the gradient  
∆VD/∆T equals the gradient of the thermocouple at the  
reference temperature. At +25°C this is approximately  
52µV/°C (obtained from a standard thermocouple table);  
therefore,  
DTC  
DT  
DVD  
DT R5 ) R6  
R6  
ǒ Ǔ  
+
+
52mV  
2000mV  
°
C
R6  
ǒ Ǔ  
°
C
R5 ) R6  
(2)  
12  
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OPTIONAL BANDWIDTH CONTROL  
µ
0.0047 F  
1mA  
Low-pass filtering is recommended where possible and  
can be done by either one of two techniques; see  
Figure 12. C2 connected to pins 3 and 4 will reduce the  
bandwidth with a cutoff frequency given by:  
(1)  
R3  
11  
3
−
1mA  
R1  
C2  
15.9  
XTR101  
fCO  
+
(
)( )  
R1 ) R2 ) R3 ) R4 C2 ) 3pF  
(1)  
This method has the disadvantage of having fCO vary with  
R1, R2, R3, R4, and it may require large values of R3 and  
R4. The other method, using C1, will use smaller values of  
capacitance and is not a function of the input resistors. It  
is, however, more subject to nonlinear distortion caused by  
slew rate limiting. This is normally not a problem with the  
slow signals associated with most process control  
transducers. The relationship between C1 and fCO is  
shown in the Typical Characteristics.  
R4  
4
13  
+
C1  
12  
R2  
NOTE: (1) R3 and R4 should be equal if used.  
2
Internally eNOISE RTI  
=
e2  
e2  
+
INPUT STAGE  
OUTPUT STAGE  
Gain  
Figure 12. Optional Filtering  
APPLICATION CIRCUITS  
Voltage  
Reference  
+
MC1403A  
VR = 2.5V  
−
100pF  
XTR101  
V+  
IO  
OPA27  
(4−20 mA)  
−
V
R1  
R2  
Ω
125  
Ω
500  
I
(0−20mA)  
Ȁ
O
R
V
R
1
R
Ȁ
+ ǒ1 ) Ǔ I  
I
*
+ 1.25 I * 5mA  
O
NOTE:  
O
O
R
2
2
Other conversions are readily achievable by  
changing the reference and ratio of R1 to R2.  
Figure 13. 0-20mA Output Converter  
13  
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2mA  
0.9852mA  
1.0147mA  
Ω
1.8k  
−
R
R
LM129  
6.9V  
Voltage  
Ref  
Ω
300  
RS  
XTR101  
R
R
+
µ
Ω
4.7k  
0.01 F  
Figure 14. Bridge Input, Voltage Excitation  
1mA  
1mA  
This circuit has downscale  
burn−out indication.  
2mA  
R
R
R
Ω
2k  
−
Ω
300  
−
Type J  
−
+
R
51Ω  
RS  
20Ω  
XTR101  
RS  
XTR101  
J
+
Zero  
+
Adjust  
Ω
2.2k  
Ω
2.5k  
Figure 15. Bridge Input, Current Excitiation  
Figure 17. Thermocouple Input with Diode Cold  
Junction Compensation  
1mA  
1mA  
This circuit has downscale  
burn−out indication.  
This circuit has upscale  
burn−out indication.  
1mA  
1mA  
+
−
−
−
Type J  
+
−
RS  
Ω
20  
RS  
20  
Ω
RTD  
100Ω  
XTR101  
RTD  
XTR101  
15Ω  
Ω
100  
Ω
15  
Zero  
Zero  
Adjust  
Adjust  
+
+
2.5kΩ  
2.5kΩ  
Figure 16. Thermocouple Input with RTD Cold  
Junction Compensation  
Figure 18. Thermocouple Input with RTD Cold  
Junction Compensation  
14  
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11  
I1  
I2  
10  
+VCC  
8
+VCC  
−
3
OPA21  
VREF  
Out  
R1  
R2  
XTR101  
µ
0.01 F  
15V  
4
+
7
Ω
2.5k  
VREF = ImA R2  
Figure 19. Dual Precision Current Sources Operated from One Supply  
Isolation  
Barrier  
+15V  
P+  
+V2  
C2  
−
Ω
1k  
8
µ
1 F  
V+  
E
722  
−
V2  
µ
1 F  
−
−
V
C1 +V1 V1  
4−20 mA  
+
+15V  
30V  
−
∆
eIN  
XTR101  
7
Ω
1M  
10  
+
+
−
Ω
1M  
15V  
12  
15  
7
2
4
3
Ω
250  
ISO100  
(1)  
VOUT  
+1V to +5V  
9
8
IREF2  
17  
−
16  
18  
NOTE: (1) Can be shifted and amplified  
using ISO100 current sources.  
IREF1  
Figure 20. Isolated Two-Wire Current Loop  
15  
ꢠ ꢆ ꢁ ꢡꢢ ꢡ  
www.ti.com  
SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
DETAILED ERROR ANALYSIS  
EXAMPLE 3  
See the circuit in Figure 9 with the XTR101BG  
specifications and the following conditions: RT = 109.4Ω at  
25°C, RT = 156.4Ω at 150°C, IO =4mA at 25°C, IO = 20mA  
at 150°C, RS = 123.3Ω, R4 = 109Ω, RL = 250Ω,  
The ideal output current is:  
IO IDEAL + 4mA ) K eIN  
(3)  
RLINE = 100Ω, VDI = 0.6V, and VPS = 24V  
0.5%.  
amps  
volt  
40  
RS  
) ǒ Ǔ  
where K is the span (gain) term, ǒ0.016  
Ǔ
Determine the % error at the upper and lower range  
values.  
In the XTR101 there are three major components of error:  
A. AT THE LOWER RANGE VALUE (T = +255C)  
sO + IOS RTO +" 6mA  
1. σO = errors associated with the output stage.  
2. σS = errors associated with span adjustment.  
3. σI = errors associated with the input stage.  
ƪe 2ƫ  
)e  
1
ȱ
ȳ
ȴ
* 5Vȧ  
DVCC  
2
ǒ
Ǔ
)
sI + VOSI ) IBI DR ) IOSI R4  
)
ȧ
PSRR  
CMRR  
Ȳ
The transfer function including these errors is:  
DR + RT 25 * R4 + 109.4 * 109 [ 0  
o
C
(
)
(
)
ǒ
Ǔ
ǒ
Ǔ
(
DVCC + 24   0.005 ) 4mA 250W ) 100W ) 0.6V  
)
IO ACTUAL + 4mA ) sO ) K 1 ) sS eIN ) sI  
(4)  
+ 120mV ) 1400mV ) 600mV + 2120mV  
When this expression is expanded, second-order terms  
(σS, σI) dropped, and terms collected, the result is:  
ǒ
Ǔ
ǒ
Ǔ
e1 + 2mA   2.5kW ) 1mA   109W  
+ 5.109V  
e2 + 2mA   2.5kW ) 1mA   109.4W  
+ 5.1094V  
ǒ
Ǔ
IO ACTUAL + 4mA ) sO ) K eIN ) KsI ) KsS eIN  
(5)  
ǒ
Ǔ
ǒ
Ǔ
The error in the output current is IO ACTUAL − IO IDEAL and  
can be found by subtracting Equation 3 from Equation 5.  
ǒ
Ǔ
e1 ) e2  
* 5V + 0.1092V  
2
IO ERROR + sO ) KsI ) KsS eIN  
(6)  
PSRR + 3.16   105 for 110dB  
CMRR + 31.6   103 for 90dB  
This is a general error expression. The composition of  
each component of error depends on the circuitry inside  
the XTR101 and the particular circuit in which it is applied.  
The circuit of Figure 9 will be used to illustrate the  
principles.  
(
)
s1 + 30mV ) 150nA   0 ) 20nA   109W )  
2120mV  
0.1092V  
)
(10)  
3.16   105 3.16   103  
+ 30mV ) 2.18mV ) 6.7mV ) 3.46mV  
+ 42.34mV  
sS + eNONLIN ) eSPAN  
sO + IOS RTO  
(7)  
(8)  
sS + eNONLINEARITY ) eSPAN  
ǒe 2Ǔ  
)e  
1
2
ǒ
Ǔ
+ 0.0001 ) 0 assumes trim of RS  
IO ERROR + sO ) K sI ) K sS eIN  
40  
* 5V  
DVCC  
PSRR  
ǒ
Ǔ
)
sI + VOSI ) IB1 ) R4 * IB2 RT  
)
CMRR  
(9)  
40  
K + 0.016 )  
+ 0.016 )  
The term in parentheses may be written in terms of offset  
current and resistor mismatches as IB1 ∆R + IOSȀ R4.  
123.3W  
RS  
amps  
volts  
+ 0.340  
VOSI(1) = input offset voltage.  
IB1(1), IB2(1) = input bias current.  
IOSI(1) = input offset current.  
IOS RTO(1) = output offset current error.  
eIN + e2 * V4 + IREF1 RT 25 C * IREF2 R4  
o
Since RT 25 C = R4:  
°
ǒ
Ǔ
eIN + IREF1 * IREF2 R4 + 0.4mA   109W  
+ 43.6mV  
∆R = RT − R4 = mismatch in resistor.  
∆VCC = change supply voltage between pins 7 and 8  
Since the maximum mismatch of the current references is  
away from 24V nominal.  
0.04% of 1mA = 0.4µA:  
IO error + 6mA ) 0.34AńV   42.34mV )  
PSRR(1) = power-supply rejection ratio.  
CMRR(1) = common-mode rejection ratio.  
εNONLIN(1) = span nonlinearity.  
εSPAN(1) = span equation error.  
Untrimmed error = 5% max. May be trimmed to zero.  
ǒ
Ǔ
ǒ
Ǔ
0.34AńV   0.0001   43.6mV  
+ 6mA ) 14.40mA ) 0.0015mA + 20.40mA  
20.40mA  
% error +  
  100%  
16mA  
(1)  
0.13% of span at lower range value.  
These items can be found in the Electrical Characteristics.  
16  
ꢠ ꢆꢁ ꢡꢢ ꢡ  
www.ti.com  
SBOS146A − OCTOBER 1986 − REVISED AUGUST 2004  
B. AT THE UPPER RANGE VALUE (T = +150°C)  
CONCLUSIONS  
DR + RT 150 * R4 + 156.4 * 109.4 + 47W  
o
Lower Range: From Equation 10, it is observed that the  
predominant error term is the input offset voltage (30µV for  
the B grade). This is of little consequence in many  
applications. VOS RTI can, however, be nulled using the  
plots shown in Figure 5 and Figure 6. The result is an error  
of 0.06% of span instead of 0.13% of span.  
C
ǒ
Ǔ
ǒ
Ǔ
DVCC + 24   0.005 ) 20mA 250W ) 100W ) 0.6V  
+ 7720mV  
e1 + 5.109V  
ǒ
Ǔ
ǒ
Ǔ
e2 + 2mA   2.5kW ) 1mA   156.4W  
+ 5.156V  
Upper Range: From Equation 11, the predominant errors  
are IOS RTO (6µA), VOS RTI (30µV), and IB (150nA), max,  
B grade. Both IOS and VOS can be trimmed to zero;  
however, the result is an error of 0.09% of span instead of  
0.19% of span.  
ǒ
Ǔ
e1 * e2  
* 5V + 0.1325V  
2
sO + 6mA  
s1 + 30mV ) 150nA   47W ) 20nA   190W )  
ǒ
Ǔ
RECOMMENDED HANDLING PROCEDURES  
FOR INTEGRATED CIRCUITS  
7720mV  
0.1325V  
)
3.16   105 3.16   103  
All semiconductor devices are vulnerable, in varying  
degrees, to damage from the discharge of electrostatic  
energy. Such damage can cause performance  
degradation or failure, either immediate or latent. As a  
general practice, we recommend the following handling  
procedures to reduce the risk of electrostatic damage:  
+ 30mV ) 9.23mV ) 24mV ) 4.19mV  
+ 67.42mV  
sS + 0.0001  
eIN + eȀ2 * V4 + IREF1 RT 150 C * IREF2 R4  
o
ǒ
Ǔ
ǒ
Ǔ
+ 1mA   156.4W * 1mA   109W  
+ 47mV  
1. Remove the static-generating materials (such as  
untreated plastic) from all areas that handle  
microcircuits.  
IO error + sO ) K sI ) K sS eIN  
(11)  
ǒ
Ǔ
+ 6mA ) 0.34AńV   67.42mV )  
2. Ground all operators, equipment, and work stations.  
ǒ
Ǔ
3. Transport and ship microcircuits, or products  
incorporating microcircuits, in static-free, shielded  
containers.  
0.34AńV   0.0001   47000mV  
+ 6mA ) 22.92mA ) 1.60mA  
+ 30.52mA  
4. Connect together all leads of each device by means  
of a conductive material when the device is not  
connected into a circuit.  
30.52mA  
% error +  
  100%  
16mA  
0.19% of span at upper range value.  
5. Control relative humidity to as high a value as practical  
(50% recommended).  
17  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Jun-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
XTR101AG  
XTR101AP  
NRND  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
NRND  
CDIP SB  
PDIP  
JD  
N
14  
14  
14  
16  
16  
16  
16  
14  
1
25  
Green (RoHS  
& no Sb/Br)  
AU  
N / A for Pkg Type  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
XTR101APG4  
XTR101AU  
PDIP  
N
25  
Green (RoHS  
& no Sb/Br)  
SOIC  
DW  
DW  
DW  
DW  
JD  
40  
Green (RoHS  
& no Sb/Br)  
XTR101AU/1K  
XTR101AU/1KG4  
XTR101AUG4  
XTR101BG  
SOIC  
1000  
1000  
40  
Green (RoHS  
& no Sb/Br)  
SOIC  
Green (RoHS  
& no Sb/Br)  
SOIC  
Green (RoHS  
& no Sb/Br)  
CDIP SB  
1
Green (RoHS  
& no Sb/Br)  
AU  
N / A for Pkg Type  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Jun-2012  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
6-Jun-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
XTR101AU/1K  
SOIC  
DW  
16  
1000  
330.0  
16.4  
10.75 10.7  
2.7  
12.0  
16.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
6-Jun-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SOIC DW 16  
SPQ  
Length (mm) Width (mm) Height (mm)  
346.0 346.0 33.0  
XTR101AU/1K  
1000  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are  
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where  
mandated by government requirements, testing of all parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,  
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information  
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a  
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Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied  
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business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional  
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all  
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Applications  
www.ti.com/audio  
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Copyright © 2012, Texas Instruments Incorporated  
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