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XTR111

型号：

XTR111

描述：

精密电压 ​​- 电流转换器/发送器[ Precision Voltage-to-Current Converter/Transmitter ]

品牌：

TI[ TEXAS INSTRUMENTS ]

页数：

32 页

PDF大小：

1171 K

下载PDF手册
XTR111  
www.ti.com  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
Precision Voltage-to-Current  
Converter/Transmitter  
Check for Samples: XTR111  
1
FEATURES  
DESCRIPTION  
The XTR111 is  
a
precision voltage-to-current  
2
•
EASY-TO-DESIGN INPUT/OUTPUT RANGES:  
0mA–20mA, 4mA–20mA, 5mA–25mA AND  
VOLTAGE OUTPUTS  
NONLINEARITY: 0.002%  
LOW OFFSET DRIFT: 1μV/°C  
ACCURACY: 0.015%  
SINGLE-SUPPLY OPERATION  
WIDE SUPPLY RANGE: 7V to 44V  
OUTPUT ERROR FLAG (EF)  
OUTPUT DISABLE (OD)  
ADJUSTABLE VOLTAGE REGULATOR:  
3V to 15V  
converter designed for the standard 0mA–20mA or  
4mA–20mA analog signals, and can source up to  
36mA. The ratio between input voltage and output  
current is set by the single resistor RSET. The circuit  
can also be modified for voltage output.  
•
•
•
•
•
•
•
•
An external P-MOSFET transistor ensures high  
output resistance and a broad compliance voltage  
range that extends from 2V below the supply voltage,  
VVSP, to voltages well below GND.  
The adjustable 3V to 15V sub-regulator output  
provides the supply voltage for additional circuitry.  
The XTR111 is available in MSOP and DFN  
surface-mount packages.  
APPLICATIONS  
24V  
•
UNIVERSAL VOLTAGE-CONTROLLED  
CURRENT SOURCE  
CURRENT OR VOLTAGE OUTPUT FOR 3-WIRE  
SENSOR SYSTEMS  
PLC OUTPUT PROGRAMMABLE DRIVER  
CURRENT-MODE SENSOR EXCITATION  
1
9
VSP  
XTR111  
OD  
EF  
Output Disable  
Output Failure  
8
REGF  
REGS  
•
I- Mirror  
5
4
Regulator  
Out  
IS  
2
•
•
15W  
(1)  
S
Q2  
Q1  
VG  
3
G
3V  
D
ISET  
10nF  
15W  
6
Signal  
Input  
V
IN  
Load  
0mA to 20mA  
4mA to 20mA  
(
Load Ground)  
GND  
SET  
10  
7
V
R
VIN  
I
= 10  
R
(
)
OUT  
SET  
SET  
I
= 10 I  
OUT  
SET  
NOTE: (1) See Application Information,  
External Current Limit Circuits for other  
options.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006–2011, Texas Instruments Incorporated  
XTR111  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ORDERING INFORMATION(1)  
PACKAGE  
PRODUCT  
PACKAGE-LEAD  
DFN-10  
DESIGNATOR  
PACKAGE MARKING  
DRC  
BSV  
XTR111  
MSOP-10  
DGQ  
CCM  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the  
device product folder at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS(1) (2)  
Over operating free-air temperature range (unless otherwise noted)  
XTR111  
+44  
UNIT  
V
Power Supply Voltage, VVSP  
Voltage at SET(3)  
–0.5 to +14  
V
(4)  
Voltage at IS(3)  
(VVSP) – 5.5 to (VVSP) + 0.5  
–0.5 to (VVSP) + 0.5  
–0.5 to (VVSP) + 0.5  
±25  
V
Voltage at REGS, REGF, VIN, OD, EF  
V
Voltage at REGF, VG  
Current into any pin(3)  
V
(4) (5)  
mA  
Output Short-Circuit Duration(6)  
:
VG  
Continous to common and VVSP  
Continous to common and VVSP  
–55 to +125  
REGF  
Operating Temperature  
Storage Temperature  
°C  
°C  
V
–65 to +150  
Electrostatic Discharge Rating (HBM)  
2000  
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those specified is not supported.  
(2) Refer to the Package Option Addendum at the end of this document for lead temperature ratings.  
(3) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails must  
be current limited.  
(4) The IS pin current absolute maximum rating is +25mA and –50mA.  
(5) See the following sections Explanation of Pin Functions, External MOSFET, and Voltage Regulator in Application Information regarding  
safe voltage ranges and currents.  
(6) See text in Application Information regarding safe voltage ranges and currents.  
2
Copyright © 2006–2011, Texas Instruments Incorporated  
 
XTR111  
www.ti.com  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
ELECTRICAL CHARACTERISTICS  
Boldface limits apply over the specified temperature range: TA = –40°C to +85°C.  
All specifications at TA = +25°C, VVSP = +24V, RSET = 2.0kΩ, REGF connected to REGS; OD = Low, External FET connected,  
unless otherwise noted.  
XTR111  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
TRANSMITTER  
Transfer Function  
Specified Output Current  
IOUT = 10 × VVIN/RSET  
0.1 25  
IOUT  
Specified Performance(1)  
Derated Performance(2)  
mA  
mA  
0 to 36  
42 ± 6  
0.002  
0.004  
0.002  
0.0002  
0.0001  
0.015  
5
Current Limit for Output Current  
mA  
(2) (3)  
Nonlinearity, IOUT/ISET  
0.1mA to 25mA  
0.1mA to 36mA  
IOUT = 4mA(1)  
0.02  
% of Span  
% of Span  
% of Span  
% of Span/°C  
% of Span/V  
% of Span  
ppm/°C  
% of Span/V  
GΩ  
Offset Current  
IOS  
0.02  
0.001  
0.005  
0.1  
vs Temperature  
vs Supply, VVSP  
8V to 40V Supply  
0.1mA to 25mA  
(2)  
Span Error, IOUT/ISET  
vs Temperature(1) (2)  
vs Supply(1)  
0.0001  
> 1  
(4)  
Output Resistance  
From Drain of QEXT  
Output Leakage  
OD = high  
< 1  
μA  
Input Impedance (VIN)  
Input Bias Current (VIN)  
Input Offset Voltage(2)  
vs Temperature  
2.4/30  
15  
GΩ/pF  
nA  
IB  
25  
VOS  
VVIN = 20mV  
0.3  
1.5  
mV  
1.5  
μV/°C  
Input Voltage Range(5)  
Noise, Referred to Input(2)  
VVIN  
0 to 12  
2.5  
V
0.1Hz to 10Hz; IOUT = 4mA  
μVPP  
See Dynamic Performance  
Section  
Dynamic Response  
(1) Includes input amplifier, but excludes RSET tolerance. Offset current is the deviation from the current ratio of ISET to IIS (output current).  
(2) See Typical Characteristics.  
(3) Span is the change in output current resulting from a full-scale change in input voltage.  
(4) Within compliance range limited by (+VVSP – 2V) +VDS required for linear operation of QEXT  
(5) See Application Information, Input Voltage section.  
.
Copyright © 2006–2011, Texas Instruments Incorporated  
3
XTR111  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
www.ti.com  
ELECTRICAL CHARACTERISTICS (continued)  
Boldface limits apply over the specified temperature range: TA = –40°C to +85°C.  
All specifications at TA = +25°C, VVSP = +24V, RSET = 2.0kΩ, REGF connected to REGS; OD = Low, External FET connected,  
unless otherwise noted.  
XTR111  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V-Regulator Output (REGF)  
Voltage Reference(6)  
vs Temperature(6)  
vs Supply(6)  
Bias Current into REGS(6)  
RLOAD = 5kΩ  
2.85  
3.0  
30  
3.15  
V
ppm/°C  
mV/V  
μA  
0.1  
0.8  
3
Load Regulation  
0.6mA to 5mA  
5
mV/mA  
mV/V  
mA  
Supply Regulation(6)  
Output Current  
RLOAD = 5kΩ  
0.01  
5
Short-Circuit Output Current  
DIGITAL INPUT (OD)  
VIL Low-Level Threshold  
VIH High-Level Threshold  
Internal Pull-Up Current  
DIGITAL OUTPUT (EF)  
IOH Leakage Current (Open Drain)  
VOL Low-Level Output Voltage  
IOL Current to 400mV Level  
POWER SUPPLY  
21  
mA  
0.6  
0.8  
V
V
1.8  
V
OD < 5.5V  
4
1
2
μA  
μA  
V
IEF = 2.2mA  
VEF = 400mV  
mA  
Specified Voltage Range  
+8  
+40  
550  
V
V
Operating Voltage  
+7 to +44  
450  
Quiescent Current(6)  
TEMPERATURE RANGE  
Specified Range  
IQ  
IOUT = 0mA  
μA  
–40  
–55  
+85  
°C  
°C  
Operating Range  
+125  
Package Thermal Impedance, θJA  
DFN  
70  
63  
°C/W  
°C/W  
MSOP  
(6) See Typical Characteristics.  
4
Copyright © 2006–2011, Texas Instruments Incorporated  
XTR111  
www.ti.com  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
PIN CONFIGURATIONS  
DGQ PACKAGE  
MSOP-10  
DRC PACKAGE  
DFN-10  
TOP VIEW  
TOP VIEW  
VSP  
1
2
3
4
5
10 GND  
Exposed  
Thermal  
Die Pad  
on  
1
2
3
4
5
10  
9
GND  
OD  
VSP  
IS  
Exposed  
Thermal  
Die Pad  
on  
IS  
VG  
9
8
7
6
OD  
EF  
Underside.  
(Must be  
connected  
to GND)  
8
EF  
VG  
Underside.  
(Must be  
connected  
to GND)  
REGS  
REGF  
SET  
VIN  
7
SET  
VIN  
REGS  
REGF  
6
Pad  
Pad  
PIN DESCRIPTIONS  
PIN  
1
NAME  
VSP  
IS  
FUNCTION  
Positive Supply  
Source Connection  
Gate Drive  
2
3
VG  
4
REGS  
REGF  
VIN  
Regulator Sense  
Regulator Force  
Input Voltage  
5
6
7
SET  
EF  
Transconductance Set  
Error Flag (Active Low)  
8
9
OD  
Output Disable (Active High)  
Negative Supply  
10  
Pad  
GND  
Pad  
Exposed Thermal Pad must be connected to GND  
Copyright © 2006–2011, Texas Instruments Incorporated  
5
XTR111  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
www.ti.com  
TYPICAL CHARACTERISTICS  
At TA = +25°C and VVSP = +24V, unless otherwise noted.  
QUIESCENT CURRENT vs SUPPLY VOLTAGE  
QUIESCENT CURRENT vs TEMPERATURE  
550  
530  
510  
490  
470  
450  
430  
410  
390  
370  
350  
700  
650  
600  
550  
500  
450  
400  
350  
300  
5
10  
15  
20  
25  
30  
35  
40  
45  
-75  
-50  
-25  
0
25  
50  
75  
100  
125  
Supply Voltage (V)  
Temperature (°C)  
Figure 1.  
Figure 2.  
GAIN vs FREQUENCY  
POWER-SUPPLY REJECTION RATIO vs FREQUENCY  
40  
30  
140  
See Applications Information,  
Dynamic Performance  
RSET = 2kW, No Bypass Cap  
120  
100  
80  
60  
40  
20  
0
RSET = 2kW, RLOAD = 2kW  
RSET = 2kW, RLOAD = 600W  
RSET = 2kW, RLOAD = 200W  
20  
10  
0
-10  
-20  
-30  
-40  
Gain = VLOAD/VVIN  
1k  
10k  
100k  
1M  
10M  
10  
100  
1k  
10k  
100k  
1M  
Frequency (Hz)  
Frequency (Hz)  
Figure 3.  
Figure 4.  
0.1Hz to 10Hz NOISE, RTI  
INPUT-REFERRED NOISE SPECTRUM  
100m  
10m  
1m  
IOUT = 4mA  
IOUT = 2mA  
100n  
10n  
1s/div  
1
10  
100  
1k  
10k  
100k  
Frequency (Hz)  
Figure 5.  
Figure 6.  
6
Copyright © 2006–2011, Texas Instruments Incorporated  
XTR111  
www.ti.com  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C and VVSP = +24V, unless otherwise noted.  
NONLINEARITY DISTRIBUTION  
GAIN ERROR DISTRIBUTION  
Gain Error (%)  
Nonlinearity (%)  
Figure 7.  
Figure 8.  
NONLINEARITY DRIFT DISTRIBUTION  
NONLINEARITY vs TEMPERATURE  
(IOUT = 0.1mA to 25mA; T = –55°C to +125°C)  
0.03  
0.02  
0.1mA to 25mA  
0.01  
0
4mA to 20mA  
-0.01  
-0.02  
-0.03  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
-75  
-50  
-25  
0
25  
50  
75  
100  
125  
Nonlinearity Drift (ppm/°C)  
Temperature (°C)  
Figure 9.  
Figure 10.  
GAIN ERROR DRIFT DISTRIBUTION  
GAIN ERROR vs TEMPERATURE  
(IOUT = 0.1mA to 25mA; T = –55°C to +125°C)  
0.15  
0.10  
0.05  
0
4mA to 20mA  
-0.05  
-0.10  
-0.15  
0.1mA to 25mA  
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1  
0
-75  
-50  
-25  
0
25  
50  
75  
100  
125  
Gain Error Drift (ppm/°C)  
Temperature (°C)  
Figure 11.  
Figure 12.  
Copyright © 2006–2011, Texas Instruments Incorporated  
7
XTR111  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C and VVSP = +24V, unless otherwise noted.  
TYPICAL NONLINEARITY  
TYPICAL NONLINEARITY  
(2pt Calibration at 4mA and 20mA)  
(2pt Calibration at 0.1mA and 25mA)  
0.0020  
0.0015  
0.0010  
0.0005  
0.000  
0.0020  
0.0015  
0.0010  
0.0005  
0.000  
-0.0005  
-0.0010  
-0.0015  
-0.0020  
-0.0005  
-0.0010  
-0.0015  
-0.0020  
4
8
12  
16  
20  
0
5
10  
IOUT (mA)  
15  
20  
25  
IOUT (mA)  
Figure 13.  
Figure 14.  
TYPICAL NONLINEARITY  
(2pt Calibration at 0.1mA and 36mA)  
INPUT VOLTAGE RANGE LIMIT TO THE  
POSITIVE SUPPLY vs TEMPERATURE  
0.010  
0.008  
3.0  
2.9  
2.8  
2.7  
2.6  
2.5  
2.4  
2.3  
2.2  
2.1  
2.0  
Seven Typical Units Shown  
VVSP = 12V  
0.006  
0.004  
0.002  
0.000  
-0.002  
-0.004  
-0.006  
-0.008  
-0.010  
0
5
10  
15  
20  
25  
30  
35  
40  
-75  
-50  
-25  
0
25  
50  
75  
100  
125  
IOUT (mA)  
Temperature (°C)  
Figure 15.  
Figure 16.  
OUTPUT SWING OF THE VOLTAGE ON IS PIN (VIS)  
vs OUTPUT CURRENT  
OUTPUT SWING OF THE VOLTAGE ON IS PIN (VIS)  
vs TEMPERATURE  
3.0  
1.8  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
20mA  
10mA  
4mA  
0
5
10  
15  
20  
25  
30  
35  
40  
-75  
-50  
-25  
0
25  
50  
75  
100  
125  
Output Current (mA)  
Temperature (°C)  
Figure 17.  
Figure 18.  
8
Copyright © 2006–2011, Texas Instruments Incorporated  
XTR111  
www.ti.com  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C and VVSP = +24V, unless otherwise noted.  
INPUT OFFSET VOLTAGE DISTRIBUTION  
INPUT OFFSET VOLTAGE DRIFT DISTRIBUTION  
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2  
0
0.2 0.4 0.6 0.8 1.0 1.2  
-5  
-4  
-3  
-2  
-1  
0
1
2
3
4
5
VOS (mV)  
VOS (mV/°C)  
Figure 19.  
Figure 20.  
INPUT OFFSET VOLTAGE vs SUPPLY VOLTAGE  
AMPLIFIER INPUT BIAS CURRENT vs TEMPERATURE  
100  
80  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
60  
40  
20  
0
-20  
-40  
-60  
-80  
-100  
0
10  
20  
30  
40  
50  
-75  
-50  
-25  
0
25  
50  
75  
100  
125  
Supply Voltage (V)  
Temperature (°C)  
Figure 21.  
Figure 22.  
OUTPUT CURRENT LIMIT DISTRIBUTION  
OUTPUT CURRENT LIMIT vs TEMPERATURE  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
-75  
-50  
-25  
0
25  
50  
75  
100  
125  
Current Limit (mA)  
Temperature (°C)  
Figure 23.  
Figure 24.  
Copyright © 2006–2011, Texas Instruments Incorporated  
9
XTR111  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C and VVSP = +24V, unless otherwise noted.  
REGULATOR VOLTAGE DISTRIBUTION  
REGULATOR VOLTAGE DRIFT DISTRIBUTION  
ILOAD = 0.6mA  
ILOAD = 0.6mA  
0
10  
20  
30  
40  
50  
60  
70  
80 More  
Regulator Voltage Drift (ppm/°C)  
Regulator Voltage (V)  
Figure 25.  
Figure 26.  
REGULATOR INPUT  
BIAS CURRENT DISTRIBUTION  
(Current into REGS Pin)  
REGULATOR INPUT BIAS  
CURRENT DRIFT DISTRIBUTION  
(Drift of Current into REGS Pin)  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
VREGS Input Bias Current Drift (nA/°C)  
VREGS Input Bias Current (mA)  
Figure 27.  
Figure 28.  
REGULATOR VOLTAGE vs TEMPERATURE  
ILOAD = 0.6mA  
REGULATOR VOLTAGE vs SUPPLY VOLTAGE  
3.05  
3.05  
3.04  
3.03  
3.02  
3.01  
3.00  
2.99  
2.98  
2.97  
2.96  
2.95  
ILOAD = 0.6mA  
3.04  
3.03  
3.02  
3.01  
3.00  
2.99  
2.98  
2.97  
2.96  
2.95  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
-75  
-50  
-25  
0
25  
50  
75  
100  
125  
Supply Voltage (V)  
Temperature (°C)  
Figure 29.  
Figure 30.  
10  
Copyright © 2006–2011, Texas Instruments Incorporated  
XTR111  
www.ti.com  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C and VVSP = +24V, unless otherwise noted.  
STEP RESPONSE: VFS = 4V, RSET = 2kΩ, RLD = 600Ω  
STEP RESPONSE: VFS = 2.5V, RSET = 1.25kΩ, RLD = 600Ω  
(Rising Edge Depends on CGATE at VG Pin)  
(Rising Edge Depends on CGATE at VG Pin)  
Photo taken with CGATE = 130pF  
Photo taken with CGATE = 130pF  
5V/div  
5V/div  
10V/div  
2V/div  
10ms/div  
10ms/div  
Figure 31.  
Figure 32.  
REGULATOR LOAD TRANSIENT  
(VREG Gain = 1V, VREGF = 3V, CL = 470nF,  
ILOAD = 3mA ± 0.3mA)  
REGULATOR LOAD TRANSIENT  
(VREG Gain = 4V, VREGF = 12V, CL = 470nF,  
ILOAD = 3mA ± 0.3mA)  
2V/div  
10mV/div  
10mV/div  
1V/div  
40ms/div  
40ms/div  
Figure 33.  
Figure 34.  
MAXIMUM REGULATOR CURRENT vs TEMPERATURE  
29  
27  
25  
23  
21  
19  
17  
15  
-75  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (°C)  
Figure 35.  
Copyright © 2006–2011, Texas Instruments Incorporated  
11  
XTR111  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
www.ti.com  
APPLICATION INFORMATION  
used during power-on, multiplexing and other  
conditions where the output should present no  
current. It has an internal pull-up that causes the  
XTR111 to come up in output disable mode unless  
the OD pin is tied low.  
The XTR111 is a voltage-controlled current source  
capable of delivering currents from 0mA to 36mA.  
The primary intent of the device is to source the  
commonly-used industrial current ranges of  
0mA–20mA or 4mA–20mA. The performance is  
specified for a supply voltage of up to 40V. The  
The onboard voltage regulator can be adjusted  
between 3V to 15V and delivers up to 5mA load  
current. It is intended to supply signal conditioning  
and sensor excitation in 3-wire sensor systems.  
Voltages above 3V can be set by a resistive divider.  
maximum  
supply  
voltage  
is  
44V.  
The  
voltage-to-current ratio is defined by an external  
resistor, RSET; therefore, the input voltage range can  
be freely set in accordance with the application  
requirement. The output current is cascoded by an  
external P-Channel MOSFET transistor for large  
voltage compliance extending below ground, and for  
easy power dissipation. This arrangement ensures  
excellent suppression of typical interference signals  
from the industrial environment because of the  
extremely high output impedance and wide voltage  
compliance.  
Figure 36 shows a basic connection for the XTR111.  
The input voltage VVIN reappears across RSET and  
controls 1/10 of the output current. The I-Mirror has a  
precise current gain of 10. This configuration leads to  
the transfer function:  
IOUT = 10 • (VVIN/RSET  
)
The output of the voltage regulator can be set over  
the range of 3V to 12V by selecting R1 and R2 using  
the following equation.  
An error detection circuit activates a logic output  
(error flag) in case the output current cannot correctly  
flow. It indicates a wire break, high load resistor, or  
loss of headroom for the current output to the positive  
supply. The output disable (OD) provided can be  
VREGF = 3V · (R1 + R2)/R2  
(1)  
VVSP = 24V Supply  
C1  
1
9
8
VSP  
OD  
EF  
(Pull Low for Normal Operation)  
REGF  
5
I-Mirror  
IS  
2
R1  
15W  
(1)  
5.6kW  
REGS  
S
Q2  
4
Q1  
G
VG  
3
D
3V  
10nF  
15W  
R2  
8.2kW  
5V  
Load  
0mA to 20mA  
4mA to 20mA  
6
VIN  
(
Load Ground)  
Signal  
Source  
(Sensor or  
DAC, for  
GND  
SET  
example)  
10  
7
VVIN  
(R )  
RSET  
IOUT = 10  
SET  
Figure 36. Basic Connection for 0mA to 20mA Related to 0V to 5V Signal Input. The Voltage Regulator is  
Set to 5V Output  
12  
Copyright © 2006–2011, Texas Instruments Incorporated  
 
XTR111  
www.ti.com  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
EXPLANATION OF PIN FUNCTIONS  
EF : The active low error flag (logic output) is  
intended for use with an external pull-up to logic-high  
for reliable operation when this output is used.  
However, it has a weak internal pull-up to 5V and can  
be left unconnected if not used.  
VIN: This input is a conventional, noninverting,  
high-impedance input of the internal operational  
amplifier (OPA). The internal circuitry is protected by  
clamp diodes to supplies. An additional clamp  
connected to approximately 18V protects internal  
circuitry. Place a small resistor in series with the input  
to limit the current into the protection if voltage can be  
present without the XTR111 being powered. Consider  
a resistor value equal to RSET for bias current  
cancellation.  
OD: This control input has a 4μA internal pull-up  
disabling the output. A pull-down or short to GND is  
required to activate the output. Controlling OD  
reduces output glitches during power-on and  
power-off. This logic input controls the output. If not  
used, connect to GND.  
SET: The total resistance connected between this pin  
and VIN reference sets the transconductance.  
Additional series resistance can degrade accuracy  
and drift. The voltage on this pin must not exceed  
14V because this pin is not protected to voltages  
above this level.  
The regulator is not affected by OD.  
EXTERNAL CURRENT LIMIT  
The XTR111 does not provide internal current limit for  
the case of when the external FET is forced to low  
impedance. The internal current source controls the  
current, but a high current from IS to GND forces an  
internal voltage clamp between VSP and IS to turn  
on. This results in a low resistance path and the  
current is only limited by the load impedance and the  
current capability of the external FET. A high current  
can destroy the IC. With the current loop interrupted  
(the load disconnected) the external MOSFET is fully  
turned on with large gate to source voltage stored in  
the gate capacitance. In the moment the loop is  
closed (the load connected) current flows into the  
load. But for the first few micro-seconds the MOSFET  
is still turned on and destructive current can flow,  
depending on the load impedance.  
IS: This output pin is connected to the transistor  
source of the external FET. The accuracy of the  
output current to IS is achieved by dynamic error  
correction in the current mirror. This pin should never  
be pulled more than 6.5V below the positive supply.  
An internal clamp is provided to protect the circuit;  
however, it must be externally current-limited to less  
than 50mA.  
VG: The gate drive for the external FET is protected  
against shorts to the supply and GND. The circuit is  
clamped so that it will not drive more than 18V below  
the positive supply. The external FET should be  
protected if its gate could be externally pulled beyond  
its ratings.  
An external current limit is recommended to protect  
the XTR111 from this condition. Figure 37a shows an  
example of a current limit circuit. The current should  
be limited to 50mA. The 15Ω resistor (R6) limits the  
current to approximately 37mA (33mA when hot). The  
PNP transistor should allow a peak current of several  
hundred mA. An example device is the (KST)2907.  
Power dissipation is not normally critical because the  
peak current duration is only a few micro-seconds.  
However, observe the leakage current through the  
transistor from IS to VG. The addition of this current  
limiting transistor and R6 still require time to  
discharge the gate of the external MOSFET. R7 and  
C3 are added for this reason, as well as to limit the  
steepness of external distortion pulses. Additional  
EMI and over-voltage protection may be required  
according to the application.  
REGF: The output of the regulator buffer can source  
up to 5mA current, but has very limited (less than  
50μA) sinking capability. The maximum short-circuit  
current is in the range of 15mA to 25mA, changing  
over temperature.  
REGS: This pin is the sense input of the voltage  
regulator. It is referenced to an internal 3V reference  
circuit. The input bias current can be up to 2μA. Avoid  
capacitive loading of REGS that may compromise the  
loop stability of the voltage regulator.  
VSP: The supply voltage of up to a maximum of 44V  
allows operation in harsh industrial environment and  
provides headroom for easy protection against  
over-voltage. Use a large enough bypass capacitor (>  
100nF) and eventually a damping inductor or a small  
resistor (5Ω) to decouple the XTR111 supply from the  
noise typically found on the 24V supplies.  
Figure 37b is a universal and basic current limiter  
circuit, using PNP or NPN transistors that can be  
connected in the source (IS to S) or in the drain  
output (in series with the current path). This circuit  
does not contribute to leakage currents. Consider  
adding an output filter like R7 and C3 in this limiter  
circuit.  
Copyright © 2006–2011, Texas Instruments Incorporated  
13  
XTR111  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
www.ti.com  
the OD pin high disables the gate driver and closes a  
switch connecting an internal 3kΩ resistor from the  
VSP pin to the VG pin. This resistor discharges the  
gate of the external FET and closes the channel; see  
Figure 38.  
IS  
IS  
R6  
15W  
R6  
15W  
Q2  
Q2  
Q1  
R7  
15W  
Q3  
VG  
R8  
5kW  
IOUT  
Table 1 lists some example devices in SO-compatible  
packages, but other devices can be used as well.  
Avoid external capacitance from IS. This capacitance  
could be compensated by adding additional  
capacitance from VG to IS; however, this  
compensation may slow the output down.  
C3  
10nF  
Q1  
VG  
IOUT  
a) Gate-Controlled Current Limit  
b) Serial Current Limit  
The drain-to-source breakdown voltage should be  
selected high enough for the application. Surge  
voltage protection might be required for negative  
over-voltages. For positive over-voltages, a clamp  
diode to the 24V supply is recommended, protecting  
the FET from reversing.  
Figure 37. External Current Limit Circuits  
EXTERNAL MOSFET  
The XTR111 delivers the precise output current to the  
IS pin. The voltage at this pin is normally 1.4V below  
VSP  
VVSP  
.
OD  
16V  
Switch  
This output requires an external transistor (QEXT) that  
forms a cascode for the current output. The transistor  
must be rated for the maximum possible voltage on  
VOUT and must dissipate the power generated by the  
current and the voltage across it.  
3kW  
VG  
GND  
The gate drive (VG) can drive from close to the  
positive supply rail to 16V below the positive supply  
voltage (VVSP). Most modern MOSFETs accept a  
maximum VGS of 20V. A protection clamp is only  
required if a large drain gate capacitance can pulse  
the gate beyond the rating of the MOSFET. Pulling  
Figure 38. Equivalent Circuit for Gate Drive and  
Disable Switch  
Table 1. P-Channel MOSFET (Examples)(1)  
MANUFACTURER  
Infineon  
PART NO.  
BSP170P  
2SJ326-Z  
NTF2955  
TP2510  
BREAKDOWN VGS  
PACKAGE  
SOT-223  
Spec.  
C-GATE  
328pF  
320pF  
492pF  
80pF  
–60V  
–60V  
–60V  
–100V  
NEC  
ON Semiconductor  
Supertex Inc.  
SOT-223  
TO-243AA  
(1) Data from published product data sheet; not ensured.  
14  
Copyright © 2006–2011, Texas Instruments Incorporated  
 
 
 
 
XTR111  
www.ti.com  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
DYNAMIC PERFORMANCE  
The output glitch magnitude depends on the  
mismatch of the internal current sources. It is  
approximately proportional to the output current level  
and scales directly with the load resistor value. It will  
differ slightly from part to part. The effects of filtering  
the output are shown in Figure 40 and Figure 41.  
The rise time of the output current is dominated by  
the gate capacitance of the external FET.  
The accuracy of the current mirror relies on the  
dynamic matching of multiple individual current  
sources. Settling to full resolution may require a  
complete cycle lasting around 100μs. Figure 39  
shows an example of the ripple generated from the  
individual current source values that average to the  
specified accuracy over the full cycle.  
External FET  
No Filter  
500W  
20ms/div  
Figure 39. Output Noise without Filter into 500Ω  
External FET  
Load Capacitor  
CF  
500W  
10nF  
20ms/div  
Figure 40. Output with 10nF Parallel to 500Ω  
Copyright © 2006–2011, Texas Instruments Incorporated  
15  
 
 
XTR111  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
www.ti.com  
External FET  
Typical Filter  
RF  
10kW  
NOTE: Scale has been changed  
from Figure 38 and Figure 39.  
CF  
10nF  
500W  
20ms/div  
Figure 41. Output with Additional Filter  
OUTPUT ERROR FLAG AND DISABLE INPUT  
INPUT VOLTAGE  
The XTR111 has additional internal circuitry to detect  
an error in the output current. In case the controlled  
output current cannot flow due to a wire break, high  
load resistance or the output voltage level  
approaching the positive supply, the error flag (EF),  
an open drain logic output, pulls low. When used, this  
digital output requires external pull-up to logic high  
(the internal pull-up current is 2μA).  
The input voltage range for a given output current  
span is set by RSET according to the transfer function.  
Select a precise and low drift resistor for best  
performance, because resistor drift directly converts  
into drift of the output current. Careful layout must  
also minimize any series resistance with RSET and the  
VIN reference point.  
The input voltage is referred to the grounding point of  
RSET. Therefore, this point should not be distorted  
from other currents. Assuming a 5V full-scale input  
signal for a 20mA output current, RSET is 2.5kΩ. A  
resistance uncertainty of just 2.5Ω already degrades  
the accuracy to below 0.1%.  
The output disable (OD) is a logic input with  
approximately 4μA of internal pull-up to 5V. The  
XTR111 comes up with the output disabled until the  
OD pin is pulled low. Logic high disables the output to  
zero output current. It can be used for calibration,  
power-on and power-off glitch reduction, and for  
output multiplexing with other outputs connected to  
the same terminal pin.  
The linear input voltage range extends from 0V to  
12V, or 2.3V below the positive supply voltage  
(whichever is smaller). The lowest rated supply  
voltage accomodates an input voltage range of up to  
5V. Potential clipping is not detected by an error  
signal; therefore, safe design guard banding is  
recommended.  
Power-on while the output is disabled (OD = high)  
cannot fully suppress output glitching. While the  
supply voltage passes through the range of 3V to 4V,  
internal circuits turn on. Additional capacitance  
between pins VG and IS can suppress the glitch. The  
smallest glitch energy appears with the OD pin left  
open; for practical use, however, this pin can be  
driven high through a 10kΩ resistor before the 24V  
supply is applied, if logic voltage is available earlier.  
Alternatively, an open drain driver can control this pin  
using the internal pull-up current. Pull-up to the  
internal regulator tends to increase the energy  
because of the delay of the regulator voltage  
increase, again depending on the supply voltage rise  
time for the first few volts.  
Do not drive the input negative (referred to GND)  
more than 300mV. Higher negative voltages turn on  
the internal protection diodes. Insert a resistor in  
series with the input if negative signals can occur  
eventually during power-on or -off or during other  
transient conditions. Select a resistor value limiting  
the possible current to 0.3mA. Higher currents are  
non-destructive (see Absolute Maximum Ratings), but  
they can produce output current glitches unless in  
disable mode.  
16  
Copyright © 2006–2011, Texas Instruments Incorporated  
XTR111  
www.ti.com  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
More protection against negative input signals is  
provided using a standard diode and a 2.2kΩ resistor,  
as shown in Figure 42.  
LEVEL SHIFT OF 0V INPUT AND  
TRANSCONDUCTANCE TRIM  
The XTR111 offers low offset voltage error at the  
input, which normally does not require cancellation. If  
the signal source cannot deliver 0V in a single-supply  
circuit, an additional resistor from the SET pin to a  
positive reference voltage or the regulator output  
(Figure 44) can shift the zero level for the input (VIN)  
to a positive voltage. Therefore, the signal source can  
drive this value within a positive voltage range. The  
2.2kW  
V-Signal  
VIN  
1N4148  
Figure 42. Enhanced Protection Against Negative  
Overload of VIN  
example shows  
a
+100mV (102.04mV) offset  
generated to the signal input. The larger this offset,  
however, the more influence of its drift and  
inaccuracy is seen in the output signal. The voltage at  
SET should not be larger than 12V for linear  
operation.  
4mA–20mA OUTPUT  
The XTR111 does not provide internal circuits to  
generate 4mA with 0V input signal. The most  
common way to shift the input signal is a two resistor  
network connected to a voltage reference and the  
signal source, as shown in Figure 43. This  
arrangement allows easy adjustment for over-and  
under-range. The example assumes a 5V reference  
(VREF) that equals the full-scale signal voltage and a  
signal span of 0V to 5V for 4mA to 20mA (IMIN to  
IMAX) output.  
Transconductance (the input voltage to output current  
ratio) is set by RSET. The desired resistor value may  
be found by choosing a combination of two resistors.  
XTR111  
I-V Amp  
VIN  
The voltage regulator output or a more precise  
reference can be used as VREF. Observe the potential  
drift added by the drift of the resistors and the voltage  
reference.  
SET  
120kW  
5V  
+100mV  
Offset  
Reference  
R1  
RSET  
Reference  
Voltage  
5V  
40kW  
2kW  
VIN  
1V to 5V  
R2  
Figure 44. Input Voltage Level Shift for 0mA  
Output Current  
10kW  
Input Voltage  
0V to 5V  
Figure 43. Resistive Divider for IMIN to IMAX Output  
(4mA to 20mA) with 0V to VFS Signal Source  
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17  
 
 
 
XTR111  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
www.ti.com  
VOLTAGE REGULATOR  
The voltage at REGF is limited by the supply voltage.  
If the supply voltage drops close to the set voltage,  
the driver output saturates and follows the supply with  
a voltage drop of less than 1V (depending on load  
current and temperature).  
The externally adjustable voltage regulator provides  
up to 5mA of current. It offers drive (REGF) and  
sense (REGS) to allow external setting of the output  
voltage as shown in Figure 45. The sense input  
(REGS) is referenced to 3.0V representing the lowest  
adjustable voltage level. An external resistor divider  
For good stability and transient response, use a load  
capacitance of 470nF or larger. The bias current into  
the sense input (REGS) is typically less than 1μA.  
This current should be considered when selecting  
high resistance values for the voltage setting because  
it lowers the voltage and produces additional  
temperature dependence.  
sets VREGF  
.
VREGF = VREGS · (R1 + R2)/R2  
Table 2 provides example values for the regulator  
adjustment resistors.  
The REGF output cannot sink current. In case of  
supply voltage loss, the output is protected against  
the discharge currents from load capacitors by  
internal protection diodes; the peak current should not  
exceed 25mA.  
Table 2. Examples for the Resistor Values Setting  
the Regulator Voltage  
(1)  
VREGF  
3V  
R1  
0
R2  
—
3.3V  
5V  
3.3kΩ  
5.6kΩ  
27kΩ  
33kΩ  
8.2kΩ  
8.6kΩ  
If the voltage regulator output is not used, connect  
REGF to REGS (the 3V mode) loaded with a 2.2nF  
capacitor. Alternatively, overdrive the loop pulling  
REGS high (see Figure 45d).  
12.4V  
(1) Values have been rounded.  
REGF  
REGF  
VREG  
3V  
R1  
470nF  
REGS  
REG  
5.6kW  
REGS  
470nF  
R2  
8.2kW  
3V  
3V  
(a)  
(b)  
VSP  
220W  
1kW  
REGF  
REGF  
R3  
1kW  
47kW  
REGS  
5V  
VREG  
Source  
R1  
470nF  
5.6kW  
REGS  
3V  
R2  
8.2kW  
3V  
(c)  
(d)  
Figure 45. Basic Connections of the Voltage Regulator  
18  
Copyright © 2006–2011, Texas Instruments Incorporated  
 
 
XTR111  
www.ti.com  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
APPLICATION BLOCK DIAGRAMS  
1
VSP  
OD  
9
8
2
Current  
Mirror  
EF  
IS  
5
4
REGF  
REGS  
5V  
C2  
R1  
470nF  
2kW  
15W  
(1)  
R2  
S
Q2  
3kW  
Q1  
G
VG  
3
D
3V  
10nF  
15W  
R3  
12-Bit Digital-to-Analog  
Converter  
2.5kW  
6
VIN  
Digital I/O  
DAC7551  
GND  
10  
SET  
7
0mA to 20mA  
RLOAD  
CLOAD  
RSET  
2.5kW  
Figure 46. Current Using 0V to 5V Input from a 12-Bit Digital-to-Analog Converter DAC7551  
1
VSP  
OD  
EF  
IS  
9
8
2
Current  
Mirror  
5
4
REGF  
REGS  
5V  
C2  
R1  
470nF  
2kW  
15W  
(1)  
REF3040  
4096mV  
R2  
S
Q2  
3kW  
Q1  
Voltage Reference  
VG  
3
G
D
3V  
10nF  
15W  
R3  
16-Bit Digital-to-Analog  
Converter  
2kW  
6
VIN  
Digital I/O  
DAC8551  
SET  
GND  
10  
0mA to 20mA output  
7
R4  
817.2kW  
Load  
CLOAD  
for 10mV to 4096mV input  
or a code of 160b to 65536b  
RLOAD  
RSET  
NOTE: Calculate RSET for R4 parallel to RSET  
.
2kW  
(1.995kW)  
Figure 47. Precision Current Output with Signal from 16-Bit DAC. Input Offset Shifted (R4) by 10mV for  
Zero Adjustment Range  
Copyright © 2006–2011, Texas Instruments Incorporated  
19  
 
 
XTR111  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
www.ti.com  
1
VSP  
OD  
EF  
IS  
9
8
2
Current  
Mirror  
5
4
REGF  
REGS  
15W  
(1)  
S
Q2  
Q1  
G
VG  
3
D
3V  
10nF  
15W  
6
VIN  
0V to 10V  
Signal Input  
GND  
10  
SET  
7
Load  
SW1  
CLOAD  
RLOAD  
RSET  
5kW  
Current (open) or  
Voltage (close) Output  
When output disabled and SW1 is closed,  
pin 7 may generate an error signal.  
Figure 48. 0V to 10V or 0mA to 20mA Output Selected by Jumper (SW1)  
(1)  
R4  
(a)  
(b)  
100W  
+24V  
Q2  
NPN  
Q2  
NPN  
R3  
R3  
1kW  
1kW  
REGF  
REGS  
REGF  
REGS  
R1  
10kW  
3V  
6V  
C2  
470nF  
C2  
R2  
470nF  
10kW  
NOTE: (1) Resistor R4 can be calculated to protect Q2  
from over current in fault conditions.  
Figure 49. Voltage Regulator Current Boost Using a Standard NPN Transistor  
20  
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XTR111  
www.ti.com  
SBOS375C –NOVEMBER 2006–REVISED JUNE 2011  
PACKAGE AND HEAT SINKING  
NOTE: All thermal models have an accuracy variation  
of 20%.  
The dominant portion of power dissipation for the  
current output is in the external FET.  
Component population, layout of traces, layers, and  
air flow strongly influence heat dissipation.  
Worst-case load conditions should be tested in the  
real environment to ensure proper thermal conditions.  
Minimize thermal stress for proper long-term  
operation with a junction temperature well below  
+125°C.  
The XTR111 only generates heat from the supply  
voltage with the quiescent current, the internal signal  
current that is 1/10 of the output current, and the  
current and internal voltage drop of the regulator.  
The exposed thermal pad on the bottom of the  
XTR111 package allows excellent heat dissipation of  
the device into the printed circuit board (PCB).  
LAYOUT GUIDELINES  
The leadframe die pad should be soldered to a  
thermal pad on the PCB. A mechanical data sheet  
showing an example layout is attached at the end of  
this data sheet. Refinements to this layout may be  
required based on assembly process requirements.  
Mechanical drawings located at the end of this data  
sheet list the physical dimensions for the package  
and pad. The five holes in the landing pattern are  
optional, and are intended for use with thermal vias  
that connect the leadframe die pad to the heatsink  
area on the PCB.  
THERMAL PAD  
The thermal pad must be connected to the same  
voltage potential as the device GND pin.  
Packages with an exposed thermal pad are  
specifically designed to provide excellent power  
dissipation, but board layout greatly influences overall  
heat dissipation. The thermal resistance from  
junction-to-ambient (TJA) is specified for the packages  
with the exposed thermal pad soldered to  
a
normalized PCB, as described in Technical Brief  
SLMA002, PowerPAD Thermally-Enhanced Package.  
See also EIA/JEDEC Specifications JESD51-0 to 7,  
QFN/SON PCB Attachment (SLUA271), and Quad  
Flatpack No-Lead Logic Packages (SCBA017).  
These documents are available for download at  
www.ti.com.  
Soldering the exposed pad significantly improves  
board-level reliability during temperature cycling, key  
push, package shear, and similar board-level tests.  
Even with applications that have low-power  
dissipation, the exposed pad must be soldered to the  
PCB to provide structural integrity and long-term  
reliability.  
space  
REVISION HISTORY  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision B (June, 2010) to Revision C  
Page  
•
Corrected wiring error in Figure 46 ..................................................................................................................................... 19  
Changes from Revision A (August, 2007) to Revision B  
Page  
•
Corrected errors in Figure 37 .............................................................................................................................................. 14  
Copyright © 2006–2011, Texas Instruments Incorporated  
21  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-May-2011  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
XTR111AIDGQR  
XTR111AIDGQRG4  
XTR111AIDGQT  
XTR111AIDGQTG4  
XTR111AIDRCR  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
MSOP-  
PowerPAD  
DGQ  
DGQ  
DGQ  
DGQ  
DRC  
DRC  
DRC  
DRC  
10  
10  
10  
10  
10  
10  
10  
10  
2500  
2500  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
MSOP-  
PowerPAD  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
MSOP-  
PowerPAD  
Green (RoHS  
& no Sb/Br)  
MSOP-  
PowerPAD  
250  
Green (RoHS  
& no Sb/Br)  
SON  
SON  
SON  
SON  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
XTR111AIDRCRG4  
XTR111AIDRCT  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
XTR111AIDRCTG4  
250  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-May-2011  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
2500  
250  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
XTR111AIDGQR  
XTR111AIDGQT  
MSOP-  
Power  
PAD  
DGQ  
DGQ  
10  
10  
330.0  
180.0  
12.4  
12.4  
5.3  
5.3  
3.3  
3.3  
1.3  
1.3  
8.0  
8.0  
12.0  
12.0  
Q1  
Q1  
MSOP-  
Power  
PAD  
XTR111AIDRCR  
XTR111AIDRCT  
SON  
SON  
DRC  
DRC  
10  
10  
3000  
250  
330.0  
180.0  
12.4  
12.4  
3.3  
3.3  
3.3  
3.3  
1.1  
1.1  
8.0  
8.0  
12.0  
12.0  
Q2  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
XTR111AIDGQR  
XTR111AIDGQT  
XTR111AIDRCR  
XTR111AIDRCT  
MSOP-PowerPAD  
MSOP-PowerPAD  
SON  
DGQ  
DGQ  
DRC  
DRC  
10  
10  
10  
10  
2500  
250  
370.0  
195.0  
367.0  
210.0  
355.0  
200.0  
367.0  
185.0  
55.0  
45.0  
35.0  
35.0  
3000  
250  
SON  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All  
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time  
of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information  
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or  
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the  
third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration  
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered  
documentation. Information of third parties may be subject to additional restrictions.  
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service  
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.  
TI is not responsible or liable for any such statements.  
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements  
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support  
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which  
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause  
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use  
of any TI components in safety-critical applications.  
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to  
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and  
requirements. Nonetheless, such components are subject to these terms.  
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties  
have executed a special agreement specifically governing such use.  
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in  
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components  
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and  
regulatory requirements in connection with such use.  
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which  
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such  
components to meet such requirements.  
Products  
Audio  
Applications  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Automotive and Transportation www.ti.com/automotive  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
www.ti.com/security  
Medical  
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Security  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Space, Avionics and Defense www.ti.com/space-avionics-defense  
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2012, Texas Instruments Incorporated  
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