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VXC1-1133

型号：

VXC1-1133

描述：

低噪声双通道100 MHz的时钟发生器[ Low-Noise Two-Channel 100-MHz Clock Generator ]

品牌：

TI[ TEXAS INSTRUMENTS ]

页数：

20 页

PDF大小：

620 K

下载PDF手册
CDCM9102  
www.ti.com  
SCAS922 –FEBRUARY 2012  
Low-Noise Two-Channel 100-MHz Clock Generator  
Check for Samples: CDCM9102  
1
FEATURES  
2
•
Integrated Low-Noise Clock Generator  
Including PLL, VCO, and Loop Filter  
•
Output Enable Pin Shuts Off Device and  
Outputs.  
•
Two Low-Noise 100-MHz Clocks (LVPECL,  
LVDS, or pair of LVCMOS)  
•
•
•
•
5-mm × 5-mm QFN-32 Package  
ESD Protection Exceeds 2 kV HBM, 500 V CDM  
Industrial Temperature Range (–40°C to 85°C)  
3.3-V Power Supply  
–
Support for HCSL Signaling Levels  
(AC-Coupled)  
–
–
–
Typical Period Jitter: 21 ps pk-pk  
Typical Random Jitter: 510 fs  
Output Type Set by Pins  
APPLICATIONS  
•
Reference Clock Generation for PCI Express  
Gen 1, Gen2, and Gen3  
•
•
Bonus Single-ended 25-MHz Output  
•
General-Purpose Clocking  
Integrated Crystal Oscillator Input Accepts  
25-MHz Crystal  
DESCRIPTION  
The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications  
standards such as PCI Express™. The device is easy to configure and use. The CDCM9102 provides two  
100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of  
LVCMOS buffers. HCSL signaling is supported using an ac-coupled network. The user configures the output  
buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided.  
Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for  
additional clock generators. All clocks generated are derived from a single external 25-MHz crystal.  
25 MHz  
Low  
Noise  
PCIe 100 MHz  
XO  
Clock  
25 MHz  
100 MHz  
PCIe  
Generator  
CDCM9102  
Figure 1. CDCM9102 Typical Application Example  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PCI Express is a trademark of PCI-SIG .  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2012, Texas Instruments Incorporated  
CDCM9102  
SCAS922 –FEBRUARY 2012  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
REGCAP1  
Vreg  
REGCAP2  
Vreg  
OE  
OSCOUT  
OUT1P  
OUT1N  
OUT0P  
OUT0N  
Low  
Noise  
Clock  
XIN  
XO  
Generator  
CDCM9102  
RESET  
OS1 OS0  
Figure 2. CDCM9102 Block Diagram  
white space  
white space  
white space  
TOP VIEW  
24 23 22 21 20 19 18 17  
25  
26  
27  
28  
16  
15  
14  
13  
NC  
NC  
NC  
NC  
VDD4  
NC  
GND  
NC  
CDCM9102  
29  
30  
31  
32  
12  
NC  
NC  
NC  
NC  
RESET  
OS0  
11  
GND  
(thermal pad)  
10  
OS1  
9
VDD3  
1
2
3
4
5
6
7
8
Figure 3. Pin Diagram  
2
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Copyright © 2012, Texas Instruments Incorporated  
Product Folder Link(s): CDCM9102  
CDCM9102  
www.ti.com  
SCAS922 –FEBRUARY 2012  
PIN FUNCTIONS  
NAME  
QFN32 PIN NO.  
DESCRIPTION  
POWER SUPPLIES  
GND  
Thermal pad, 14, 22  
Power supply ground and thermal relief  
Power Supply, OUT1 clock port  
VDD2  
1
VDD1  
4
Power Supply, OUT0 clock port  
VDD3  
9
Power supply, low-noise clock generator  
Power supply, low-noise clock generator  
Power supply, low-noise clock generator  
Power supply, crystal oscillator input  
VDD4  
16  
18  
20  
19  
17  
VDD5  
VDD6  
REGCAP1  
REGCAP2  
Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND  
Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND  
DEVICE CONFIGURATION AND CONTROL  
NC  
8, 13, 15, 24–32  
No connection permitted  
OE  
7
Output enable/shutdown control input (see Table 1)  
Output format select control inputs (see Table 2)  
OS1  
10  
11  
12  
OS0  
RESET  
Device reset input (active-low) (see Table 3)(1)  
Parallel resonant crystal input (25 MHz)  
CRYSTAL OSCILLATOR  
XIN  
21  
DEVICE OUTPUTS  
OUT0P  
6
5
Output 0 – positive terminal (100 MHz)  
Output 0 – negative terminal (100 MHz)  
Output 1 – positive terminal (100 MHz)  
Output 1 – negative terminal (100 MHz)  
Oscillator output port (25 MHz)  
OUT0N  
OUT1P  
3
OUT1N  
2
OSCOUT  
23  
(1) For proper device startup, it is recommended that a capacitor be installed from pin 12 to GND. See STARTUP TIME ESTIMATION  
section for more details.  
ORDERING INFORMATION  
TA  
PACKAGED DEVICES  
FEATURES  
CDCM9102RHBT  
32-pin QFN (RHB) package, small tape and reel  
32-pin QFN (RHB) package, tape and reel  
–40°C to 85°C  
CDCM9102RHBR  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
–0.5  
–0.5  
–0.5  
TYP  
MAX  
4.6  
UNIT  
V
VDDx  
VIN  
Supply voltage range(2)  
(3)  
Input voltage range  
VDDx + 0.5  
VDDx + 0.5  
20  
V
VOUT  
IIN  
IOUT  
Tstg  
Output voltage range(3)  
V
Input current  
mA  
mA  
°C  
Output current  
50  
Storage temperature range  
–65  
150  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating  
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) Supply voltages must be applied simultaneously.  
(3) The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed  
Copyright © 2012, Texas Instruments Incorporated  
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3
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CDCM9102  
SCAS922 –FEBRUARY 2012  
www.ti.com  
DISSIPATION RATINGS(1)(2)  
PARAMETER  
TEST CONDITIONS  
VALUE, 4 × 4 Vias on Pad  
UNIT  
ºC/W  
ºC/W  
θJA  
θJP  
Junction-to-ambient thermal resistance  
0 LFM  
35  
4
(3)  
Junction-to-thermal pad (top) thermal resistance  
(1) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).  
(2) Connected to GND with sixteen thermal vias (0.3 mm in diameter)  
(3) θJP (junction-to-pad) is used for the QFN package, because the primary heat flow is from the junction to the GND pad of the QFN  
package.  
ELECTRICAL CHARACTERISTICS  
RECOMMENDED OPERATING CONDITIONS  
MIN  
3
TYP  
MAX UNIT  
POWER SUPPLIES  
VDDX  
DC power-supply voltage  
3.3  
3.6  
85  
V
TEMPERATURE  
TA  
Ambient temperature  
–40  
°C  
DEVICE CURRENT CONSUMPTION  
TA = –40°C to 85°C, VDDx = 3.3 V, OE = 1, values represent cumulative current/power on all VDDx pins.  
EXTERNAL  
RESISTOR POWER  
(mW)  
CURRENT  
(mA)  
DEVICE POWER  
(mW)  
BLOCK  
CONDITION  
Entire device, core  
current  
85  
280  
LVPECL  
LVDS  
28  
42.4  
50  
Output Buffers  
20  
66  
LVCMOS  
V × ƒout × (CL + 20 × 10–12) × 103  
V2 × ƒout × (CL + 20 × 10–12) × 103  
DIGITAL INPUT CHARACTERISTICS – RESET, OE, OS1, OS0  
TA = –40°C to 85°C  
PARAMETER  
LVCMOS INPUTS  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
VIH  
VIL  
IIH  
Input high voltage  
Input low voltage  
Input high current  
Input low current  
Input capacitance  
Input pullup resistor  
0.6 VDD  
V
0.4 VDD  
V
VDD = 3.6 V, VIL = 0 V  
200  
–200  
10  
µA  
µA  
pF  
kΩ  
IIL  
VDD = 3 V, VIH = 3.6 V  
CIN  
RPU  
8
150  
4
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CDCM9102  
www.ti.com  
SCAS922 –FEBRUARY 2012  
CRYSTAL-OSCILLATOR INPUT-PORT CHARACTERISTICS (XIN)  
VDD = 3.3 V, TA = –40°C to 85°C  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
25  
8
MAX UNIT  
CRYSTAL CHARACTERISTICS (External 25 MHz Crystal)  
fXTAL  
Crystal input frequency  
Fundamental mode  
MHz  
ESR  
Effective series resistance of crystal  
On-chip load capacitance  
50  
10  
1
Ω
pF  
CIN  
XTALDL  
CSHUNT  
Maximum drive level - XTAL  
Maximum shunt capacitance  
0.1  
mW  
pF  
7
CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT MODE = LVPECL)  
VDD1, VDD2 = 3.3 V; TA = –40°C to 85°C  
PARAMETER  
Output high voltage  
Output low voltage  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
VOH  
VOL  
V
DD – 1.18  
V
DD – 0.73  
DD – 1.55  
V
V
DD – 2  
V
V
V
|VOD  
|
Differential output voltage  
Output rise/fall time  
Output duty cycle  
0.6  
1.23  
175  
55%  
20  
tR/tF  
20% to 80%  
ps  
ODC  
45%  
tSKEW  
Skew between outputs  
ps  
CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT MODE = LVDS)  
VDD1, VDD2 = 3.3V; TA = –40°C to 85°C  
PARAMETER  
Differential output voltage  
VOD magnitude change  
Common-mode voltage  
VOS magnitude change  
Output rise/fall time  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
|VOD  
|
0.247  
0.454  
50  
V
mV  
V
ΔVOD  
VOS  
1.125  
45%  
1.375  
50  
ΔVOS  
tR/tF  
mV  
ps  
20% to 80%  
255  
55%  
30  
ODC  
tSKEW  
Output duty cycle  
Skew between outputs  
ps  
CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT MODE = LVCMOS)  
VDD1, VDD2 = 3.3V; TA = –40°C to 85°C  
PARAMETER  
Output high voltage  
Output low voltage  
TEST CONDITIONS  
VCC = 3 V to 3.6 V, IOH = –100 µA  
VCC = 3 V to 3.6 V, IOH = 100 µA  
20% to 80%  
MIN  
TYP  
MAX UNIT  
VOH  
V
DD – 0.5  
V
VOL  
0.3  
V
tSLEW  
ODC  
tSKEW  
Output rise/fall slew rate  
Output duty cycle  
2.4  
V/ns  
45%  
55%  
50  
Skew between outputs  
ps  
OUTPUT JITTER PERFORMANCE  
fOUT = 100 MHz, VDD = 3.3 V, TA = 25°C, jitter integration bandwidth 10 kHz–20 MHz  
LVCMOS OUTPUT MODE  
LVPECL OUTPUT MODE  
LVDS OUTPUT MODE  
Random jitter Period jitter  
Random jitter Period jitter  
Random jitter  
(fs)  
Period jitter  
(ps pk-pk)  
(fs)  
(ps pk-pk)  
24.5  
(fs)  
(ps pk-pk)  
20.7  
507  
510  
533  
26.5  
Copyright © 2012, Texas Instruments Incorporated  
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CDCM9102  
SCAS922 –FEBRUARY 2012  
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TEST CONFIGURATIONS  
LVCMOS  
5 pF  
Figure 4. LVCMOS Output Test Load  
Phase Noise Analyzer  
RF  
50 W  
LVCMOS  
50 W  
Figure 5. LVCMOS AC Configuration for Device Test  
Oscilloscope  
CH2  
CH1  
50 W  
50 W  
LVPECL  
50 W (2)  
V
- 2 V  
DD  
Figure 6. LVPECL DC Configuration for Device Test  
Phase Noise Analyzer  
RF  
50 W  
LVPECL  
50 W  
150 W (2)  
Figure 7. LVPECL AC Configuration for Device Test  
6
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CDCM9102  
www.ti.com  
SCAS922 –FEBRUARY 2012  
Oscilloscope  
CH2  
CH1  
50 W  
50 W  
LVDS  
100 W  
Figure 8. LVDS DC Configuration for Device Test  
Phase Noise Analyzer  
RF  
50 W  
50 W  
50 W  
LVDS  
50 W  
Figure 9. LVDS AC Configuration for Device Test  
Copyright © 2012, Texas Instruments Incorporated  
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7
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CDCM9102  
SCAS922 –FEBRUARY 2012  
www.ti.com  
PERFORMANCE CHARACTERISTICS  
Figure 10. CDCM9102 Typical Phase Noise Performance (LVPECL Mode)  
FUNCTIONAL DESCRIPTION  
DEVICE CONFIGURATION  
Table 1. CDCM9102 Pin Control of Output Enable  
OE (Pin 7)  
MODE  
Power down  
Normal  
DEVICE CORE  
Power down  
Active  
OUTPUT  
Hi-Z  
0
1
Active  
Table 2. CDCM9102 Pin Configuration of Output Type  
CONTROL PINS  
OUTPUT MODE  
OS1 (Pin 10)  
OS0 (Pin 11)  
0
0
1
1
0
1
0
1
LVCMOS, OSCOUT = OFF  
LVDS, OSCOUT = OFF  
LVPECL, OSCOUT = OFF  
LVPECL, OSCOUT = ON  
8
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CDCM9102  
www.ti.com  
SCAS922 –FEBRUARY 2012  
Table 3. CDCM9102 Device Reset  
RESET (Pin 12)  
OPERATING MODE  
Device reset  
DEVICE OUTPUTS  
0
0 → 1  
1
Hi-Z  
Hi-Z  
Clock generator calibration  
Normal  
Active  
white space  
white space  
white space  
Copyright © 2012, Texas Instruments Incorporated  
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9
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CDCM9102  
SCAS922 –FEBRUARY 2012  
www.ti.com  
APPLICATION INFORMATION  
CRYSTAL INPUT (XIN) INTERFACE  
The CDCM9102 implements a Colpitts oscillator; therefore, one side of the crystal connects to the XIN pin and  
the other crystal terminal connects to ground. The device requires the use of a fundamental-mode crystal, and  
the oscillator operates in parallel resonance mode. The correct load capacitance is necessary to ensure that the  
circuit oscillates properly. The load capacitance comprises all capacitances in the oscillator feedback loop (the  
capacitances seen between the terminals of the crystal in the circuit). It is important to account for all sources of  
capacitance when calculating the correct value for the external discrete load capacitance shown in Figure 11.  
XIN  
(Pin 21)  
XO  
25 MHz  
C
C
C
C
IN  
L
STRAY  
PARASITIC  
Figure 11. Configuration of Circuit for CDCM9102 XIN Oscillator  
The CDCM9102 has been characterized with 10-pF parallel-resonant crystals. The input stage of the crystal  
oscillator in the CDCM9102 is designed to oscillate at the correct frequency for all parallel-resonant crystals with  
low-pull capability and rated with a load capacitance that is equal to the sum of the on-chip load capacitance at  
the XIN pin (CIN = 10 pF maximum), crystal stray capacitance, and board parasitic capacitance between the  
crystal and XIN pin. To minimize stray and parasitic capacitances, minimize the trace distance routed from the  
crystal to the XIN pin and avoid other active traces and/or active circuitry in the area of the crystal oscillator  
circuit. Table 4 lists crystal types that have been evaluated with the CDCM9102.  
Table 4. CDCM9102 Crystal Recommendations  
MANUFACTURER  
Vectron  
PART NUMBER  
VXC1-1133  
218-3  
Fox  
Saronix  
FP2650002  
A mismatch of the load capacitance results in a frequency error according to Equation 1:  
C
S
C
S
Δf  
=
-
f
2 C + C  
(
2 C + C  
O) ( La  
)
Lr  
O
(1)  
where:  
Δƒ is the frequency error required by the application.  
f is the fundamental frequency of the crystal.  
CS is the motional capacitance of the crystal. This is a parameter in the data sheet of the crystal.  
C0 is the shunt capacitance of the crystal. This is a parameter in the data sheet of the crystal.  
CLr is the rated load capacitance of the crystal. This is a parameter in the data sheet of the crystal.  
CLa is the actual load capacitance implemented on the PCB (CIN + stray capacitance + parasitic capacitance  
+ CL).  
The difference between the rated load capacitance (from the crystal datasheet) and the actual load capacitance  
(CLa = CIN + CL + CSTRAY + CPARASITIC) should be minimized. A crystal with a low pull-ability rating (low CS) is  
ideal.  
Design Example:  
Desired frequency tolerance Δf ≤ ±80 ppm  
Crystal Vendor Parameters:  
Intrinsic Frequency Tolerance = ±30 ppm  
10  
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SCAS922 –FEBRUARY 2012  
C0 = 7 pF (shunt capacitance)  
CS = 10 fF (motional capacitance)  
CLr = 12 pF (load capacitance)  
Substituting these parameters into Equation 1 yields a maximum value of CLa = 17 pF in order to achieve the  
(1)  
desired Δf (±50 ppm). Recall that CLa = CIN + CL + CSTRAY + CPARASITIC = 8 pF + (CL + CSTRAY + CPARASITIC  
)
.
Ideally, the load presented to this crystal should be 12 pF; therefore the sum of (CL + CSTRAY + CPARASITIC) must  
be less than 9 pF. Stray and parasitic capacitance must be controlled. This is because the Colpitts oscillator is  
particularly sensitive to capacitance in parallel with the crystal; therefore, good layout practice is essential. It is  
recommended that the designer extract the stray and parasitic capacitance from the printed circuit board design  
tool and adjust CL accordingly to achieve CLr = CLa. In common scenarios, the external load capacitor is often  
unnecessary; however, it is recommended that pads be implemented to accommodate an external load capacitor  
so that the ppm error can be minimized.  
STARTUP TIME ESTIMATION  
The CDCM9102 contains a low-noise clock generator that calibrates to an optimal operating point at device  
power up. In order to ensure proper device operation, the oscillator must be stable prior to the low-noise clock  
generator calibration procedure. Quartz-based oscillators can take up to 2 ms to stabilize; therefore it is  
recommended that the application ensure that the RESET pin is de-asserted at least 5 ms after the power supply  
has finished ramping. This can be accomplished by controlling the RESET pin directly, or by applying a 47-nF  
capacitor to ground on the RESET pin (this provides a delay because the RESET pin includes a 150-kΩ pullup  
resistor.  
The CDCM9102 startup time can be estimated based on parameters defined in Table 5 and graphically shown in  
Figure 12.  
Table 5. CDCM9102 Startup Time Dependencies  
Parameter  
Definition  
Description  
Formula / Method of Determination  
1
The reciprocal of the applied reference  
frequency in seconds  
tREF  
=
= 0.04 μs  
tREF  
Reference clock period  
fREF  
Power-supply rise time to low limit of  
power-on-reset trip point  
tpul  
Power-up time (low limit)  
Power-up time (high limit)  
Time required for power supply to ramp to 2.27 V  
Time required for power supply to ramp to 2.64 V  
Power supply rise time to high limit of  
power-on-reset trip point  
tpuh  
After POR releases, the Colpitts oscillator is  
enabled. This start-up time is required for the  
oscillator to generate the requisite signal  
levels for the delay block to be clocked by the  
reference input.  
500 μs best case and 800 μs worst case (for a crystal  
input)  
trsu  
Reference start-up time  
Delay time  
Internal delay time generated from the  
reference clock. This delay provides time for  
the reference oscillator to stabilize.  
tdelay  
tdelay = 16,384 × tREF = 655 µs  
VCO calibration time generated from the  
reference clock. This process selects the  
operating point for the VCO based on the PLL  
settings.  
tVCO_CAL  
VCO calibration time  
PLL lock time  
tVCO_CAL = 550 × tREF = 22 µs  
Time requried for PLL to lock within ±10 ppm  
of fREF  
tPLL_LOCK  
The PLL settles in 12.5 μs  
(1) CIN = 8 pF (typical), 10 pF (maximum). See the Crystal Oscillator Input Port Characteristics (XIN) table.  
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Reference  
Start-Up  
Power Up  
VCO Calibration  
PLL Lock  
Delay  
2.64  
2.27  
tpd  
tpuh  
Time - (S)  
trsu  
tdelay  
tVCO_CAL  
tPLL_LOCK  
Figure 12. CDCM9102 Start-Up Time Dependencies  
The CDCM9102 startup time limits, tMAX and tMIN, can now be calculated as follows  
tMAX = tpuh + trsu + tdelay + tVCO_CAL + tPLL_LOCK  
tMIN = tpul + trsu + tdelay + tVCO_CAL + tPLL_LOCK  
THERMAL MANAGEMENT  
To ensure optimal performance and reliability, good thermal design practices are important when using the  
CDCM9102. Die temperature should be limited to a maximum of 125°C. That is, as an estimate, TA (ambient  
temperature) plus device power consumption times θJA should not exceed 125°C.  
The device package has an exposed pad that provides the primary heat removal path as well as an electrical  
grounding to the printed circuit board (PCB). To maximize the removal of heat from the package, a thermal  
landing pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of  
the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.  
A recommended land and via pattern is shown in Figure 13.  
5.0 mm,min  
0.33 mm, typ  
2.1 mm, typ  
Figure 13. Recommended PCB Layout for CDCM9102  
POWER SUPPLY FILTERING  
PLL-based frequency synthesizers are very sensitive to noise on the power supply, which can dramatically  
increase the jitter of the PLL. This is especially true for analog-based PLLs. Thus, it is essential to reduce noise  
from the system power supply, especially when jitter/phase noise is very critical to applications. A PLL has  
attenuated jitter due to power supply noise at frequencies beyond the PLL bandwidth due to attenuation by the  
loop response.  
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass  
12  
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www.ti.com  
SCAS922 –FEBRUARY 2012  
capacitors provide the very low-impedance path for high-frequency noise and guard the power supply system  
against induced fluctuations. The bypass capacitors also provide a source of instantaneous current as required  
by the device output stages. Therefore, bypass capacitors must have low ESR. To properly use the bypass  
capacitors, they must be placed very close to the power supply pins and must be laid out with short loops to  
minimize inductance.  
Figure 14 shows a general recommendation for decoupling the power supply. The CDCXM9102 power supplies  
fall into one of two categories: analog supplies (VDD3, VDD4, and VDD5), and input/output supplies (VDD1,  
VDD2, and VDD6). Short the analog supplies together to form the analog supply node; likewise, short the  
input/output supplies together to form the I/O supply node. Isolate the analog node from the PCB power supply  
and I/O node by inserting a ferrite bead. This helps isolate the high-frequency switching noises generated by the  
clock drivers and I/O from the sensitive analog supply node. Choosing an appropriate ferrite bead with low dc  
resistance is important, as it is imperative to maintain a voltage at the power-supply pin of the CDCM9102 that is  
over the minimum voltage needed for its proper operation.  
PCB  
Supply  
Analog Node  
I/O Node  
Ferrite Bead  
0.1 µF  
(´3)  
10 µF  
10 µF  
0.1 µF  
(´3)  
Figure 14. CDCM9102 Power Supply Decoupling – Power Pin Bypass Concept  
OUTPUT TERMINATION  
The CDCM9102 is a 3.3-V clock driver which has the following options for the output type: LVPECL, LVDS, and  
LVCMOS.  
LVPECL TERMINATION  
The CDCM9102 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination is required to  
ensure correct operation of the device and to optimize signal integrity. The proper termination for LVPECL is  
50 Ω to (Vcc-2) V but this dc voltage is not readily available on a board. Thus a Thevenin’s equivalent circuit is  
worked out for the LVPECL termination in both direct-coupled (dc) and ac-coupled cases, as shown in Figure 15  
and Figure 16. It is recommended to place all resistive components close to either the driver end or the receiver  
end. If the supply voltages of the driver and receiver are different, ac coupling is required.  
V
DDOUT  
130 W (2)  
LVPECL  
LVPECL  
82 W (2)  
Figure 15. LVPECL Output Termination (DC-Coupled)  
Copyright © 2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
13  
Product Folder Link(s): CDCM9102  
 
 
CDCM9102  
SCAS922 –FEBRUARY 2012  
www.ti.com  
V
b
50 W (2)  
LVPECL  
150 W (2)  
Figure 16. LVPECL Output Termination (AC-Coupled)  
LVDS TERMINATION  
The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the  
receiver end. Either a direct-coupled (dc) termination or ac-coupled termination can be used for LVDS outputs,  
as shown in Figure 17 and Figure 18. It is recommended to place all resistive components close to either the  
driver end or the receiver end. If the supply voltages of the driver and receiver are different, ac coupling is  
required.  
100 W  
LVDS  
LVDS  
Figure 17. LVDS Output Termination (DC Coupled)  
100 W  
LVDS  
Figure 18. LVDS Output Termination (AC Coupling)  
LVCMOS TERMINATION  
Series termination is a common method to maintain the signal integrity for LVCMOS drivers, if connected to a  
receiver with a high-impedance input. For series termination, a series resistor, Rs, is placed close to the driver,  
as shown in Figure 19. The sum of the driver impedance and Rs should be close to the transmission-line  
impedance, which is usually 50 Ω. Because the LVCMOS driver in the CDCM9102 has an impedance of 30 Ω,  
Rs is recommended to be 22 Ω to maintain proper signal integrity.  
LVCMOS  
LVCMOS  
22 W  
Figure 19. LVCMOS Output Termination  
14  
Submit Documentation Feedback  
Copyright © 2012, Texas Instruments Incorporated  
Product Folder Link(s): CDCM9102  
 
 
 
CDCM9102  
www.ti.com  
SCAS922 –FEBRUARY 2012  
INTERFACING BETWEEN LVPECL and HCSL (PCI Express)  
Certain PCI Express applications require HCSL signaling. Because the common-mode voltage for LVPECL and  
HCSL are different, applications requiring HCSL signaling must use ac coupling as shown in Figure 20. The  
150-Ω resistors ensure proper biasing of the CDCM9102 LVPECL output stage. The 471-Ω and 56-Ω resistor  
network biases the HCSL receiver input stage.  
V
DDHCSL  
471 W (2)  
HCSL  
LVPECL  
56 W (2)  
150 W (2)  
Figure 20. Interfacing Between LVPECL and HCSL  
Copyright © 2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
15  
Product Folder Link(s): CDCM9102  
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
17-Mar-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
CDCM9102RHBR  
CDCM9102RHBT  
ACTIVE  
ACTIVE  
QFN  
QFN  
RHB  
RHB  
32  
32  
3000  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
CDCM9102RHBR  
CDCM9102RHBT  
QFN  
QFN  
RHB  
RHB  
32  
32  
3000  
250  
330.0  
180.0  
12.4  
12.4  
5.3  
5.3  
5.3  
5.3  
1.5  
1.5  
8.0  
8.0  
12.0  
12.0  
Q2  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CDCM9102RHBR  
CDCM9102RHBT  
QFN  
QFN  
RHB  
RHB  
32  
32  
3000  
250  
367.0  
210.0  
367.0  
185.0  
35.0  
35.0  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
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supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
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Copyright © 2012, Texas Instruments Incorporated  
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