VX-722 Dual Frequency HPLL VCXO
LVPECL Applicaꢀon Diagrams
+3.3V
+3.3V
10nF
1nF
10nF
1nF
VC
VC
+3.3V
1
2
3
6
5
4
1
2
3
6
5
4
130ꢀ
82ꢀ
130ꢀ
82ꢀ
10nF
10nF
10nF
10nF
FS
FS
240ꢀ
240ꢀ
Figure 6 - Single Resistor Terminaꢀon Scheme
Figure 7 - Pull Up Pull Down Terminaꢀon
Resistor values are typically 120 to 240 ohms for 3.3V operaꢀon and 82 to 120 ohms for 2.5V Resistor values are typically for 3.3V operaꢀon
operaꢀon. For 2.5V operaꢀon, the resistor to ground is 62 ohms and the resistor to supply is 240 ohms
There are numerous applicaꢀon notes on terminaꢀng and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 6,
and a pull-up/pull-down scheme as shown in Figure 7. An AC coupling capacitor is opꢀonal, depending on the applicaꢀon and the input logic requirements of
the next stage.
One of the most important consideraꢀons is terminaꢀng the Output and Complementary Outputs equally. An unused output should not be leꢂ un-
terminated, and if one of the two outputs is leꢂ open it will result in excessive jiꢁer on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jiꢁer related problems.
LVDS Applicaꢀon Diagrams
+3.3V
+3.3V
10nF
1nF
10nF
1nF
VC
VC
1
2
3
6
5
4
1
2
3
6
5
4
10nF
10nF
Receiver
100ꢀ
Receiver
FS
FS
100ꢀ
Figure 8 - LVDS to LVDS, internal 100Ω
Figure 9 - LVDS to LVDS, External 100Ω and AC block ing caps
Some LVDS structures have an internal 100 ohm resistor on the
input and do not need addiꢀonal components.
One of the most important consideraꢀons is terminaꢀng the Output and Complementary Outputs equally. An unused output should not be leꢂ un-
terminated, and if one of the two outputs is leꢂ open it will result in excessive jiꢁer on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jiꢁer related problems.
Page 4 of 9
Rev2: 14 November 2012
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