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5V41065PGGI

型号：

5V41065PGGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

12 页

PDF大小：

133 K

下载PDF手册
DATASHEET  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
IDT5V41065  
Recommended Applications  
Features/Benefits  
2 Output synthesizer for PCIe Gen1/2 and Ethernet  
• 16-pin TSSOP package; small board footprint  
• Spread-spectrum capable; reduces EMI  
General Description  
• Outputs can be terminated to LVDS; can drive a wider  
variety of devices  
The IDT5V41065 is a PCIe Gen2 compliant spread  
spectrum capable clock generator. The device has 2  
differential HCSL outputs and can be used in  
• 25 MHz, 125 MHz and 200 MHz output frequencies;  
supports Ethernet applications  
communication or embedded systems to subtantially  
reduce electro-magnetic interference (EMI). The spread  
amount and output frequency are selectable via select pins.  
The IDT5V41065 can also supply 25 MHz, 125 MHz and  
200 MHz outputs for applications such as Ethernet.  
• OE control pin; greater system power management  
• Spread% and frequency pin selection; no software  
required to configure device  
• Industrial temperature range available; supports  
demanding embedded applications  
• For PCIe Gen3 applications, see the 5V41235  
Output Features  
• 2 - 0.7V current mode differential HCSL output pairs  
Key Specifications  
• Cycle-to-cycle jitter < 100 ps  
• Output-to-output skew < 50 ps  
• PCIe Gen2 phase jitter < 3.0ps RMS  
Block Diagram  
VDD  
2
SS1:SS0  
S1:S0  
CLK0  
CLK0  
2
2
Control  
Logic  
Phase Lock Loop  
CLK1  
CLK1  
X1/ICLK  
Clock  
Buffer/  
Crystal  
Oscillator  
25 MHz  
crystal or clock  
X2  
2
GND  
Optional tuning crystal  
capacitors  
Rr(IREF)  
OE  
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
1
IDT5V41065 REV E 112111  
IDT5V41065  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Output Select Table 1 (MHz)  
Pin Assignment  
S1  
0
S0  
0
CLK(1:0), CLK(1:0)  
1
2
3
4
5
6
7
8
VDDXD  
CLK0  
16  
15  
14  
13  
12  
11  
10  
9
S0  
S1  
25M  
100M  
125M  
200M  
0
1
SS0  
X1/ICLK  
X2  
CLK0  
1
0
1
1
GNDODA  
VDDODA  
CLK1  
Spread Selection Table 2  
OE  
SS1 SS0  
Spread%  
No Spread  
Down -0.5  
Down -0.75  
No Spread  
GNDXD  
SS1  
CLK1  
IREF  
0
0
1
1
0
1
0
1
16-pin (173 mil) TSSOP  
Pin Descriptions  
Pin  
Number  
Pin  
Name  
Pin  
Type  
Pin Description  
1
2
3
4
5
6
S0  
S1  
Input Select pin 0. See Table1. Internal pull-up resistor.  
Input Select pin 1. See Table 1. Internal pull-up resistor.  
SS0  
X1/ICLK  
X2  
Input Spread Select pin 0. See Table 2. Internal pull-up resistor.  
Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.  
Output Crystal connection. Leave unconnected for clock input.  
OE  
Input Output enable. Tri-states outputs and device is not shut down. Internal  
pull-up resistor.  
7
8
9
GNDXD  
SS1  
Power Connect to ground.  
Input Spread Select pin 1. See Table 2. Internal pull-up resistor.  
IREF  
Output Precision resistor attached to this pin is connected to the internal current  
reference.  
10  
11  
12  
13  
14  
15  
16  
CLK1  
CLK1  
Output HCSL complementary clock output 1.  
Output HCSL true clock output 1.  
VDDODA  
GNDODA  
CLK0  
Power Connect to voltage supply +3.3 V for output driver and analog circuits  
Power Connect to ground.  
Output HCSL complementary clock output 0.  
Output HCSL true clock output 0.  
CLK0  
VDDXD  
Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.  
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
2
IDT5V41065 REV E 112111  
IDT5V41065  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Applications Information  
External Components  
A minimum number of external components are required for  
proper operation.  
Output Structures  
6*IREF  
IREF  
=2.3 mA  
Decoupling Capacitors  
Decoupling capacitors of 0.01 μF should be connected  
between each VDD pin and the ground plane, as close to  
the VDD pin as possible. Do not share ground vias between  
components. Route power from power source through the  
capacitor pad and then into ICS pin.  
Crystal  
See Output Termination  
Sections - Pages 3 ~ 5  
A 25 MHz fundamental mode parallel resonant crystal  
should be used. This crystal must have less than 300 ppm  
of error across temperature in order for the IDT5V41065 to  
meet PCI Express specifications.  
RR 475  
Ω
General PCB Layout Recommendations  
Crystal Capacitors  
For optimum device performance and lowest output phase  
noise, the following guidelines should be observed.  
Crystal capacitors are connected from pins X1 to ground  
and X2 to ground to optimize the accuracy of the output  
frequency.  
1. Each 0.01µF decoupling capacitor should be mounted on  
the component side of the board as close to the VDD pin as  
possible.  
C = Crystal’s load capacitance in pF  
L
Crystal Capacitors (pF) = (C - 8) * 2  
L
2. No vias should be used between decoupling capacitor  
and VDD pin.  
For example, for a crystal with a 16 pF load cap, each  
external crystal cap would be 16 pF. (16-8)*2=16.  
3. The PCB trace to VDD pin should be kept as short as  
possible, as should the PCB trace to the ground via.  
Distance of the ferrite bead and bulk decoupling from the  
device is less critical.  
Current Source (Iref) Reference Resistor - R  
R
If board target trace impedance (Z) is 50Ω, then R = 475Ω  
(1%), providing IREF of 2.32 mA. The output current (I ) is  
R
OH  
4. An optimum layout is one with all components on the  
same side of the board, minimizing vias through other signal  
layers (any ferrite beads and bulk decoupling capacitors can  
be mounted on the back). Other signal traces should be  
routed away from the IDT5V41065.This includes signal  
traces just underneath the device, or on layers adjacent to  
the ground plane layer used by the device.  
equal to 6*IREF.  
Output Termination  
The PCI-Express differential clock outputs of the  
IDT5V41065 are open source drivers and require an  
external series resistor and a resistor to ground. These  
resistor values and their allowable locations are shown in  
detail in the PCI-Express Layout Guidelines section.  
The IDT5V41065 can also be configured for LVDS  
compatible voltage levels. See the LVDS Compatible  
Layout Guidelines section.  
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
3
IDT5V41065 REV E 112111  
IDT5V41065  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Layout Guidelines  
SRC Reference Clock  
Common Recommendations for Differential Routing  
L1 length, route as non-coupled 50ohm trace  
L2 length, route as non-coupled 50ohm trace  
L3 length, route as non-coupled 50ohm trace  
Dimension or Value  
0.5 max  
0.2 max  
0.2 max  
33  
Unit Figure  
inch  
inch  
inch  
ohm  
ohm  
1
1
1
1
1
Rs  
Rt  
49.9  
Down Device Differential Routing  
L4 length, route as coupled microstrip 100ohm differential trace  
L4 length, route as coupled stripline 100ohm differential trace  
2 min to 16 max  
1.8 min to 14.4 max  
inch  
inch  
1
1
Differential Routing to PCI Express Connector  
L4 length, route as coupled microstrip 100ohm differential trace  
L4 length, route as coupled stripline 100ohm differential trace  
0.25 to 14 max  
0.225 min to 12.6 max  
inch  
inch  
2
2
Figure 1: Down Device Routing  
L2  
L1  
Rs  
Rs  
L4  
L4'  
L2'  
L1'  
Rt  
Rt  
HCSL Output Buffer  
PCI Express  
Down Device  
REF_CLK Input  
L3' L3  
Figure 2: PCI Express Connector Routing  
L2  
L1  
Rs  
L4  
L4'  
L2'  
L1'  
Rs  
Rt  
Rt  
HCSL Output Buffer  
PCI Express  
Add-in Board  
REF_CLK Input  
L3' L3  
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
4
IDT5V41065 REV E 112111  
IDT5V41065  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Alternative Termination for LVDS and other Common Differential Signals (figure 3)  
Vdiff  
0.45v  
0.58  
0.80  
0.60  
Vp-p  
0.22v  
0.28  
0.40  
0.3  
Vcm  
1.08  
0.6  
0.6  
1.2  
R1  
33  
33  
33  
33  
R2  
R3  
R4  
Note  
150  
78.7  
78.7  
174  
100  
137  
none  
140  
100  
100  
100  
100  
ICS874003i-02 input compatible  
Standard LVDS  
R1a = R1b = R1  
R2a = R2b = R2  
Figure 3  
L2  
L1  
R3  
R4  
R1a  
R1b  
L4  
L4'  
L2'  
L1'  
R2a  
R2b  
HCSL Output Buffer  
Down Device  
REF_CLK Input  
L3'  
L3  
Cable Connected AC Coupled Application (figure 4)  
Component  
Value  
Note  
R5a, R5b  
R6a, R6b  
Cc  
8.2K 5%  
1K 5%  
0.1 µF  
Vcm  
0.350 volts  
Figure 4  
3.3 Volts  
R5a  
R5b  
Cc  
L4  
L4'  
Cc  
R6a  
R6b  
PCIe Device  
REF_CLK Input  
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
5
IDT5V41065 REV E 112111  
IDT5V41065  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Typical PCI-Express (HCSL) Waveform  
700 mV  
0
500 ps  
500 ps  
tOR  
tOF  
0.525 V  
0.175 V  
0.525 V  
0.175 V  
Typical LVDS Waveform  
1325 mV  
1000 mV  
500 ps  
500 ps  
tOR  
tOF  
1250 mV  
1150 mV  
1250 mV  
1150 mV  
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
6
IDT5V41065 REV E 112111  
IDT5V41065  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the IDT5V41065. These ratings are stress  
ratings only. Functional operation of the device at these or any other conditions above those indicated in the  
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for  
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended  
operating temperature range.  
Item  
Supply Voltage, VDDXD, VDDODA  
All Inputs and Outputs  
Rating  
4.6 V  
-0.5 V to VDD+0.5 V  
0 to +70° C  
Ambient Operating Temperature (commercial)  
Ambient Operating Temperature (industrial)  
Storage Temperature  
-40 to +85° C  
-65 to +150° C  
125°C  
Junction Temperature  
Soldering Temperature  
260°C  
ESD Protection (Input)  
2000 V min. (HBM)  
DC Electrical Characteristics  
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85° C  
Parameter  
Symbol  
Conditions  
Min.  
3.135  
2.2  
Typ.  
3.3  
Max.  
3.465  
Units  
V
Supply Voltage  
V
1
Input High Voltage  
V
S0, S1, OE, ICLK, SS0, SS1  
S0, S1, OE, ICLK, SS0, SS1  
0 < Vin < VDD  
VDD +0.3  
V
IH  
1
Input Low Voltage  
Input Leakage Current  
V
I
VSS-0.3  
-5  
0.8  
5
V
IL  
2
μA  
mA  
mA  
pF  
pF  
pF  
nH  
kΩ  
kΩ  
IL  
Operating Supply Current  
@100 MHz  
I
R =33Ω, R =50Ω, C =2 pF  
63  
42  
85  
50  
7
DD  
S
P
L
I
OE =Low  
DDOE  
Input Capacitance  
Output Capacitance  
X1, X2 Capacitance  
Pin Inductance  
C
Input pin capacitance  
Output pin capacitance  
IN  
C
6
OUT  
C
5
INX  
L
5
PIN  
Output Impedance  
Pull-up Resistor  
Z
CLK outputs  
3.0  
O
R
S0, S1, OE, SS0, SS1  
100  
PU  
1. Single edge is monotonic when transitioning through region.  
2. Inputs with pull-ups/-downs are not included.  
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
7
IDT5V41065 REV E 112111  
IDT5V41065  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1  
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85° C  
Parameter  
Input Frequency  
Symbol  
Conditions  
Min.  
Typ.  
25  
Max.  
Units  
MHz  
MHz  
MHz  
mV  
mV  
mV  
mV  
ps  
Output Frequency  
HCSL termination  
25  
25  
200  
100  
850  
LVDS termination  
HCSL  
1,2  
Output High Voltage  
V
OH  
1,2  
Output Low Voltage  
V
HCSL  
-150  
250  
OL  
1,2  
Crossing Point Voltage  
Crossing Point Voltage  
Absolute  
550  
140  
100  
1,2,4  
Variation over all edges  
1,3  
Jitter, Cycle-to-Cycle  
Frequency Synthesis Error  
Modulation Frequency  
All outputs  
0
ppm  
kHz  
ps  
Spread spectrum  
30  
32.9  
33  
700  
700  
125  
50  
1,2  
Rise Time  
t
From 0.175 V to 0.525 V  
From 0.525 V to 0.175 V  
175  
175  
OR  
1,2  
Fall Time  
t
ps  
OF  
1,2  
Rise/Fall Time Variation  
ps  
Output to Output Skew  
ps  
1,3  
Duty Cycle  
45  
7
55  
%
5
Output Enable Time  
All outputs  
50  
50  
100  
100  
1.8  
30  
ns  
5
Output Disable Time  
All outputs  
ns  
Stabilization Time  
t
From power-up VDD=3.3 V  
ms  
STABLE  
Spread Spectrum Transition  
Time  
t
Stabilization time after spread  
spectrum changes  
ms  
SPREAD  
Note 1: Test setup is R =33Ω, R =50Ω with C =2 pF, Rr = 475Ω (1%).  
S
P
L
Note 2: Measurement taken from a single-ended waveform.  
Note 3: Measurement taken from a differential waveform.  
Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.  
Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.  
Electrical Characteristics - Differential Phase Jitter  
Parameter  
Symbol  
Conditions  
Min Typ Max  
Units  
ps (p-p)  
Notes  
1,2,3  
1,2,3  
1,2,3  
t
PCIe Gen1  
32  
0.8  
2.3  
86  
3
jphasePLL  
Jitter, Phase  
t
PCIe Gen2, 10 kHz < f < 1.5 MHz  
ps (RMS)  
ps (RMS)  
jphaseLO  
t
PCIe Gen2, 1.5 MHz < f < Nyquist (50 MHz)  
3.1  
jphaseHIGH  
Note 1. Guaranteed by design and characterization, not 100% tested in production.  
Note 2. See http://www.pcisig.com for complete specs.  
Note 3: Applies to 100MHz, spread off and 0.5% down spread only.  
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
8
IDT5V41065 REV E 112111  
IDT5V41065  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Thermal Characteristics  
Parameter  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
Thermal Resistance Junction to  
Ambient  
θ
Still air  
1 m/s air flow  
3 m/s air flow  
78  
70  
68  
37  
° C/W  
° C/W  
° C/W  
° C/W  
JA  
θ
θ
JA  
JA  
Thermal Resistance Junction to Case  
θ
JC  
Marking Diagram (5V41065PGG)  
Marking Diagram (5V41065PGGI)  
16  
9
16  
9
IDT5V410  
65PGGI  
#YYWW$  
IDT5V410  
65PGG  
#YYWW$  
1
8
1
8
Notes:  
1. Line 1 and 2: IDT part number.  
2. Line 3: # – Die revision; YYWW – Date code; $ – Assembly location.  
3. “G” after the two-letter package code designates RoHS compliant package.  
4. “I” at the end of part number indicates industrial temperature range.  
5. Bottom marking: country of origin if not USA.  
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
9
IDT5V41065 REV E 112111  
IDT5V41065  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)  
Package dimensions are kept current with JEDEC Publication No. 95  
Millimeters  
Inches*  
16  
Symbol  
Min  
--  
Max  
1.20  
0.15  
1.05  
0.30  
0.20  
5.1  
Min  
--  
0.002  
0.032  
0.007  
Max  
0.047  
0.006  
0.041  
0.012  
A
A1  
A2  
b
0.05  
0.80  
0.19  
0.09  
4.90  
E1  
E
INDEX  
AREA  
C
D
E
0.0035 0.008  
0.193 0.201  
0.252 BASIC  
0.169 0.177  
0.0256 Basic  
6.40 BASIC  
1
2
E1  
e
4.30  
0.65 Basic  
4.50  
D
L
0.45  
0.75  
0.018  
0.030  
a
0°  
8°  
0°  
8°  
aaa  
--  
0.10  
--  
0.004  
A
A2  
A1  
c
- C -  
e
SEATING  
PLANE  
b
L
aaa C  
Ordering Information  
Part / Order Number  
Marking  
See Page 8  
Shipping Packaging  
Tubes  
Package  
Temperature  
0 to +70° C  
0 to +70° C  
-40 to +85° C  
-40 to +85° C  
5V41065PGG  
5V41065PGG8  
5V41065PGGI  
5V41065PGGI8  
16-pin TSSOP  
16-pin TSSOP  
16-pin TSSOP  
16-pin TSSOP  
Tape and Reel  
Tubes  
See Page 8  
Tape and Reel  
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
10  
IDT5V41065 REV E 112111  
IDT5V41065  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Revision History  
Rev. Originator  
Date  
Description of Change  
A
07/15/08 New datasheet; Preliminary initial release.  
B
C
D
RDW  
RDW  
RDW  
01/13/10 Added Gen2 to title; update Electrical tables per char; added Differential Phase Jitter table.  
04/27/10 Updated electrical tables per char; VDD is now 3.3 5%; released to final.  
07/19/10 1. Updated title and general decription  
2. Updated cycle-to-cycle jitter spec from 125 to 100 ps.  
E
RDW  
11/21/11 1. Changed title to “2 Output PCIe GEN1/2 Synthesizer”  
2. Added note to Features section: “For PCIe Gen3 applications, see 5V41235”  
3. Updated Differential Phase Jitter table.  
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
11  
IDT5V41065 REV E 112111  
IDT5V41065  
2 OUTPUT PCIE GEN1/2 SYNTHESIZER  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
800-345-7015  
408-284-8200  
Fax: 408-284-2775  
For Tech Support  
www.idt.com/go/clockhelp  
Corporate Headquarters  
Integrated Device Technology, Inc.  
www.idt.com  
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated  
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or  
registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
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 		5V40501DVGI8 LOCO ™ PLL时钟乘法器[ LOCO™ PLL CLOCK MULTIPLIER ] 9 页

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 		5V40512DCGI8 [ Clock Generator, 133.3MHz, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8 ] 9 页

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