请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

PZ5032-CS7A44

型号：

PZ5032-CS7A44

描述：

IC- SM -CMOS PLD\n[ IC-SM-CMOS PLD ]

品牌：

ETC[ ETC ]

页数：

16 页

PDF大小：

268 K

下载PDF手册
INTEGRATED CIRCUITS  
Xilinx has acquired the entire Philips CoolRunner  
Low Power CPLD Product Family. For more  
technical or sales information, please see:  
www.xilinx.com  
XCR5032C  
32 macrocell CPLD with enhanced clocking  
Product specification  
1998 Jul 23  
Supersedes data of 1998 Jun 24  
IC27 Data Handbook  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
XCR5032C  
Xilinx has acquired the entire Philips CoolRunner Low Power CPLD Product Family. For  
more technical or sales information, please see: www.xilinx.com  
FEATURES  
DESCRIPTION  
The PZ5032C CPLD (Complex Programmable Logic Device) is a  
member of the Fast Zero Power (FZP ) family of CPLDs from  
Philips Semiconductors. These devices combine high speed and  
zero power in a 32 macrocell CPLD. With the FZP design  
technique, the PZ5032C offers true pin-to-pin speeds of 6ns, while  
simultaneously delivering power that is less than 75µA at standby  
without the need for ‘turbo bits’ or other power down schemes. By  
replacing conventional sense amplifier methods for implementing  
product terms (a technique that has been used in PLDs since the  
bipolar era) with a cascaded chain of pure CMOS gates, the  
dynamic power is also substantially lower than any competing  
CPLD—70% lower at 50MHz. These devices are the first  
TotalCMOS PLDs, as they use both a CMOS process technology  
and the patented full CMOS FZP design technique. For 3V  
applications, Philips also offers the high speed PZ3032C CPLD that  
offers pin-to-pin speeds of 8ns.  
• Industry’s first TotalCMOS PLD – both CMOS design and  
process technologies  
• Fast Zero Power (FZP ) design technique provides ultra-low  
power and very high speed  
• High speed pin-to-pin delays of 6ns  
• Ultra-low static power of less than 75µA  
• Dynamic power that is 70% lower at 50MHz than competing  
devices  
• 100% routable with 100% utilization while all pins and all  
macrocells are fixed  
• Deterministic timing model that is extremely simple to use  
• Up to 6 clocks with programmable polarity at every macrocell  
• 5 Volt, In-System Programmable (ISP) using a JTAG interface  
– On-chip supervoltage generation  
The Philips FZP CPLDs introduce the new patent-pending XPLA  
(extended Programmable Logic Array) architecture. The XPLA  
architecture combines the best features of both PLA and PAL type  
structures to deliver high speed and flexible logic allocation that  
results in superior ability to make design changes with fixed pinouts.  
The XPLA structure in each logic block provides a fast 6ns PAL  
path with 5 dedicated product terms per output. This PAL path is  
joined by an additional PLA structure that deploys a pool of 32  
product terms to a fully programmable OR array that can allocate  
the PLA product terms to any output in the logic block. This  
combination allows logic to be allocated efficiently throughout the  
logic block and supports as many as 37 product terms on an output.  
The speed with which logic is allocated from the PLA array to an  
output is only 2ns, regardless of the number of PLA product terms  
– ISP commands include: Enable, Erase, Program, Verify  
– Supported by multiple ISP programming platforms  
– 4 pin JTAG interface (TCK, TMS, TDI, TDO)  
– JTAG commands include: Bypass, Idcode  
• Support for complex asynchronous clocking  
• Innovative XPLA architecture combines high speed with  
extreme flexibility  
• 1000 erase/program cycles guaranteed  
• 20 years data retention guaranteed  
• Logic expandable to 37 product terms  
• PCI compliant  
used, which results in worst case t ’s of only 8ns from any pin to  
PD  
2
• Advanced 0.5µ E CMOS process  
any other pin. In addition, logic that is common to multiple outputs  
can be placed on a single PLA product term and shared across  
multiple outputs via the OR array, effectively increasing design  
density.  
• Security bit prevents unauthorized access  
• Design entry and verification using industry standard and Philips  
CAE tools  
The PZ5032C CPLDs are supported by industry standard CAE tools  
(Cadence, Exemplar Logic, Minc, Mentor, Synopsys, Synario,  
Viewlogic, OrCAD), using text (Abel, VHDL, Verilog) and/or  
schematic entry. Design verification uses industry standard  
simulators for functional and timing simulation. Development is  
supported on personal computer, Sparc, and HP platforms. Device  
fitting uses either Minc or Philips Semiconductors-developed tools.  
• Reprogrammable using industry standard device programmers  
• Innovative Control Term structure provides either sum terms or  
product terms in each logic block for:  
– Programmable 3-State buffer  
– Asynchronous macrocell register preset/reset  
– Up to 2 asynchronous clocks  
• Programmable global 3-State pin facilitates ‘bed of nails’ testing  
The PZ5032C CPLD is reprogrammable using industry standard  
device programmers from vendors such as Data I/O, BP  
Microsystems, SMS, and others. The PZ5032C also includes an  
industry-standard, IEEE 1149.1, JTAG interface through which  
In-System Programming (ISP) and reprogramming of the device are  
supported.  
without using logic resources  
• Available in both PLCC and TQFP packages  
Table 1. PZ5032C Features  
PZ5032C  
Usable gates  
1000  
Maximum inputs  
Maximum I/Os  
36  
32  
Number of macrocells  
I/O macrocells  
32  
32  
Buried macrocells  
Propagation delay (ns)  
Packages  
0
6.0  
44-pin PLCC, 44-pin TQFP  
PAL is a registered trademark of Advanced Micro Devices, Inc.  
2
1998 Jul 23  
853–2080 19774  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
ORDERING INFORMATION  
ORDER CODE  
PZ5032CS6A44  
PZ5032CS7A44  
PZ5032CS10A44  
PZ5032CS6BC  
PZ5032CS7BC  
PZ5032CS10BC  
DESCRIPTION  
DESCRIPTION  
DRAWING NUMBER  
SOT187-2  
44-pin PLCC, 6ns t  
Commercial temp range, 5 volt power supply, ± 5%  
Commercial temp range, 5 volt power supply, ± 5%  
Commercial temp range, 5 volt power supply, ± 5%  
Commercial temp range, 5 volt power supply, ± 5%  
Commercial temp range, 5 volt power supply, ± 5%  
Commercial temp range, 5 volt power supply, ± 5%  
PD  
44-pin PLCC, 7.5ns t  
SOT187-2  
PD  
PD  
44-pin PLCC, 10ns t  
44-pin TQFP, 6ns t  
SOT187-2  
,
SOT376-1  
PD  
44-pin TQFP, 7.5ns t  
SOT376-1  
PD  
PD  
44-pin TQFP, 10ns t  
SOT376-1  
PRODUCT terms, and are used to control the preset/reset and  
output enables of the 16 macrocells’ flip-flops. In addition, two of the  
control terms can be used as clock signals (see Macrocell  
Architecture section for details). The PAL array consists of a  
programmable AND array with a fixed OR array, while the PLA array  
consists of a programmable AND array with a programmable OR  
array. The PAL array provides a high speed path through the array,  
while the PLA array provides increased product term density.  
XPLA ARCHITECTURE  
Figure 1 shows a high level block diagram of a 32 macrocell device  
implementing the XPLA architecture. The XPLA architecture  
consists of logic blocks that are interconnected by a Zero-power  
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each  
logic block is essentially a 36V16 device with 36 inputs from the ZIA  
and 16 macrocells. Each logic block also provides 32 ZIA feedback  
paths from the macrocells and I/O pins.  
Each macrocell has 5 dedicated product terms from the PAL array.  
From this point of view, this architecture looks like many other CPLD  
architectures. What makes the CoolRunner family unique is what  
is inside each logic block and the design technique used to  
implement these logic blocks. The contents of the logic block will be  
described next.  
The pin-to-pin t of the PZ5032C device through the PAL array is  
PD  
6ns. This performance is equivalent to the fastest 5 volt CPLD  
available today. If a macrocell needs more than 5 product terms, it  
simply gets the additional product terms from the PLA array. The  
PLA array consists of 32 product terms, which are available for use  
by all 16 macrocells. The additional propagation delay incurred by a  
macrocell using 1 or all 32 PLA product terms is just 2ns. So the  
Logic Block Architecture  
Figure 2 illustrates the logic block architecture. Each logic block  
contains control terms, a PAL array, a PLA array, and 16 macrocells.  
The 6 control terms can individually be configured as either SUM or  
total pin-to-pin t for the PZ5032C using 6 to 37 product terms is  
PD  
8ns (6ns for the PAL + 2ns for the PLA).  
MC0  
MC0  
MC1  
MC1  
36  
36  
LOGIC  
BLOCK  
LOGIC  
BLOCK  
I/O  
I/O  
ZIA  
MC15  
MC15  
16  
16  
16  
16  
SP00550  
Figure 1. Philips XPLA CPLD Architecture  
3
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
36 ZIA INPUTS  
6
CONTROL  
5
PAL  
ARRAY  
PLA  
ARRAY  
(32)  
SP00435A  
Figure 2. Philips XPLA Logic Block Architecture  
4
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
macrocell’s flip-flop. Note that the Power-on Reset leaves all  
Macrocell Architecture  
macrocells in the “zero” state when power is properly applied, and  
that the Preset/Reset feature for each macrocell can also be  
disabled. Control terms CT2 and CT3 can be used as a clock signal  
to the flip-flops of the macrocells, and as the Output Enable of the  
macrocell’s output buffer. Control terms CT4 and CT5 can be used  
to control the Output Enable of the macrocell’s output buffer. Having  
four dedicated Output Enable control terms ensures that the  
CoolRunner devices are PCI compliant. The output buffers can  
also be always enabled or always disabled. All CoolRunner  
devices also provide a Global Tri-State (GTS) pin, which, when  
enabled and pulled Low, will 3-State all the outputs of the device.  
This pin is provided to support “In-Circuit Testing” or “Bed-of-Nails”  
testing.  
Figure 3 shows the architecture of the macrocell used in the  
CoolRunner PZ5032C. The macrocell can be configured as either  
a D or T type flip-flop or a combinatorial logic function. A D-type  
flip-flop is generally more useful for implementing state machines  
and data buffering while a T-type flip-flop is generally more useful in  
implementing counters. Each of these flip-flops can be clocked from  
any one of four sources. Two of the clock sources (CLK0 and CLK1)  
are connected to low-skew, device-wide clock networks designed to  
preserve the integrity of the clock signal by reducing skew between  
rising and falling edges. Clock 0 (CLK0) is designated as a  
“synchronous” clock and must be driven by an external source.  
Clock 1 (CLK1) can be used as a “synchronous” clock that is driven  
by an external source, or as an “asynchronous” clock that is driven  
by a macrocell equation. Both CLK0 and CLK1 can clock the  
macrocell flip-flops on either the rising edge or the falling edge of the  
clock signal. The other clock sources are two of the six control terms  
(CT2 and CT3) provided in each logic block. These clocks can be  
individually configured as either a PRODUCT term or SUM term  
equation created from the 36 signals available inside the logic block.  
The timing for asynchronous and control term clocks is different in  
that the Tco time is extended by the amount of time that it takes for  
the signal to propagate through the array and reach the clock  
network, and the Tsu time is reduced. Please see the app note titled  
“Understanding CoolRunner Clocking Options” for more detail.  
There are two feedback paths to the ZIA: one from the macrocell,  
and one from the I/O pin. The ZIA feedback path before the output  
buffer is the macrocell feedback path, while the ZIA feedback path  
after the output buffer is the I/O pin feedback path. When the  
macrocell is used as an output, the output buffer is enabled, and the  
macrocell feedback path can be used to feedback the logic  
implemented in the macrocell. When the I/O pin is used as an input,  
the output buffer will be 3-Stated and the input signal will be fed into  
the ZIA via the I/O feedback path, and the logic implemented in the  
buried macrocell can be fed back to the ZIA via the macrocell  
feedback path. It should be noted that unused inputs or I/Os should  
be properly terminated (See the section on terminations in this data  
sheet and the app note Terminating Unused CoolRunner I/O  
Pins).  
The six control terms of each logic block are used to control the  
asynchronous Preset/Reset of the flip-flops and the enable/disable  
of the output buffers in each macrocell. Control terms CT0 and CT1  
are used to control the asynchronous Preset/Reset of the  
TO ZIA  
PAL  
PLA  
D/T  
Q
INIT  
(P or R)  
GTS  
CLK0  
CLK0  
CLK1  
CLK1  
GND  
CT0  
CT1  
GND  
SP00551  
Figure 3. PZ5032C Macrocell Architecture  
5
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
5 product terms or less, the t = 6ns, the t = 4.5ns, and the  
Simple Timing Model  
Figure 4 shows the CoolRunner Timing Model. The CoolRunner  
timing model looks very much like a 22V10 timing model in that  
PD  
SU  
t
= 5ns. If an output is using 6 to 37 product terms, an additional  
CO  
2.5ns must be added to the t and t timing parameters to  
PD  
SU  
account for the time to propagate through the PLA array.  
there are three main timing parameters, including t , t , and t  
.
PD SU  
CO  
In other competing architectures, the user may be able to fit the  
design into the CPLD, but is not sure whether system timing  
requirements can be met until after the design has been fit into the  
device. This is because the timing models of competing  
architectures are very complex and include such things as timing  
dependencies on the number of parallel expanders borrowed,  
sharable expanders, varying number of X and Y routing channels  
used, etc. In the XPLA architecture, the user knows up front  
whether the design will meet system timing requirements. This is  
due to the simplicity of the timing model. For example, in the  
TotalCMOS Design Technique  
for Fast Zero Power  
Philips is the first to offer a TotalCMOS CPLD, both in process  
technology and design technique. Philips employs a cascade of  
CMOS gates to implement its Sum of Products instead of the  
traditional sense amp approach. This CMOS gate implementation  
allows Philips to offer CPLDs which are both high performance and  
low power, breaking the paradigm that to have low power, you must  
have low performance. Refer to Figure 5 and Table 2 showing the I  
DD  
vs. Frequency of our PZ5032C TotalCMOS CPLD.  
PZ5032C device, the user knows up front that if a given output uses  
t
= COMBINATORIAL PAL ONLY  
= COMBINATORIAL PAL + PLA  
PD_PAL  
t
PD_PLA  
INPUT PIN  
OUTPUT PIN  
REGISTERED  
= PAL ONLY  
t
t
REGISTERED  
SU_PAL  
= PAL + PLA  
t
SU_PLA  
CO  
INPUT PIN  
D
Q
OUTPUT PIN  
SP00552  
GLOBAL CLOCK PIN  
Figure 4. CoolRunner Timing Model  
80  
TYPICAL  
60  
I
DD  
40  
20  
0
(mA)  
0
20  
40  
60  
80  
100  
120  
140  
160  
180  
FREQUENCY (MHz)  
SP00635  
Figure 5.  
I vs. Frequency @ V = 5.0V  
DD DD  
Table 2. I vs Frequency  
DD  
V
DD  
= 5.00V  
FREQ  
(MHz)  
0
1
20  
40  
60  
80  
100  
120  
18.7  
140  
160  
180  
Typical I  
(mA)  
DD  
0.04  
0.20  
3.14  
6.25  
9.32  
12.5  
15.5  
21.7  
24.7  
27.8  
6
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
factory with these I/O pins set to perform JTAG functions, but  
through the software, the final function of these pins can be  
JTAG Testing Capability  
JTAG is the commonly-used acronym for the Boundary Scan Test  
(BST) feature defined for integrated circuits by IEEE Standard  
1149.1. This standard defines input/output pins, logic control  
functions, and commands which facilitate both board and device  
level testing without the use of specialized test equipment. The  
Philips PZ5032C devices use the JTAG interface for In–System  
Programming/Reprogramming. Although only a subset of the full  
JTAG command set is implemented (see Table 5), the devices are  
fully capable of sitting in a JTAG scan chain.  
controlled. If the end application will require the device to be  
reprogrammed at some future time with ISP, then the pins can be  
left as dedicated JTAG functions, which means they are not  
available for use as general purpose I/O pins. However, unlike  
competing CPLDs, the Philips PZ5032C allow the macrocells  
associated with these pins to be used as buried logic when the  
JTAG/ISP function is enabled. This is the default state for the  
software, and no action is required to leave these pins enabled for  
the JTAG/ISP functions. If, however, JTAG/ISP is not required in the  
end application, the software can specify that this function be turned  
off and that these pins be used as general purpose I/O. Because the  
devices initially have the JTAG/ISP functions enabled, the JEDEC  
file can be down loaded into the device once, after which the  
JTAG/ISP pins will become general purpose I/O. This feature is  
good for manufacturing because the devices can be programmed  
during test and assembly of the end product and yet still use all of  
the I/O pins after the programming is done. It eliminates the need for  
a costly, separate programming step in the manufacturing process.  
Of course, if the JTAG/ISP function is never required, this feature  
can be turned off in the software and the device can be programmed  
with an industry-standard programmer, leaving the pins available for  
I/O functions. Table 4 defines the dedicated pins used by the four  
mandatory JTAG signals for each of the PZ5032C package types.  
The Philips PZ5032C’s JTAG interface includes a TAP Port defined  
by the IEEE 1149.1 JTAG Specification. As implemented in the  
Philips PZ5032C, the TAP Port includes four of the five pins (refer to  
Table 3) described in the JTAG specification: TCK, TMS, TDI, and  
TDO. The fifth signal defined by the JTAG specification is TRST*  
(Test Reset). TRST* is considered an optional signal, since it is not  
actually required to perform BST or ISP. The Philips PZ5032C saves  
an I/O pin for general purpose use by not implementing the optional  
TRST* signal in the JTAG interface. Instead, the Philips PZ5032C  
supports the test reset functionality through the use of its power up  
reset circuit, which is included in all Philips CPLDs. The pins  
associated with the TAP Port should connect to an external pull–up  
resistor to keep the JTAG pins from floating when they are not being  
used (see section on Terminations).  
In the Philips PZ5032C, the four mandatory JTAG pins each require  
a unique, dedicated pin on the device. The devices come from the  
Table 3. JTAG Pin Description  
PIN  
TCK  
TMS  
TDI  
NAME  
DESCRIPTION  
Test Clock Output  
Test Mode Select  
Test Data Input  
Test Data Output  
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins, respectively.  
Serial input pin selects the JTAG instruction mode. TMS should be driven high during user mode operation.  
Serial input pin for instructions and test data. Data is shifted in on the rising edge of TCK.  
TDO  
Serial output pin for instructions and test data. Data is shifted out on the falling edge of TCK. The signal is  
tri-stated if data is not being shifted out of the device.  
Table 4. PZ5032C JTAG Pinout by Package Type  
(PIN NUMBER / MACROCELL #)  
DEVICE  
TCK  
TMS  
TDI  
TDO  
PZ5032C  
44-pin PLCC  
44-pin TQFP  
32/B8  
26/B8  
13/A8  
7/A8  
7/A3  
1/A3  
38/B3  
32/B3  
Table 5. PZ5032C Low-Level JTAG Boundary-Scan Commands  
INSTRUCTION  
(Instruction Code)  
Register Used  
DESCRIPTION  
Bypass  
(1111)  
Bypass Register  
Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data to pass  
synchronously through the selected device to adjacent devices during normal device operation. The Bypass  
instruction can be entered by holding TDI at a constant high value and completing an Instruction-Scan cycle.  
Idcode  
(0001)  
Boundary-Scan Register  
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted  
out of TDO. The IDCODE instruction permits blind interrogation of the components assembled onto a printed  
circuit board. Thus, in circumstances where the component population may vary, it is possible to determine  
what components exist in a product.  
7
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
required by the device for normal operation. A set of low-level ISP  
basic commands implemented in the PZ5032C enable this feature.  
The ISP commands implemented in the Philips PZ5032C are  
specified in Table 6. Please note that an ENABLE command must  
precede all ISP commands unless an ENABLE command has  
already been given for a preceding ISP command.  
5-Volt, In-System Programming (ISP)  
ISP is the ability to reconfigure the logic and functionality of a  
device, printed circuit board, or complete electronic system before,  
during, and after its manufacture and shipment to the end customer.  
ISP provides substantial benefits in each of the following areas:  
• Design  
– Faster time-to-market  
Terminations  
– Debug partitioning and simplified prototyping  
– Printed circuit board reconfiguration during debug  
– Better device and board level testing  
The CoolRunner PZ5032C CPLDs are TotalCMOS devices. As  
with other CMOS devices, it is important to consider how to properly  
terminate unused inputs and I/O pins when fabricating a PC board.  
The PZ5032C devices do not have on-chip termination circuits, so it  
is recommended that unused inputs and I/O pins be properly  
terminated. Allowing unused inputs and I/O pins to float can cause  
the voltage to be in the linear region of the CMOS input structures,  
which can increase the power consumption of the device. Philips  
recommends the use of 10KΩ pull-up resistors for the termination.  
Using pull-up resistors allows the flexibility of using these pins  
should late design changes require additional I/O. These unused  
• Manufacturing  
– Multi-Functional hardware  
– Reconfigurability for Test  
– Eliminates handling of “fine lead-pitch” components for  
programming  
– Reduced Inventory and manufacturing costs  
– Improved quality and reliability  
pins may also be tied directly to V , but this will make it more  
DD  
difficult to reclaim the use of the pin, should this be needed by a  
subsequent design revision.  
• Field Support  
– Easy remote upgrades and repair  
– Support for field configuration, re-configuration, and  
customization  
When using the JTAG/ISP functions, it is also recommended that  
10KΩ pull-up resistors be used on each of the four mandatory  
signals. Letting these signals float can cause the voltage on TMS to  
come close to ground, which could cause the device to enter  
JTAG/ISP mode at unspecified times. See the application notes  
JTAG and ISP in Philips Devices and Terminating Unused  
CoolRunner I/O Pins for more information.  
The Philips PZ5032C allows for 5-Volt, in-system  
programming/reprogramming of its EEPROM cells via its JTAG  
interface. An on-chip charge pump eliminates the need for  
externally-provided supervoltages, so that the PZ5032C may be  
easily programmed on the circuit board using only the 5-volt supply  
Table 6. Low Level ISP Commands  
INSTRUCTION  
(Register Used)  
INSTRUCTION  
CODE  
DESCRIPTION  
Enable  
(ISP Shift Register)  
1001  
1010  
1011  
1100  
Enables the Erase, Program, and Verify commands.  
Erases the entire EEPROM array.  
Erase  
(ISP Shift Register)  
Program  
(ISP Shift Register)  
Programs the data in the ISP Shift Register into the addressed EEPROM row.  
Verify  
(ISP Shift Register)  
Transfers the data from the addressed row to the ISP Shift Register. The data can then be  
shifted out and compared with the JEDEC file. The outputs during this operation can be  
defined by the user.  
8
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
JTAG and ISP Interfacing  
• Automated Test Equipment  
• Third party Programmers  
• High-End ISP Tools  
A number of industry-established methods exist for JTAG/ISP  
interfacing with CPLD’s and other integrated circuits. The Philips  
PZ5032C supports the following methods:  
• PC Parallel Port  
• Workstation or PC Serial Port  
• Embedded Processor  
For more details on JTAG and ISP for the PZ5032C, refer to the  
related application note: JTAG and ISP in Philips CPLDs.  
PROGRAMMING SPECIFICATIONS  
SYMBOL  
PARAMETER  
MIN.  
4.5  
MAX.  
UNIT  
DC Parameters  
V
V
supply program/verify  
5.5  
V
mA  
V
CCP  
CCP  
CC  
I
I
limit program/verify  
200  
CC  
V
V
V
V
Input voltage (High)  
Input voltage (Low)  
Output voltage (Low)  
Output voltage (High)  
Output current (Low)  
Output current (High)  
2.0  
IH  
0.8  
0.5  
V
IL  
V
SOL  
SOH  
2.4  
8
V
TDO_I  
mA  
mA  
OL  
TDO_I  
8
OH  
AC Parameters  
f
TCK maximum frequency  
Pulse width erase  
10  
100  
10  
MHz  
ms  
ms  
µs  
MAX  
PWE  
PWP  
Pulse width program  
PWV  
Pulse width verify  
10  
INIT  
Initialization time  
100  
10  
µs  
TMS_SU  
TDI_SU  
TMS_H  
TDI_H  
TDO_CO  
TMS setup time before TCK ↑  
TDI setup time before TCK ↑  
TMS hold time after TCK ↑  
TDI hold time after TCK ↑  
TDO valid after TCK ↓  
ns  
10  
ns  
25  
ns  
25  
ns  
40  
ns  
9
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
1
ABSOLUTE MAXIMUM RATINGS  
SYMBOL  
PARAMETER  
MIN.  
–0.5  
–1.2  
–0.5  
–30  
MAX.  
7.0  
UNIT  
V
2
V
V
V
Supply voltage  
Input voltage  
Output voltage  
Input current  
Output current  
DD  
I
V
DD  
V
DD  
+0.5  
V
+0.5  
V
OUT  
I
I
30  
mA  
mA  
°C  
°C  
IN  
OUT  
–100  
–40  
100  
150  
150  
T
J
Maximum junction temperature  
Storage temperature  
T
str  
–65  
NOTES:  
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at  
these or any other condition above those indicated in the operational and programming specification is not implied.  
2. The chip supply voltage must rise monotonically.  
OPERATING RANGE  
PRODUCT GRADE  
TEMPERATURE  
VOLTAGE  
Commercial  
0 to +70°C  
5 ±5% V  
10  
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES  
Commercial: 0°C ≤ T  
≤ +70°C; 4.75V ≤ V ≤ 5.25V  
amb  
DD  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN.  
MAX.  
UNIT  
V
V
V
V
V
V
Input voltage low  
V
DD  
V
DD  
= 4.75V  
= 5.25V  
0.8  
IL  
Input voltage high  
Input clamp voltage  
Output voltage low  
Output voltage high  
2.0  
V
IH  
I
2
V
= 4.75V, I = –18mA  
–1.2  
0.5  
V
DD  
IN  
V
= 4.75V, I = 12mA  
V
OL  
OH  
DD  
OL  
V
= 4.75V, I = –12mA  
2.4  
–10  
–10  
–10  
–10  
–10  
V
DD  
OH  
I
I
I
I
I
I
Input leakage current low  
V
= 5.25V (except CKO), V = 0.4V  
10  
10  
10  
10  
10  
75  
1
µA  
µA  
µA  
µA  
µA  
µA  
mA  
mA  
mA  
pF  
pF  
pF  
IL  
DD  
IN  
Input leakage current high  
Clock input leakage current  
3-Stated output leakage current low  
3-Stated output leakage current high  
Standby current  
V
V
V
V
= 5.25V, V = 3.0V  
IN  
IH  
DD  
DD  
DD  
DD  
DD  
= 5.25V, V = 0.4V  
IL  
IN  
= 5.25V, V = 0.4V  
OZL  
OZH  
DDQ  
IN  
= 5.25V, V = 3.0V  
IN  
V
= 5.25V, T  
= 0°C  
amb  
V
DD  
= 5.25V, T  
= 0°C @ 1MHz  
= 0°C @ 50MHz  
amb  
amb  
1
I
Dynamic current  
DDD  
V
DD  
= 5.25V, T  
15  
–200  
8
2
I
Short circuit output current  
1 pin at a time for no longer than 1 second  
–50  
5
OS  
C
C
C
Input pin capacitance  
Clock input capacitance  
I/O pin capacitance  
T
= 25°C, f = 1MHz  
= 25°C, f = 1MHz  
= 25°C, f = 1MHz  
IN  
amb  
T
amb  
12  
10  
CLK  
T
amb  
I/O  
NOTE:  
1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded.  
Inputs are tied to V or ground. This parameter guaranteed by design and characterization, not testing.  
DD  
2. This parameter guaranteed by design and characterization, not by test.  
1
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES  
Commercial: 0°C ≤ T  
≤ +70°C; 4.75V ≤ V ≤ 5.25V  
amb  
DD  
–6  
–7  
–10  
SYMBOL  
PARAMETER  
UNIT  
MIN. MAX. MIN. MAX. MIN. MAX.  
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
t
t
t
t
t
t
t
Propagation delay time, input (or feedback node) to output through PAL  
2
3
6
8
2
3
7.5  
10  
7
2
3
10  
12.5  
9
ns  
ns  
PD_PAL  
PD_PLA  
CO  
Propagation delay time, input (or feedback node) to output through PAL & PLA  
Clock to out delay time  
2
5.5  
2
2
ns  
Setup time (from input or feedback node) through PAL  
3.5  
5.5  
5.5  
8
8
ns  
SU_PAL  
SU_PLA  
H
Setup time (from input or feedback node) through PAL + PLA  
10.5  
ns  
Hold time  
0
0
0
ns  
Clock High time  
Clock Low time  
Input rise time  
3
3
4
4
5
5
ns  
CH  
ns  
CL  
20  
20  
20  
20  
20  
20  
ns  
R
Input fall time  
ns  
F
2
Maximum FF toggle rate  
Maximum internal frequency  
Maximum external frequency  
Output buffer delay time  
(1/t + t )  
167  
133  
111  
125  
91  
100  
64  
MHz  
MHz  
MHz  
ns  
MAX1  
MAX2  
MAX3  
BUF  
CH  
CL  
2
(1/t  
+ t  
)
SUPAL  
CF  
2
(1/t  
+ t  
)
80  
59  
SUPAL  
CO  
1.5  
4.5  
6.5  
4
1.5  
6
1.5  
8.5  
11  
Input (or feedback node) to internal feedback node delay time through PAL  
Input (or feedback node) to internal feedback node delay time through PAL + PLA  
Clock to internal feedback node delay time  
ns  
PDF_PAL  
PDF_PLA  
CF  
8.5  
ns  
5.5  
7.5  
50  
15  
15  
15  
18  
ns  
Delay from valid V to valid reset  
50  
11  
11  
11  
14  
50  
µs  
INIT  
DD  
2, 3  
Input to output disable  
12.5  
12.5  
12.5  
15.5  
ns  
ER  
2
Input to output valid  
ns  
EA  
2
Input to register preset  
ns  
RP  
2
Input to register reset  
ns  
RR  
NOTES:  
1. Specifications measured with one output switching. See Figure 6 and Table 7 for derating.  
2. This parameter guaranteed by design and characterization, not by test.  
3. Output C = 5pF.  
L
11  
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
SWITCHING CHARACTERISTICS  
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.  
V
DD  
COMPONENT  
VALUES  
470Ω  
S1  
R1  
R2  
C1  
250Ω  
R1  
R2  
35pF  
V
IN  
V
OUT  
MEASUREMENT  
S1  
S2  
C1  
t
Open  
Closed  
Closed  
Closed  
PZH  
t
Closed  
Closed  
PZL  
t
P
S2  
NOTE: For t  
and t  
C = 5pF, and 3-State levels are  
PHZ  
PLZ  
measured 0.5V from steady state active level.  
SP00476  
VOLTAGE WAVEFORM  
ns  
V
= 5V, 25°C  
DD  
6.00  
+3.0V  
90%  
5.60  
10%  
0V  
t
R
t
F
1.5ns  
1.5ns  
5.20  
4.80  
TYPICAL  
SP00368  
MEASUREMENTS:  
All circuit delays are measured at the +1.5V level of  
inputs and outputs, unless otherwise specified.  
Input Pulses  
4.40  
4.00  
16  
1
2
4
8
12  
SP00636  
Figure 6.  
PD_PAL  
t
vs. Outputs switching  
PD_PAL  
Table 7. t  
DD  
vs # of Outputs switching  
V
= 5.00V  
# of  
Outputs  
1
2
4
8
12  
16  
5.2  
Typical  
(ns)  
4.2  
4.4  
4.6  
4.9  
5.0  
12  
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
PIN DESCRIPTIONS  
Package Thermal Characteristics  
Philips Semiconductors uses the Temperature Sensitive Parameter  
(TSP) method to test thermal resistance. This method meets  
Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC  
Package Databook. Thermal resistance varies slightly as a function  
of input power. As input power increases, thermal resistance  
changes approximately 5% for a 100% change in power.  
PZ5032C –  
44-Pin Plastic Leaded Chip Carrier  
6
1
40  
7
39  
Figure 7 is a derating curve for the change in Θ with airflow based  
JA  
on wind tunnel measurements. It should be noted that the wind flow  
dynamics are more complex and turbulent in actual applications  
than in a wind tunnel. Also, the test boards used in the wind tunnel  
contribute significantly to forced convection heat transfer, and may  
not be similar to the actual circuit board, especially in size.  
PLCC  
17  
29  
18  
28  
Pin  
1
Function  
IN1  
Pin  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
Function  
I/O–A10  
I/O–A11  
I/O–A12  
I/O–A13  
I/O–A14  
I/O–A15  
Pin  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
Function  
I/O–B9  
Package  
44-pin PLCC  
Θ
JA  
2
IN3  
I/O–B8 (TCK)  
I/O–B7  
3
V
DD  
49.8°C/W  
66.3°C/W  
4
I/O–A0–CK1  
I/O–A1  
I/O–B6  
5
V
DD  
44-pin TQFP  
6
I/O–A2  
I/O–B5  
7
I/O–A3 (TDI)  
I/O–A4  
I/O–B4  
GND  
8
V
I/O–B3 (TDO)  
I/O–B2  
DD  
9
I/O–A5  
I/O–B15  
I/O–B14  
I/O–B13  
I/O–B12  
I/O–B11  
I/O–B10  
GND  
10  
11  
12  
13  
14  
15  
GND  
I/O–B1  
0
10  
20  
30  
40  
50  
PERCENTAGE  
REDUCTION IN  
I/O–A6  
I/O–B0  
I/O–A7  
GND  
Θ
(%)  
JA  
I/O–A8 (TMS)  
I/O–A9  
IN0–CK0  
IN2–gtsn  
V
DD  
SP00546  
PZ5032C –  
44-Pin Thin Quad Flat Package  
44  
34  
PLCC/  
QFP  
1
33  
23  
TQFP  
0
1
2
3
4
5
AIR FLOW (m/s)  
11  
SP00419A  
12  
22  
Figure 7. Average Effect of Airflow on Θ  
JA  
Pin  
1
Function  
I/O–A3 (TDI)  
I/O–A4  
Pin  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
Function  
Pin  
Function  
I/O–B4  
I/O–B3 (TDO)  
I/O–B2  
I/O–B1  
I/O–B0  
GND  
GND  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
2
V
DD  
3
I/O–A5  
I/O–B15  
I/O–B14  
I/O–B13  
I/O–B12  
I/O–B11  
I/O–B10  
GND  
4
GND  
5
I/O–A6  
6
I/O–A7  
7
I/O–A8 (TMS)  
I/O–A9  
IN0–CK0  
IN2–gtsn  
IN1  
8
9
V
DD  
10  
11  
12  
13  
14  
15  
I/O–A10  
I/O–A11  
I/O–A12  
I/O–A13  
I/O–A14  
I/O–A15  
I/O–B9  
IN3  
I/O–B8 (TCK)  
I/O–B7  
V
DD  
I/O–A0–CK1  
I/O–A1  
I/O–B6  
V
I/O–A2  
DD  
I/O–B5  
SP00547  
13  
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
PLCC44: plastic leaded chip carrier; 44 leads  
SOT187-2  
14  
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
TQFP44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm  
SOT376-1  
15  
1998 Jul 23  
Philips Semiconductors  
Product specification  
32 macrocell CPLD with enhanced clocking  
PZ5032C  
Data sheet status  
[1]  
Data sheet  
status  
Product  
status  
Definition  
Objective  
specification  
Development  
This data sheet contains the design target or goal specifications for product development.  
Specification may change in any manner without notice.  
Preliminary  
specification  
Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date.  
Philips Semiconductors reserves the right to make chages at any time without notice in order to  
improve design and supply the best possible product.  
Product  
specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make  
changes at any time without notice in order to improve design and supply the best possible product.  
[1] Please consult the most recently issued datasheet before initiating or completing a design.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1998  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
Date of release: 07-98  
Document order number:  
9397 750 04176  
Philips  
Semiconductors  
厂商 型号 描述 页数 下载

ETC

 		PZ5032 32宏单元CPLD\n[ 32 Macrocell CPLD ] 14 页

ETC

 		PZ5032-10(TBD) ASIC[ ASIC ] 12 页

XILINX

 		PZ5032-10A44 [ EE PLD, 12.5ns, 32-Cell, CMOS, PQCC44 ] 13 页

XILINX

 		PZ5032-10BC [ EE PLD, 12.5ns, 32-Cell, CMOS, PQFP44 ] 13 页

ETC

 		PZ5032-10BC-S 电可擦除可编程逻辑器件复杂\n[ Electrically-Erasable Complex PLD ] 13 页

ETC

 		PZ5032-6(TBD) ASIC[ ASIC ] 12 页

XILINX

 		PZ5032-6A44 [ EE PLD, 8ns, 32-Cell, CMOS, PQCC44 ] 13 页

XILINX

 		PZ5032-6BC [ EE PLD, 8ns, 32-Cell, CMOS, PQFP44 ] 13 页

ETC

 		PZ5032-6BC-S 电可擦除可编程逻辑器件复杂\n[ Electrically-Erasable Complex PLD ] 13 页

ETC

 		PZ5032-7(TBD) ASIC[ ASIC ] 12 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于壹壹捌

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：sales@ic118.com

服务时间：周一至周六 8:30-17:30

壹壹捌官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.200278s