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HYS64V16220GCDL-7.5-X

型号：

HYS64V16220GCDL-7.5-X

品牌：

INFINEON[ Infineon ]

页数：

18 页

PDF大小：

133 K

下载PDF手册
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
3.3 V SDRAM Modules  
144-pin SO-DIMM SDRAM Modules  
PC100/PC133  
32 MB, 64 MB & 128 MB Density in COB Technique  
• 144-pin Eight Byte Small Outline Dual-In-Line • Auto Refresh (CBR) and Self Refresh  
Synchronous DRAM Modules for notebook  
• Decoupling capacitors mounted on substrate  
applications  
• All inputs and outputs are LVTTL compatible  
• One bank 4M × 64 non-parity organization  
• Serial Presence Detect with E2PROM  
• Two bank 8M × 64 and 16M × 64 non-parity  
module organization  
• Uses COB (“Chip-on-Board”) technique  
• 4096 refresh cycles every 64 ms  
• Gold contact pad  
• suitable for use in PC100 and PC133  
applications  
• Auto ReSingle + 3.3 V (± 0.3 V) power supply  
• This module family is fully pin and functional  
compatible with the latest INTEL SO-DIMM  
specification  
• Programmable CAS Latency, Burst Length,  
and Wrap Sequence (Sequential &  
Interleave)  
• Performance:  
-7.5  
-8  
Unit  
PC133  
3-3-3  
PC100  
2-2-2  
fCK  
tAC  
Clock Frequency (max.)  
133  
5.4  
100  
6
MHz  
ns  
Clock Access Time  
CAS Latency = 2 & 3  
This Infineon module family are industry standard 144-pin 8-byte Synchronous DRAM (SDRAM)  
Small Outline Dual In-line Memory Modules (SO-DIMM) which are organized as x64 high speed  
memory arrays designed for use in non-parity applications. These SO-DIMMs use COB (“Chip-on-  
Board”) technology. Decoupling capacitors are mounted on the board.  
The DIMMs use optional serial presence detects implemented via a serial E2PROM using the 2-pin  
I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes  
are available to the end user.  
All Infineon 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67.5 mm  
long footprint.  
Data Book  
1
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
Product Sprectrum  
Organi- Partnumber  
zation  
SDRAMs Row Bank  
Used Addr. Select  
Column Refresh Period  
Addr.  
4M × 64 HYS64V4220GCDL-7.5 4 4M × 16 12  
8M × 64 HYS64V8220GCDL-7.5 8 4M × 16 12  
16M × 64 HYS64V16220GCDL-7.5 16 8M × 8 12  
BA0, BA1 8  
BA0, BA1 8  
BA0, BA1 9  
BA0, BA1 8  
BA0, BA1 8  
BA0, BA1 9  
4k  
4k  
4k  
4k  
4k  
4k  
64 ms  
64 ms  
64 ms  
64 ms  
64 ms  
64 ms  
4M × 64 HYS64V4220GCDL-8  
8M × 64 HYS64V8220GCDL-8  
16M × 64 HYS64V16220GCDL-8  
4 4M × 16 12  
8 4M × 16 12  
16 8M × 8 12  
Note: All partnumbers end with a place code (not shown), designating the die revision. Consult  
factory for current revision. Example: HYS 64V16220GCDL-8-B, indicating Rev.B dies are  
used for SDRAM components.  
Card Dimensions  
Organization  
4M × 64  
PCB-Board  
L × H × T [mm]  
L-DIM-144-C8  
L-DIM-144-C8  
L-DIM-144-C9  
67.60 × 25.40 × 3.80  
67.60 × 25.40 × 3.80  
67.60 × 25.40 × 3.80  
8M × 64  
16M × 64  
Pin Definitions and Functions  
A0 - A11  
Address Inputs  
DQMB0 - Data Mask  
DQMB7  
BA0, BA1  
Bank Selects  
CS0 - CS3 Chip Select  
DQ0 - DQ63 Data Input/Output  
VDD  
VSS  
SCL  
SDA  
N.C.  
–
Power (+ 3.3 V)  
RAS  
CAS  
WE  
Row Address Strobe  
Column Address Strobe  
Read/Write Input  
Clock Enable  
Ground  
Clock for Presence Detect  
Serial Data Out for Presence Detect  
CKE0  
CLK0  
No Connection  
Clock Input  
–
Data Book  
2
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
Pin Configuration  
PIN# Front Side  
PIN# Back Side  
PIN# Front Side  
PIN# Back Side  
1
VSS  
2
VSS  
73  
N.C.  
74  
CLK1  
VSS  
3
DQ0  
DQ1  
DQ2  
DQ3  
VDD  
4
DQ32  
DQ33  
DQ34  
DQ35  
VDD  
75  
VSS  
76  
5
6
77  
N.C.  
78  
N.C.  
7
8
79  
N.C.  
80  
N.C.  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
81  
VDD  
82  
VDD  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
83  
DQ16  
DQ17  
DQ18  
DQ19  
VSS  
84  
DQ48  
DQ49  
DQ50  
DQ51  
VSS  
DQ4  
DQ5  
DQ6  
DQ7  
VSS  
DQ36  
DQ37  
DQ38  
DQ39  
VSS  
85  
86  
87  
88  
89  
90  
91  
92  
93  
DQ20  
DQ21  
DQ22  
DQ23  
VDD  
94  
DQ52  
DQ53  
DQ54  
DQ55  
VDD  
DQMB0  
DQMB1  
VDD  
DQMB4  
DQMB5  
VDD  
95  
96  
97  
98  
99  
100  
102  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
132  
134  
136  
138  
A0  
A3  
101  
103  
105  
107  
109  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
A1  
A4  
A6  
A7  
A2  
A5  
A8  
BA0  
VSS  
VSS  
VSS  
VSS  
DQ8  
DQ9  
DQ10  
DQ11  
VDD  
DQ40  
DQ41  
DQ42  
DQ43  
VDD  
A9  
BA1  
A10  
A11  
VDD  
VDD  
DQMB2  
DQMB3  
VSS  
DQMB6  
DQMB7  
VSS  
DQ12  
DQ13  
DQ14  
DQ15  
VSS  
DQ44  
DQ45  
DQ46  
DQ47  
VSS  
DQ24  
DQ25  
DQ26  
DQ27  
VDD  
DQ56  
DQ57  
DQ58  
DQ59  
VDD  
N.C.  
N.C.  
CLK0  
VDD  
N.C.  
N.C.  
DQ28  
DQ29  
DQ30  
DQ31  
DQ60  
DQ61  
DQ62  
DQ63  
CKE0  
VDD  
RAS  
CAS  
Data Book  
3
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
Pin Configuration (cont’d)  
PIN# Front Side PIN# Back Side  
PIN# Front Side  
PIN# Back Side  
67  
69  
71  
WE  
68  
70  
72  
CKE1  
(A12)  
(A13)  
139  
141  
143  
VSS  
140  
142  
144  
VSS  
SCL  
VDD  
CS0  
CS1  
SDA  
VDD  
WE  
CS0  
CS WE  
LDQM  
CS WE  
LDQM  
DQMB0  
DQMB4  
DQ0-DQ7  
DQ32-DQ39  
DQ0-DQ7  
DQ0-DQ7  
DQMB1  
DQMB5  
UDQM  
UDQM  
DQ8-DQ15  
DQ40-DQ47  
DQ8-DQ15  
DQ8-DQ15  
D0  
D2  
CS WE  
LDQM  
CS WE  
LDQM  
DQMB2  
DQMB6  
DQ16-DQ23  
DQ48-DQ55  
DQ0-DQ7  
DQ0-DQ7  
DQMB3  
DQMB7  
UDQM  
UDQM  
DQ24-DQ31  
DQ56-DQ63  
DQ8-DQ15  
DQ8-DQ15  
D1  
D3  
A0-A11, BA0, BA1  
D0-D3  
D0-D3  
D0-D3  
D0-D3  
D0-D3  
D0-D3  
4 SDRAM  
E2PROM  
(256 word x 8 Bit)  
VCC  
C1-C4  
SA0  
SCL  
SA1  
SDA  
SA2  
VSS  
RAS  
CAS  
CKE0  
CLK0  
CLK1  
Note: All resistors are 10 Ω  
10 pF  
SPB04133  
Block Diagram: One Bank 4M × 64 SDRAM DIMM Module  
Data Book  
4
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
WE  
CS0  
CS1  
CS WE  
LDQM  
CS WE  
LDQM  
CS  
LDQM  
WE  
CS  
LDQM  
WE  
DQMB0  
DQMB4  
DQ0-DQ7  
DQ32-DQ39  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQMB1  
DQMB5  
UDQM  
UDQM  
UDQM  
UDQM  
DQ8-DQ15  
DQ40-DQ47  
DQ8-DQ15  
DQ8-DQ15  
DQ8-DQ15  
DQ8-DQ15  
D0  
D4  
D2  
D6  
CS WE  
LDQM  
CS WE  
LDQM  
CS  
LDQM  
WE  
CS  
LDQM  
WE  
DQMB2  
DQMB6  
DQ16-DQ23  
DQ48-DQ55  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQMB3  
DQMB7  
UDQM  
UDQM  
UDQM  
UDQM  
DQ24-DQ31  
DQ56-DQ63  
DQ8-DQ15  
DQ8-DQ15  
DQ8-DQ15  
DQ8-DQ15  
D1  
D5  
D3  
D7  
A0-A11, BA0, BA1  
D0-D7  
D0-D7  
D0-D7  
D0-D7  
D0-D7  
D0-D7  
E2PROM  
(256 word x 8 Bit)  
VCC  
C1-C4  
SA0  
SCL  
SA1  
SDA  
SA2  
VSS  
RAS  
CAS  
CKE0  
CLK0  
CLK1  
4 SDRAM  
4 SDRAM  
Note: All resistors are 10 Ω  
SPB04134  
Block Diagram: Two Bank 8M × 64 SDRAM DIMM Module  
Data Book  
5
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
CS1  
CS0  
CS  
CS  
CS  
CS  
DQMB0  
DQM  
DQM  
DQMB4  
DQM  
DQM  
DQ0-DQ7  
DQ0-DQ7  
DQ0-DQ7  
DQ32-DQ39  
DQ0-DQ7  
DQ0-DQ7  
DQMB1  
DQM  
DQM  
DQMB5  
DQM  
DQM  
DQ8-DQ15  
DQ0-DQ7  
DQ0-DQ7  
DQ40-DQ47  
DQ0-DQ7  
DQ0-DQ7  
D0  
D4  
D2  
D6  
CS  
DQM  
CS  
DQM  
CS  
DQM  
CS  
DQM  
DQMB2  
DQMB6  
DQ16-DQ23  
DQ0-DQ7  
DQ0-DQ7  
DQ48-DQ55  
DQ0-DQ7  
DQ0-DQ7  
DQMB3  
DQM  
DQM  
DQMB7  
DQM  
DQM  
DQ24-DQ31  
DQ0-DQ7  
DQ0-DQ7  
DQ56-DQ63  
DQ0-DQ7  
DQ0-DQ7  
D1  
D5  
D3  
D7  
A0-A11, BA0, BA1  
D0-D7  
D0-D7  
D0-D7  
D0-D15  
D0-D3  
D4-D7  
E2PROM (256 word x 8 Bit)  
VDD  
SA0  
SCL  
SA1  
SDA  
SA2  
C
V
SS  
RAS, CAS, WE  
CKE0  
Note: 1.DQ wiring may differ than describes in this  
drawing, however DQ/DQMB/CKE/CS relationship  
must be maintained as shown.  
2.In this design each of the D0-D7 components  
are represented by two 8 M x 8 chips. These two  
chips effectively work as a single 8 M x 16 device.  
CKE1  
CLK0  
CLK1  
4 SDRAM  
4 SDRAM  
SPB04202  
Block Diagram: Two Bank 16M × 64 SDRAM DIMM Module  
Data Book  
6
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
DC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
2.0  
Input High Voltage  
VIH  
VIL  
VDD + 0.3  
V
Input Low Voltage  
– 0.5  
2.4  
0.8  
–
V
Output High Voltage (IOUT = – 4.0 mA)  
Output Low Voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
V
–
0.4  
20  
V
Input Leakage Current, any input  
– 20  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output Leakage Current  
IO(L)  
– 20  
20  
µA  
(DQ is disabled, 0 V < VOUT < VDD)  
Capacitance  
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
4M × 64  
8M × 64  
16M × 64  
max.  
max.  
max.  
Input Capacitance (A0 to A11, BA0, BA1) CI1  
25  
35  
35  
25  
10  
25  
10  
8
50  
50  
35  
30  
15  
25  
15  
8
65  
75  
58  
40  
15  
50  
18  
8
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
Input Capacitance (RAS, CAS, WE)  
Input Capacitance (CLK0, CLK1)  
Input Capacitance (CS0, CS1)  
CI2  
CI3  
CI4  
CI5  
Input Capacitance (DQMB0 - DQMB7)  
Input/Output Capacitance (DQ0 - DQ63) CIO  
Input Capacitance (SCL, SA0 - 2)  
Input/Output Capacitance  
CSC  
CSD  
Data Book  
7
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
Operating Currents per Memory Bank  
TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V  
(Recommended Operating Conditions unless otherwise noted)  
Parameter  
Test Condition Symbol  
Unit Note  
1)  
Operating current  
–
ICC1  
260 520 1024 mA  
tRC = tRC(MIN.), tCK = tCK(MIN.)  
Outputs open, Burst Length = 4, CL = 3  
All banks operated in random access,  
all banks operated in ping-pong manner  
to maximize gapless data access  
1)  
1)  
Precharge stand-by current  
in Power Down Mode  
t
CK = min.  
ICC2P  
4
2
8
4
16  
8
mA  
mA  
tCK = infinity  
ICC2PS  
CS = VIH(MIN.), CKE ≤ VIL(MAX.)  
1)  
1)  
Precharge Stand-by Current  
in Non-Power Down Mode  
t
CK = min.  
ICC2N  
70 140 280 mA  
10 20 40 mA  
tCK = infinity  
ICC2NS  
CS = VIH (MIN.), CKE ≥ VIH(MIN.)  
1)  
1)  
No operating current  
CKE ≥ VIH(MIN.) ICC3N  
CKE ≤ VIL(MAX.) ICC3P  
90 180 360 mA  
16 32 64 mA  
tCK = min., CS = VIH(MIN.),  
active state (max. 4 banks)  
1), 2)  
Burst operating current  
–
–
–
ICC4  
ICC5  
ICC6  
200 400 800 mA  
260 520 1040 mA  
1.6 3.2 6.4 mA  
tCK = min.,  
Read command cycling  
1)  
Auto refresh current  
tCK = min.,  
Auto Refresh command cycling  
1)  
Self refresh current  
Self Refresh Mode, CKE = 0.2 V  
Notes  
1. These parameters depend on the cycle rate. These values are measured at 100 MHz operation  
frequency. Input signals are changed once during tCK, excepts for ICC6 and for stand-by currents  
when tCK = infinity.  
2. These parameters are measured with continuous data stream during read access and all DQ  
toggling. CL = 3 and BL = 4 are assumed and the VDDQ current is excluded.  
Data Book  
8
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
1), 2)  
AC Characteristics  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
-7.5  
PC133-333  
Unit Note  
-8  
PC100-222  
min. max. min.  
max.  
Clock and Access Time  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
tCK  
fCK  
tAC  
–
ns  
ns  
7.5  
10  
–
–
10  
10  
–
–
Clock Frequency  
CAS Latency = 3  
CAS Latency = 2  
–
MHz  
MHz  
–
–
133  
100  
–
–
100  
100  
2), 3)  
Access Time from Clock  
CAS Latency = 3  
–
–
5.4  
6
–
–
6
6
ns  
ns  
CAS Latency = 2  
Clock High Pulse Width  
Clock Low Pulse Width  
Transition Time  
tCH  
tCL  
tT  
2.5  
2.5  
0.3  
–
3
–
ns  
ns  
ns  
–
–
–
–
3
–
1.2  
0.5  
10  
Setup and Hold Parameters  
Input Setup Time  
4)  
4)  
4)  
4)  
tIS  
1.5  
0.8  
–
–
–
1
–
–
2
1
–
1
2
–
–
1
–
–
ns  
Input Hold Time  
tIH  
ns  
Power Down Mode Entry Time  
Power Down Mode Exit Setup Time  
Mode Register Set-up Time  
tSB  
tPDE  
tRSC  
CLK  
CLK  
CLK  
0.8  
2
–
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
Row Active Time  
5)  
5)  
5)  
5)  
5)  
tRCD  
tRP  
tRAS  
tRC  
20  
20  
45  
67  
14  
–
20  
20  
50  
70  
16  
–
ns  
ns  
ns  
ns  
ns  
–
–
100k  
100k  
Row Cycle Time  
–
–
–
–
Activate (a) to Activate (b) Command  
Period  
tRRD  
CAS(a) to CAS(b) Command Period  
tCCD  
1
–
1
–
CLK  
–
Data Book  
9
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
AC Characteristics (cont’d) 1), 2)  
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
-7.5  
PC133-333  
Unit Note  
-8  
PC100-222  
min. max. min.  
max.  
Refresh Cycle  
Refresh Period (4096 cycles)  
Self Refresh Exit Time  
tREF  
–
1
64  
–
–
1
64  
–
ms  
–
6)  
tSREX  
CLK  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
3
1
3
–
–
–
7
2
3
0
3
–
–
–
8
2
ns  
–
Data Out to Low Impedance Time  
Data Out to High Impedance Time  
DQM Data Out Disable Latency  
ns  
–
7)  
tHZ  
ns  
tDQZ  
CLK  
–
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
–
–
2
0
–
–
CLK  
CLK  
–
–
DQM Write Mask Latency  
tDQW  
Data Book  
10  
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
Notes  
1. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must  
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation  
can begin.  
2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover  
point. The transition time is measured between VIH and VIL. All AC measurements assume  
tT = 1 ns with the AC output load circuit shown. Specified tAC and tOH parameters are measured  
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate  
between 0.8 V and 2.0 V.  
3. If clock rising time is longer than 1 ns, a time (tT – 0.5) ns must be added to this parameter.  
4. If tT is longer than 1 ns, a time (tT – 1) ns must be added to this parameter.  
5. Whenever the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh  
commands must be given to “wake-up” the device.  
6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
after the Self Refresh Exit command is registered.  
7. Referenced to the time at which the output achieves the open circuit condition, not to output  
voltage levels.  
tCH  
2.4 V  
0.4 V  
CLOCK  
tT  
tCL  
tHOLD  
tSETUP  
INPUT  
1.4 V  
tAC  
tAC  
I/O  
tLZ  
tOH  
50 pF  
OUTPUT  
1.4 V  
Measurement conditions for  
AC and tOH  
tHZ  
t
SPT03404  
A serial presence detect storage device - E2PROM - is assembled onto the module. Information  
about the module configuration, speed, etc. is written into the E2PROM device during module  
production using a serial presence detect protocol (I2C synchronous 2-wire bus).  
Data Book  
11  
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
SPD-Table for PC100 2-2-2 SO-DIMM Modules  
Byte# Description  
SPD Entry Value  
Hex  
0
Number of SPD Bytes  
128  
80  
08  
04  
0C  
08  
02  
40  
00  
01  
A0  
60  
00  
80  
10  
00  
01  
1
Total Bytes in Serial PD  
256  
2
Memory Type  
SDRAM  
3
Number of Row Addresses (without BS)  
Number of Column Addresses  
Number of DIMM Banks  
–
4
–
08  
01  
09  
02  
5
1/2  
6
Module Data Width  
64  
7
Module Data Width (cont’d)  
Module Interface Levels  
0
8
LVTTL  
9
SDRAM Cycle Time at CL = 3  
SDRAM Access Time from Clock at CL = 3  
DIMM Config (Error Det/Corr.)  
Refresh Rate/Type  
10.0 ns  
10  
11  
12  
13  
14  
15  
6.0 ns  
none  
Self-Refresh, 15.6 µs  
SDRAM Width, Primary  
x16  
Error Checking SDRAM Data Width  
Minimum Clock Delay for Back-to-Back  
Random Column Address  
n/a/x8  
t
CCD = 1 CLK  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
Burst Length Supported  
1, 2, 4, 8 & full page  
2
8F  
04  
06  
01  
01  
00  
0E  
A0  
60  
FF  
FF  
14  
10  
14  
2D  
08  
20  
10  
20  
10  
Number of SDRAM Banks  
Supported CAS Latencies  
2, & 3  
CS Latencies  
CS latency = 0  
Write latency = 0  
non buffered/non reg.  
WE Latencies  
SDRAM DIMM Module Attributes  
SDRAM Device Attributes: General  
SDRAM Cycle Time at CL = 2  
SDRAM Access Time from Clock at CL = 2  
SDRAM Cycle Time at CL = 1  
SDRAM Access Time from Clock at CL = 1  
Minimum Row Precharge Time  
Minimum Row Active to Row Active Delay  
Minimum RAS to CAS Delay  
Minimum RAS Pulse Width  
Module Bank Density (per bank)  
SDRAM Input Setup Time  
V
DD tol +/– 10%  
10.0 ns  
6.0 ns  
not supported  
not supported  
20 ns  
16 ns  
20 ns  
45 ns  
32 MB/64 MB  
2 ns  
08  
10  
SDRAM Input Hold Time  
1 ns  
SDRAM Data Input Setup Time  
SDRAM Data Input Hold Time  
2 ns  
1 ns  
Data Book  
12  
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
SPD-Table for PC100 2-2-2 SO-DIMM Modules (cont’d)  
Byte# Description  
SPD Entry Value  
Hex  
36-61 Superset Information  
–
FF  
12  
62  
63  
SPD Revision  
Revision 1.2  
Checksum for Bytes 0 - 62  
–
DF E0  
FF  
64  
E9  
64  
64-125 Manufactures’s Information (optional)  
–
126  
Frequency Specification  
Details  
PC100  
64  
87  
127  
–
–
C7 C7  
FF  
128+  
Unused Storage Locations  
Data Book  
13  
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
SPD-Table for PC133 3-3-3 SO-DIMM Modules  
Byte# Description  
SPD Entry Value  
Hex  
0
Number of SPD Bytes  
128  
80  
08  
04  
0C  
08  
02  
40  
00  
01  
75  
54  
00  
80  
10  
00  
01  
1
Total Bytes in Serial PD  
256  
2
Memory Type  
SDRAM  
3
Number of Row Addresses (without BS)  
Number of Column Addresses  
Number of DIMM Banks  
–
4
–
08  
01  
09  
02  
5
1/2  
6
Module Data Width  
64  
7
Module Data Width (cont’d)  
Module Interface Levels  
0
8
LVTTL  
9
SDRAM Cycle Time at CL = 3  
SDRAM Access Time from Clock at CL = 3  
DIMM Config (Error Det/Corr.)  
Refresh Rate/Type  
7.5 ns  
10  
11  
12  
13  
14  
15  
5.4 ns  
none  
Self-Refresh, 15.6µs  
SDRAM Width, Primary  
x16  
Error Checking SDRAM Data Width  
Minimum Clock Delay for Back-to-Back  
Random Column Address  
n/a/x8  
t
CCD = 1 CLK  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
Burst Length Supported  
1, 2, 4, 8 & full page  
2
8F  
04  
06  
01  
01  
00  
0E  
A0  
60  
FF  
FF  
14  
0F  
14  
2D  
08  
15  
08  
15  
08  
Number of SDRAM Banks  
Supported CAS Latencies  
2, & 3  
CS Latencies  
CS latency = 0  
Write latency = 0  
non buffered/non reg.  
WE Latencies  
SDRAM DIMM Module Attributes  
SDRAM Device Attributes: General  
SDRAM Cycle Time at CL = 2  
SDRAM Access Time from Clock at CL = 2  
SDRAM Cycle Time at CL = 1  
SDRAM Access Time from Clock at CL = 1  
Minimum Row Precharge Time  
Minimum Row Active to Row Active Delay  
Minimum RAS to CAS Delay  
Minimum RAS Pulse Width  
Module Bank Density (per bank)  
SDRAM Input Setup Time  
V
DD tol +/– 10%  
10.0 ns  
6.0 ns  
not supported  
not supported  
20 ns  
14 ns  
20 ns  
45 ns  
32 MB/64 MB  
1.5 ns  
08  
10  
SDRAM Input Hold Time  
0.8 ns  
SDRAM Data Input Setup Time  
SDRAM Data Input Hold Time  
1.5 ns  
0.8 ns  
Data Book  
14  
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
SPD-Table for PC133 3-3-3 SO-DIMM Modules (cont’d)  
Byte# Description  
SPD Entry Value  
Hex  
36-61 Superset Information  
–
FF  
12  
62  
63  
SPD Revision  
Revision 1.2  
Checksum for Bytes 0 - 62  
–
81  
82  
03  
64  
64-125 Manufactures’s Information (optional)  
–
FF  
64  
126  
Frequency Specification  
Details  
PC133  
64  
87  
127  
–
–
C7 C7  
FF  
128+  
Unused Storage Locations  
Data Book  
15  
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
Package Outlines  
32 & 64 MByte SO-DIMM Module Package  
(144-pin, Dual Read-out, Single In-line Memory Module)  
67,6  
63,6  
3,8  
+0.1  
1
59 61  
143  
1.0  
-
3,3  
32.8  
23.2  
24.5  
4,6  
2,5  
3,7  
O 1,8  
60  
2
62  
144  
Detail of Contacts:  
+/- 0.05  
0,6  
0,8  
4Mx64/8Mx64 COB-SDRAM SODIMM  
DM144-C8.WMF  
Data Book  
16  
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
128 MByte SO-DIMM Module Package  
(144-pin, Dual Read-out, Single In-line Memory Module)  
67.6  
63.6  
3.8  
1
59  
61  
143  
144  
1±  
0.1  
3.3  
23.2  
24.5  
32.8  
2.5  
4.6  
±0.1  
1.5  
60  
1.8  
3.7  
2
62  
Detail of Contacts  
±0.05  
0.6  
0.8  
GLD09192  
Data Book  
17  
12.99  
HYS 64Vx20(2)0GCDL  
144-pin SO-DIMM SDRAM Modules  
Rev Changes:  
12.98  
4M x 64 version added, 128 MByte version SPD byte changed from 08h to 10h  
(x16 device), check sum adjusted.  
Capacitance values according to measurments on samples adjusted  
12.1.99  
Preliminary changed to final  
Input Capacitances adjusted  
19.3.99  
20.4.99  
128 MB block diagram clarified  
ICC6 low-power versions reduced to 400 µA * components  
Infineon logo added  
5.5.99  
21.7.99  
29.7.99  
23.8.99  
Serial resistors for clock inputs and dummy loading corrected  
Some capacitance values changes due to new measured data  
PC133 versions added  
Editorial changes made according to Mr. Lewbel findings  
PC133 Byte 126 changed to 64h  
27.8.99  
6.9.99  
Drawing for C8 optimised, old drawing may be missleading  
Template from R&L  
3.12.99  
PC133 timing parameters changed according to INTEL PC133 specification  
Data Book  
18  
12.99  
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