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DX-DI-64IP-XVE

型号：

DX-DI-64IP-XVE

描述：

周边其他\n[ Peripheral Miscellaneous ]

品牌：

ETC[ ETC ]

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0
LogiCORE PCI Interface v3.0  
0
0
DS 208 (v.1.2) June 28, 2002  
Data Sheet, v3.0.99  
Introduction  
With the Xilinx LogiCORE PCI-X Interface, a designer can  
build a customized PCI-X 1.0a-compliant core with high  
sustained performance, 800 Mbytes/sec.  
LogiCORE Facts  
1
PCI-X64 / PCI64 Resource Utilization  
Slice Four Input LUTs  
Slice Flip Flops  
IOB Flip Flops  
IOBs  
2646  
1605  
257  
Features  
90  
•
Fully PCI-X 1.0a-compliant core, 64-bit, 100/66/33  
MHz interface with 3.3 V operation  
BUFGs / DCMs  
2 / 1  
1
PCI-X64 Mode Only Resource Utilization  
Slice Four Input LUTs  
•
•
•
•
Customizable, programmable, single-chip solution  
Predefined implementation for predictable timing  
Incorporates Xilinx Smart-IP Technology  
2126  
1461  
257  
Slice Flip Flops  
IOB Flip Flops  
IOBs  
Fully verified design tested with Xilinx proprietary test-  
bench and hardware  
90  
BUFGs / DCMs  
1 / 1  
•
Available for configuration and download on the web:  
1
PCI64 Mode Only Resource Utilization  
-
-
Web-based Configuration and Download Tool  
Web-based User Constraint File Generator Tool  
Slice Four Input LUTs  
Slice Flip Flops  
IOB Flip Flops  
IOBs  
1915  
1350  
253  
•
•
Instant Access to New Releases  
Integrated extended capabilities:  
90  
-
-
-
PCI-X Capability Item  
BUFGs / DCMs  
1 / 0  
Power Management Capability Item  
Message Signalled Interrupt Capability Item  
Provided with Core  
Documentation  
PCI-X Design Guide  
PCI-X Implementation Guide  
Verilog/VHDL Simulation Model  
•
•
Supported PCI-X only functions:  
-
-
-
-
Split Completion  
Design File Formats  
Memory Read Dword  
Memory Read Block  
Memory Write Block  
NGO Netlist  
User Constraint Files (UCF)  
Verilog/VHDL Example Design  
Constraint Files  
Example Design  
Supported PCI only functions:  
Design Tool Requirements  
-
-
-
-
Memory Read  
Xilinx Tools  
v4.2i, Service Pack 3  
Synplicity Synplify  
Memory Read Multiple  
Memory Read Line  
Tested Entry and  
Verification Tools  
2
Synopsys FPGA Express  
Exemplar Leonardo Spectrum  
Memory Write and Invalidate  
3
Xilinx XST  
Cadence Verilog XL  
Model Technology ModelSim  
1. The resource utilization depends on configuration of the interface and the user  
design. Unused resources are trimmed by the Xilinx technology mapper. The uti-  
lization figures reported in this table are representative of a maximum configura-  
tion.  
2. See the implementation guide or product release notes for current supported ver-  
sions.  
3. XST is command line option only. See Implementation Guide for details.  
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other  
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea-  
ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may  
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warran-  
ties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.  
DS 208 (v.1.2) June 28, 2002  
www.xilinx.com  
1
Data Sheet, v3.0.99  
1-800-255-7778  
LogiCORE PCI Interface v3.0  
LogiCORE Facts (Cont)  
The core meets the setup, hold, and clock to timing require-  
ments as specified in the PCI-X specification. The interface  
is verified through extensive simulation.  
PCI-X 64 Supported Devices  
PCI64/33  
Only  
Virtex-E V300EBG432-8C  
Virtex-II 2V1000FG456-5C  
3.3v only  
3.3v only  
Other features that enable efficient implementation of a  
PCI-X system include:  
PCI-X64/66  
Only  
Virtex-E V300EBG432-8C  
Virtex-II 2V1000FG456-5C  
3.3v only  
3.3v only  
•
Block SelectRAM™ memory. Blocks of on-chip  
ultra-fast RAM with synchronous write and dual-port  
RAM capabilities. Used in PCI-X designs to implement  
FIFOs.  
PCI-X64/100  
Only  
Virtex-II 2V1000FG456-5C  
Virtex-II 2V1000FG456-5C  
3.3v only  
3.3v only  
PCI-X64/66  
PCI64/33  
•
SelectRAM memory. Distributed on-chip ultra-fast RAM  
with synchronous write option and dual-port RAM  
capabilities. Used in PCI-X designs to implement  
FIFOs.  
Xilinx provides technical support for this LogiCORE product when used as described  
in the Design Guide and the Implementation Guide. Xilinx cannot guarantee timing,  
functionality, or support of product if implemented in devices not listed, or if custom-  
ized beyond that allowed in the product documentation.  
Note: Fully compliant designs over 66 MHz require two bitstreams.  
Note: Universal card implementations not supported.  
Note: Commercial devices only; 0 C < Tj < 85 C.  
The interface is carefully optimized for best possible perfor-  
mance and utilization in Xilinx FPGA devices.  
More Features  
Smart-IP Technology  
•
Supported PCI and PCI-X functions:  
Drawing on the architectural advantages of Xilinx FPGAs,  
Xilinx Smart-IP technology ensures the highest perfor-  
mance, predictability, repeatability, and flexibility in PCI-X  
designs. The Smart-IP technology is incorporated in every  
LogiCORE PCI-X Interface.  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Memory Write  
I/O Read  
I/O Write  
Configuration Read  
Xilinx Smart-IP technology leverages the Xilinx architectural  
advantages, such as look-up tables and segmented routing,  
as well as floorplanning information, such as logic mapping  
and location constraints. This technology provides the best  
physical layout, predictability, and performance. Addition-  
ally, these features allow for significantly reduced compile  
times over competing architectures.  
Configuration Write  
Interrupt Acknowledge  
Bus Parking  
Type 0 Configuration Space Header  
Full 64-bit Addressing Support  
Up to 6 Base Address Registers  
Expansion ROM Base Address Register  
Instant-On Base Address Registers  
Parity Generation, Parity Error Detection  
Full Command/Status Registers  
To guarantee the critical setup, hold, minimum clock to out,  
and maximum clock to out timing, the PCI-X interface is  
delivered with Smart-IP constraint files that are unique for a  
device and package combination. These constraint files  
guide the implementation tools so that the critical paths  
always are within specification.  
Applications  
Xilinx provides Smart-IP constraint files for many device  
and package combinations. Constraint files for unsupported  
device and package combinations may be generated using  
the web-based constraint file generator.  
•
Embedded applications in networking, industrial,  
and telecommunication systems  
•
PCI-X add-in boards such as frame buffers, network  
adapters, and data acquisition boards  
Functional Description  
The LogiCORE PCI-X Interface is partitioned into six major  
blocks and a user application as shown in Figure 1.  
•
•
Hot swap CompactPCI-X boards  
Any applications that need a PCI-X interface  
General Description  
Datapath  
The LogiCORE PCI-X Interface is a preimplemented and  
fully tested module for Xilinx FPGAs. Critical paths are con-  
trolled by constraint and guide files to ensure predictable  
timing. This significantly reduces the engineering time  
required to implement the PCI-X portion of your design.  
Resources can instead be focused on your unique user  
application logic in the FPGA and on the system level  
design. As a result, LogiCORE PCI-X products minimize  
your product development time.  
There are four datapaths, in and out for both target and ini-  
tiator. To improve timing and ease of design, the four unidi-  
rectional datapaths are multiplexed inside the interface. All  
data transfers are register-to-register. Since fewer registers  
are on each datapath, loading is reduced and false timing  
paths are eliminated.  
2
www.xilinx.com  
1-800-255-7778  
DS 208 (v.1.2) June 28, 2002  
Data Sheet, v3.0.99  
LogiCORE PCI Interface v3.0  
Table 1: PCI-X Configuration Space Header  
31  
16 15  
0
Target Datapath In  
Initiator Datapath In  
targ  
init  
data path mux  
data path mux  
00h  
04h  
08h  
0Ch  
Device ID  
Status  
Vendor ID  
Command  
data path mux  
data path mux  
Target Datapath Out  
Initiator Datapath Out  
Class Code  
Rev ID  
Target Status  
Target Control  
Target  
State  
Machine  
BIST  
Header Type Latency Tim- Cache Line  
Config  
Space  
Initiator  
State  
Machine  
Initiator Control  
Initiator Status  
er  
Size  
Watchdog  
10h  
14h  
18h  
1Ch  
20h  
24h  
28h  
2Ch  
30h  
34h  
38h  
3Ch  
Base Address Register 0 (BAR0)  
Base Address Register 1 (BAR1)  
Base Address Register 2 (BAR2)  
Base Address Register 3 (BAR3)  
Base Address Register 4 (BAR5)  
Base Address Register 5 (BAR5)  
Cardbus CIS Pointer  
Target Hit  
Decode  
Figure 1: LogiCORE PCI-X Interface Block Diagram  
Decode  
When an address is broadcast on the bus, the decode mod-  
ule compares it to the base address registers for a match. If  
one occurs, the target state machine is activated.  
Subsystem ID  
Expansion ROM Base Address  
Reserved  
Reserved  
Subsystem Vendor ID  
PCI-X Configuration Space  
CapPtr  
This block provides the first 64 bytes of Type 0, version 2.3  
Configuration Space Header, and an additional 64 bytes  
reserved for extended capabilities, as shown in Table 1. The  
remaining 128 bytes of configuration space are available to  
the user for application specific registers. Together, these  
support software-driven “Plug-and Play” initialization and  
configuration. This includes information for Command, Sta-  
tus, Base Address Registers, and the extended capabilities  
required for PCI-X.  
Max Lat  
Min Gnt  
Interrupt Pin  
Interrupt  
Line  
40h  
44h  
Power Management Capa-  
bility  
NxtCap  
PM Cap  
Data  
PMCSR  
BSE  
PMCSR  
48h  
Message Control  
NxtCap  
MSI Cap  
Three extended capabilities are provided in the interface:  
4Ch  
Message Address  
Message Upper Address  
Reserved Message Data  
PCI-X Command NxtCap PCI-X Cap  
PCI-X Status  
Reserved  
Available User Configuration Space  
•
•
•
PCI-X Capability Item  
50h  
Power Management Capability Item  
Message Signalled Interrupt Capability Item  
54h  
58h  
These capability items may be linked or delinked from the  
capabilities list as required, and user functions can be inte-  
grated into the capabilities list.  
5Ch  
60h-7Fh  
80h-FFh  
Note:  
Shaded areas are not implemented and return zero.  
Watchdog  
The watchdog monitors various system conditions, includ-  
ing bus mode and bus width. This module also indicates if  
run-time reconfiguration is required for loading different bit-  
streams.  
Target State Machine  
This block controls the PCI-X and PCI interface for target  
functions. The controller is a high-performance state  
machine using one-hot encoding for maximum perfor-  
mance.  
DS 208 (v.1.2) June 28, 2002  
Data Sheet, v3.0.99  
www.xilinx.com  
1-800-255-7778  
3
LogiCORE PCI Interface v3.0  
Table 2: PCI Bus Commands  
Initiator State Machine  
CBE [3:0]  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Command  
Interrupt Acknowledge  
Special Cycle  
Initiator  
Yes  
Target  
Yes  
This block controls the PCI-X and PCI interface for initiator  
functions. The initiator control logic also uses one-hot  
encoding for maximum performance.  
Yes  
No  
I/O Read  
Yes  
Yes  
I/O Write  
Yes  
Yes  
User Interface  
Reserved  
Ignore  
Ignore  
Yes  
Ignore  
Ignore  
Yes  
The PCI-X interface provides a simplified user application  
interface which allows a user to create one design that han-  
dles both PCI-X and PCI transactions without design  
changes, and both 32-bit and 64-bit data transfers without  
external data width conversion. This eliminates the need for  
multiple designs to support PCI-X and PCI and varying bus  
widths.  
Reserved  
Memory Read1  
Memory Write  
Yes  
Yes  
Reserved  
Ignore  
Ignore  
Yes  
Ignore  
Ignore  
Yes  
Reserved  
Configuration Read  
Configuration Write  
Memory Read Multiple2  
Dual Address Cycle  
Memory Read Line2  
Memory Write Invalidate2  
Yes  
Yes  
Yes  
Yes  
This streamlined interface also simplifies the amount of  
work needed to create a user application. The user inter-  
face can be designed as either a 32-bit or 64-bit interface  
and the PCI-X interface will automatically handle data con-  
versions regardless of the width of the PCI-X or PCI bus.  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
1. This command can only be used for a single dword transfer.  
2. These commands have fixed byte enables of 0h.  
Table 3: PCI-X Bus Commands  
Interface Configuration  
CBE [3:0]  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Command  
Interrupt Acknowledge  
Special Cycle  
Initiator  
Yes  
Target  
Yes  
The LogiCORE PCI-X Interface can easily be configured to  
fit unique system requirements by using the Xilinx  
Web-based Configuration and Download Tool or by chang-  
ing the HDL configuration file. The following customization  
options, among many others, are supported by the interface  
and are described in the product design guide.  
Yes  
No  
I/O Read  
Yes  
Yes  
I/O Write  
Yes  
Yes  
Reserved  
Ignore  
Ignore  
Yes  
Ignore  
Ignore  
Yes  
Reserved  
Memory Read Dword  
Memory Write  
•
•
•
•
•
•
•
Base Address Registers (number, size, and mode)  
Expansion ROM BAR  
Yes  
Yes  
Alias to Memory Read Block  
Alias to Memory Write Block  
Configuration Read  
Configuration Write  
Split Completion  
Dual Address Cycle  
Memory Read Block  
Memory Write Block  
Yes  
Yes  
Cardbus CIS pointer  
Yes  
Yes  
Yes  
Yes  
Configuration Space Header ROM  
Interrupt Connectivity  
Yes  
Yes  
Yes  
Yes  
Extended Command Use  
Yes  
Yes  
Yes  
Yes  
Capability Configuration  
Yes  
Yes  
Burst Transfer  
Bandwidth  
The PCI-X bus derives its performance from its ability to  
support burst transfers. The performance of any PCI-X  
application depends largely on the size of the burst transfer.  
Buffers to support PCI-X burst transfer can efficiently be  
implemented using on-chip RAM resources.  
The LogiCORE PCI-X Interface supports fully compliant  
zero wait-state burst operations for both sourcing and  
receiving data. This interface supports a sustained band-  
width of up to 800 MBytes/sec. The design can be config-  
ured to take advantage of the ability of the LogiCORE PCI-X  
Interface to do very long bursts.  
Supported PCI Commands  
The flexible user application interface, combined with sup-  
port for many different PCI-X features, gives users a solu-  
tion that lends itself to use in many high-performance  
applications. The user is not locked into one DMA engine,  
hence, an optimized design that fits a specific application  
can be designed.  
Table 2 lists the PCI bus commands supported by the Logi-  
CORE PCI-X Interface, and Table 3 lists the supported  
PCI-X bus commands.  
4
www.xilinx.com  
1-800-255-7778  
DS 208 (v.1.2) June 28, 2002  
Data Sheet, v3.0.99  
LogiCORE PCI Interface v3.0  
Information on additional Xilinx LogiCORE modules is avail-  
able on the Xilinx IP Center.  
Recommended Design Experience  
The LogiCORE PCI-X Interface is pre-implemented allow-  
ing engineering focus on the unique user application func-  
Table 4: Timing Parameters, 66MHz PCI-X  
tions of  
a PCI-X design. Regardless, PCI-X is a  
Symbol  
Tcyc  
Parameter  
CLK Cycle Time  
Min  
151  
6
Max  
20  
-
high-performance design that is challenging to implement in  
any technology. Therefore, previous experience with build-  
ing high-performance, pipelined FPGA designs using Xilinx  
implementation software, constraint files, and guide files is  
recommended. The challenge to implement a complete  
PCI-X design including user application functions varies  
depending on configuration and functionality of your appli-  
cation. Contact your local Xilinx representative for a closer  
review and estimation for your specific requirements.  
Thigh  
Tlow  
CLK High Time  
CLK Low Time  
6
0.72  
-
CLK to Signal Valid Delay  
(bussed signals)  
3.82  
Tval  
CLK to Signal Valid Delay  
(point to point signals)  
0.72  
3.82  
Tval  
Float to Active Delay  
Active to Float Delay  
02  
-
1.72  
-
72  
-
Ton  
Toff  
Tsu  
Input Setup Time to CLK  
(bussed signals)  
Timing Specifications  
Tsu  
Input Setup Time to CLK  
(point to point signals)  
1.72  
-
The maximum speed at which your user design is capable  
of running can be affected by the size and quality of the  
design. The following tables show the key timing parame-  
ters for the LogiCORE PCI-X Interface. Timing Parameters  
in the 66MHz PCI-x are listed in Tab le 4. Timing Parameters  
in the 33MHz PCI are listed in Table 5.  
Th  
Input Hold Time from CLK  
Reset Active to Output Float  
0.52  
-
-
Trstoff  
40  
Notes:  
1. Controlled by timespec constraints, included in product.  
2. Controlled by SelectIO configured for PCIX.  
3. Operation at 100 MHz requires Tsu of 1.2 and Tcyc of 10.  
Table 5: Timing Parameters, 33MHz PCI  
Ordering Information  
Symbol  
Tcyc  
Parameter  
CLK Cycle Time  
Min  
301  
11  
Max  
-
-
This core may be downloaded from the Xilinx IP Center for  
use with the Xilinx CORE Generator System V4.1 and later.  
The Xilinx CORE Generator System tool is bundled with all  
Alliance and Foundation Series Software packages, at no  
additional charge.  
Thigh  
Tlow  
CLK High Time  
CLK Low Time  
11  
22  
-
CLK to Signal Valid Delay  
(bussed signals)  
112  
Tval  
CLK to Signal Valid Delay  
(point to point signals)  
22  
112  
Tval  
Part Numbers  
Float to Active Delay  
Active to Float Delay  
22  
-
72  
-
281  
-
Ton  
Toff  
Tsu  
DO-DI-PCIX64-VE  
Input Setup Time to CLK  
(bussed signals)  
-PCI-X 64-bit 66/100 MHz IP only Core  
DX-DI-64IP-XVE  
Input Setup Time to CLK  
(point to point signals)  
102  
-
Tsu  
- Upgrade from  
DO-DI-PCI64/DO-DI-PCI-AL/DO-DI-PCI64DK to  
DO-DI-PCIX64-VE  
02  
-
-
Th  
Input Hold Time from CLK  
Reset Active to Output Float  
Trstoff  
40  
Notes:  
1. Controlled by timespec constraints, included in product.  
2. Controlled by SelectIO configured for PCI33_3 or PCIX.  
To order Xilinx’s PCI Core, please visit the Xilinx Silicon  
Xpresso Cafe or contact your local Xilinx sales representa-  
tive.  
Revision History  
The following table shows the revision history for this document.  
Date  
Version  
Revision  
06/28/02  
1.0  
New template  
DS 208 (v.1.2) June 28, 2002  
Data Sheet, v3.0.99  
www.xilinx.com  
1-800-255-7778  
5
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