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HYS72V32301GR-7.5-C2

型号：

HYS72V32301GR-7.5-C2

品牌：

ETC[ ETC ]

页数：

23 页

PDF大小：

352 K

下载PDF手册
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
3.3 V 168-pin Registered SDRAM Modules  
PC133 128 MByte Module  
PC133 256 MByte module  
PC133 512 MByte Module  
PC133 1 GByte Module  
PC133 2 GByte Module  
•
168-pin Registered 8 Byte Dual-In-Line  
SDRAM Module for PC and Server main  
memory applications  
•
Programmable CAS Latency, Burst Length,  
and Wrap Sequence (Sequential &  
Interleave)  
•
One bank 16M × 72, 32M x 72, 64M × 72and  
128M x 72, two bank 128M × 72 and  
256M x 72 organization  
•
•
•
All inputs and outputs are LVTTL compatible  
Serial Presence Detect with E2PROM  
Utilizes SDRAMs in TSOPII-54 packages  
with registers and PLL.  
•
•
Optimized for ECC applications with very low  
input capacitances  
•
•
Card Size: 133.35 mm × 38.10 / 43.18 mm  
with Gold contact pads and max. 4.00 / 6.80  
mm thickness (JEDEC MO-161)  
JEDEC standard Synchronous DRAMs  
(SDRAM) Programmable CAS Latency, Burst  
Length and Wrap Sequence (Sequential &  
Interleave)  
These modules all fully compatible with the  
current industry standard PC133 and PC100  
specifications  
•
•
Single + 3.3 V (± 0.3 V) power supply  
Auto Refresh (CBR) and Self Refresh  
•
Performance:  
speed grade  
-7  
-7.5  
133  
7.5  
5.4  
100  
10  
Unit  
MHz  
ns  
fCK  
tCK  
tAC  
fCK  
tCK  
tAC  
Clock Frequency (max.) @ CL = 3  
Clock Cycle Time (min.) @ CL = 3  
Clock Access Time (min.) @ CL= 3  
Clock Frequency (max.) @ CL = 2  
Clock Cycle Time (min.) @ CL = 2  
Clock Access Time (min.) @ CL= 2  
133  
7.5  
5.4  
133  
7.5  
5.4  
ns  
MHz  
ns  
6
ns  
Description  
The HYS 72Vxx3xxGR-7 and -7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs)  
organized as 16M × 72, 32M x 72, 64M × 72, 128M × 72 and 256M x 72 high speed memory arrays designed with  
Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM  
and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces capacitive  
loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors  
are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial  
E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second  
128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte  
interface in a 133.35 mm long footprint.  
INFINEON Technologies  
1
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Ordering Information  
Partnumber 1)  
Compliance  
Code 2)  
Description  
SDRAM  
Technology  
PC133-333:  
HYS 72V16300GR-7.5-C  
HYS 72V16300GR-7.5-E  
PC133R-333-542-B2 one bank 128 MB Reg. DIMM  
64 MBit (x4)  
HYS 72V16301GR-7.5-C2  
HYS 72V32301GR-7.5-C2  
PC133R-333-542-B2 one bank 128 MB Reg. DIMM  
PC133R-333-542-B2 one bank 256 MB Reg. DIMM  
PC133R-333-542-AA one bank 256 MB Reg. DIMM  
128 MBit (x8)  
128 Mbit (x4)  
256 Mbit (x8)  
HYS 72V32300GR-7.5-C2  
HYS 72V32300GR-7.5-D  
HYS 72V64300GR-7.5-C2  
HYS 72V64300GR-7.5-D  
PC133R-333-542-B2 one bank 512 MB Reg. DIMM  
256 MBit (x4)  
HYS 72V128320/1GR-7.5-C2 PC133R-333-542-B2 two banks 1 GByte Reg. DIMM  
HYS 72V128320/1GR-7.5-D  
256 MBit  
(x4, stacked) 3)  
HYS 72V128300GR-7.5-A  
PC133R-333-542-B2 one bank 1 GByte Reg. DIMM  
512 MBit (x4)  
HYS 72V256320/1GR-7.5-A PC133R-333-542-B2 two banks 2 GByte Reg. DIMM  
512 MBit  
(x4, stacked) 3)  
PC133-222:  
HYS 72V16300GR-7-E  
HYS 72V16301GR-7-C2  
HYS 72V32301GR-7-C2  
HYS 72V32300GR-7-D  
HYS 72V64300GR-7-D  
HYS 72V128320/1GR-7-D  
PC133R-222-542-B2 one bank 128 MB Reg. DIMM  
PC133R-222-542-B2 one bank 128 MB Reg. DIMM  
PC133R-222-542-B2 one bank 256 MB Reg. DIMM  
PC133R-222-542-AA one bank 256 MB Reg. DIMM  
PC133R-222-542-B2 one bank 512 MB Reg. DIMM  
PC133R-222-542-B2 two banks 1 GByte Reg. DIMM  
64 MBit (x4)  
128 MBit (x8)  
128 Mbit (x4)  
256 Mbit (x8)  
256 MBit (x4)  
256 MBit  
(x4, stacked) 3)  
HYS 72V128300GR-7-A  
HYS 72V256320/1GR-7-A  
PC133R-222-542-B2 one bank 1 GByte Reg. DIMM  
PC133R-222-542-B2 two banks 2 GByte Reg. DIMM  
512 MBit (x4)  
512 MBit  
(x4, stacked) 3)  
Notes:  
1.) All part numbers end with a place code, designating the die revision of the components used on the  
Registered DIMM module. Consult factory for current revision. Example: HYS 64V32300GR-7.5-D,  
indicating Rev.D dies are used for 256Mbit SDRAM components.  
2.) The Compliance Code is printed on the modules labels and describes speed sort of the modules,  
latencies, access time from clock,SPD revision and Raw Card version acording to the actual JEDEC  
standard.  
3.) Modules with stacked components are available in two version, with components stacked using a  
soldering stacking technique (f.e. HYS72V128320GR-7.5 ) and an welding technique developed by  
INFINEON Technologies (f.e. HYS72V128321GR-7.5)  
.
INFINEON Technologies  
2
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Pin Definitions and Functions  
A0 - A11, A12  
Address Inputs (A12 is used for  
256Mbit based modules only)  
DQMB0 - DQMB7  
Data Mask  
Chip Select  
BA0, BA1  
Bank Selects  
CS0 - CS3  
REGE*)  
DQ0 - DQ63  
Data Input/Output  
Register Enable  
“H” or N.C = registered mode  
“L” = buffered mode  
CB0 - CB7  
RAS  
Check Bits  
VDD  
VSS  
SCL  
SDA  
N.C.  
–
Power (+ 3.3 V)  
Ground  
Row Address Strobe  
Column Address Strobe  
Read/Write Input  
Clock Enable  
CAS  
Clock for Presence Detect  
Serial Data Out  
No Connection  
–
WE  
CKE0  
CLK0 - CLK3  
Clock Input  
Note : *) To confirm to this specification, motherboards must pull this pin to high state or no connect.  
Address Format  
Density Organization Memory SDRAMs # of  
# of row/bank/ Refresh Period Interval  
Banks  
SDRAMs columns bits  
128 MB 16M × 72  
128 MB 16M × 72  
256 MB 32M x 72  
256 MB 32M x 72  
512 MB 64M × 72  
1
1
1
1
1
2
1
2
16M × 4  
16M x 8  
32M x 4  
32M x 8  
64M × 4  
64M × 4  
18  
9
12/2/10  
12/2/10  
12/2/11  
13/2/10  
13/2/11  
13/2/11  
13/2/12  
13/2/12  
4k  
4k  
4k  
8k  
8k  
8k  
8k  
8k  
64 ms 15.6 µs  
64 ms 15.6 µs  
64 ms 15.6 µs  
64 ms 7.8 µs  
64 ms 7.8 µs  
64 ms 7.8 µs  
64ms 7.8 µs  
64ms 7.8 µs  
18  
9
18  
36  
1 GB  
1 GB  
2 GB  
128M × 72  
128M × 72  
256M × 72  
128M × 4 18  
128M × 4 36  
INFINEON Technologies  
3
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Pin Configuration  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
PIN# Symbol  
1
2
3
4
5
6
7
8
VSS  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
VSS  
DU  
CS2  
DQMB2  
DQMB3  
DU  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
VSS  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
VSS  
CKE0  
CS3  
DQMB6  
DQMB7  
N.C.  
VDD  
N.C.  
N.C.  
CB6  
DQ0  
DQ1  
DQ2  
DQ3  
VDD  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VSS  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
VDD  
DQ14  
DQ15  
CB0  
CB1  
VSS  
DQ32  
DQ33  
DQ34  
DQ35  
VDD  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VSS  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
VDD  
DQ46  
DQ47  
CB4  
VDD  
N.C.  
N.C.  
CB2  
CB3  
VSS  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
CB7  
VSS  
DQ16  
DQ17  
DQ18  
DQ19  
VDD  
DQ20  
N.C.  
DU  
N.C.  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ24  
DQ25  
DQ26  
DQ27  
VDD  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
DQ48  
DQ49  
DQ50  
DQ51  
VDD  
DQ52  
N.C.  
DU  
REGE  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
DQ56  
DQ57  
DQ58  
DQ59  
VDD  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
CB5  
VSS  
N.C.  
N.C.  
VDD  
N.C.  
N.C.  
VDD  
CAS  
DQMB4  
DQMB5  
CS1  
RAS  
VSS  
A1  
A3  
A5  
A7  
A9  
BA0  
A11  
VDD  
CLK1  
WE  
DQMB0  
DQMB1  
CS0  
DU  
VSS  
A0  
A2  
A4  
A6  
A8  
A10 (AP)  
BA1  
VDD  
VDD  
CLK0  
CLK2  
N.C.  
WP  
SDA  
SCL  
CLK3  
N.C.  
SA0  
SA1  
SA2  
VDD  
VDD  
A12  
INFINEON Technologies  
4
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
RCS0  
RDQMB0  
RDQMB4  
DQM  
CS  
DQM  
CS  
DQ0-DQ3  
DQ4-DQ7  
DQ32-DQ35  
DQ0-DQ3  
DQ0-DQ3  
D0  
D8  
DQM  
CS  
DQM  
CS  
DQ36-DQ39  
DQ0-DQ3  
DQ0-DQ3  
D1  
D9  
RDQMB1  
RDQMB5  
DQM  
DQM  
CS  
DQ8-DQ11  
DQ40-DQ43  
DQ0-DQ3  
DQ0-DQ3  
D2  
D3  
D10  
DQM  
CS  
DQ0-DQ3  
DQM  
CS  
DQ12-DQ15  
CB0-CB3  
DQ44-DQ47  
CB4-CB7  
DQ0-DQ3  
D11  
DQM  
CS  
DQM  
CS  
DQ0-DQ3  
D17  
DQ0-DQ3  
D16  
RCS2  
RDQMB2  
RDQMB6  
DQM  
DQ0-DQ3  
CS  
DQM  
DQ0-DQ3  
D12  
CS  
DQ16-DQ19  
DQ20-DQ23  
DQ48-DQ51  
D4  
DQM  
CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D13  
CS  
DQ52-DQ55  
D5  
RDQMB3  
RDQMB7  
DQM  
CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D14  
CS  
DQ24-DQ27  
DQ56-DQ59  
D6  
DQM  
CS  
DQ0-DQ3  
DQM  
CS  
DQ0-DQ3  
D15  
DQ28-DQ31  
DQ60-DQ63  
D7  
E2PROM  
(256 word x 8 Bit)  
CLK0  
12 pF  
PLL  
SDRAMs D0-D17  
CLK1, CLK2, CLK3  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
SA2  
SCL  
12 pF  
CS0/CS2  
DQMB0-7  
BA0, BA1  
A0-A11, A12  
RAS  
CAS  
CKE0  
WE  
RCS0/RCS2  
WP  
RDQMB0-7  
RBA0, RBA1  
RA0-RA11, RA12  
RRAS  
RCAS  
RCKE0  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
SDRAMs D0-D17  
47 kΩ  
VCC  
VSS  
D0-D17, Reg., DLL  
D0-D17, Reg., DLL  
C
RWE  
REGE  
1) DQ wirding may differ from that decribed  
in this drawing; however DQ/DQB relationship  
must be maintained as shown  
10 kΩ  
VCC  
2) All resistors are 10 Ω unless otherwise noted  
SPB04135  
Block Diagram: One Bank 16M x 72, 32M x 72, 64M x 72 and 128M x 72 SDRAM DIMM Modules  
HYS72V16300GR, HYS72V32301GR, HYS72V64300GR and HYS72V128320GR  
using x4 organized SDRAMs  
INFINEON Technologies  
5
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
RCS0  
CS  
DQM  
CS  
DQM  
RDQMB0  
DQ0-DQ7  
RDQMB4  
DQ32-DQ39  
DQ0-DQ7  
DQ0-DQ7  
D0  
D4  
CS  
DQM  
CS  
DQM  
RDQMB1  
RDQMB5  
DQ8-DQ15  
DQ40-DQ47  
DQ0-DQ7  
DQ0-DQ7  
D1  
D5  
CS WE  
DQM  
CB0- CB7  
RCS2  
DQ0-DQ7  
D8  
CS  
DQM  
CS  
DQM  
RDQMB2  
RDQMB4  
DQ16-DQ23  
DQ48-DQ55  
DQ0-DQ7  
DQ0-DQ7  
D2  
D6  
CS  
DQM  
CS  
DQM  
RDQMB3  
RDQMB7  
DQ24-DQ31  
DQ56-DQ63  
DQ0-DQ7  
DQ0-DQ7  
D3  
D7  
E2PROM  
(256 word x 8 Bit)  
VCC  
VSS  
D0-D8, Reg., DLL  
D0-D8, Reg., DLL  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
C
SA2  
SCL  
WP  
Ω
47 k  
CLK0  
12 pF  
PLL  
SDRAMs D0-D8  
Notes:  
1)  
DQ wirding may differ from that  
decribed in this drawing;  
however DQ/DQB relationship  
must be maintained as shown  
CS0/CS2  
DQMB0-7  
BA0, BA1  
A0-A11,12*)  
RAS  
CAS  
CKE0  
WE  
RCS0/RCS2  
RDQMB0-7  
RBA0, RBA1  
RA0-11,12  
RRAS  
RCAS  
RCKE0  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
SDRAMs D0-D8  
2)  
Ω
All resistors are 10 unless  
otherwise noted  
*) A12 is only for 32 M x 72  
organisation  
RWE  
CLK1, CLK2, CLK3  
REGE  
12 pF  
Ω
10 k  
VCC  
SPB04130-2  
Block Diagram: One Bank 16M x72 and 32M x 72 Modules  
HYS72V16301 & HYS72V32300GR using x8 organized SDRAMs  
INFINEON Technologies  
6
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
RCS0  
RCS1  
RDQMB0  
RDQMB4  
DQM  
CS DQM  
CS  
DQM CS  
DQ0-DQ3  
DQM  
CS  
DQ0-DQ3  
DQ0-DQ3  
DQ4-DQ7  
DQ32-DQ35  
DQ0-DQ3  
DQ0-DQ3  
D0  
D0  
CS  
D8  
D8  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
CS  
DQ36-DQ39  
D1  
D1  
D9  
D9  
RDQMB1  
RDQMB5  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
CS  
DQ8-DQ11  
DQ40-DQ43  
D2  
D2  
D10  
D10  
DQM  
CS DQM  
DQ0-DQ3 DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
CS  
DQ0-DQ3  
DQ12-DQ15  
CB0-CB3  
DQ44-DQ47  
CB4-CB7  
D3  
D3  
D11  
D11  
DQM  
CS DQM  
DQ0-DQ3 DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D17  
CS  
D16  
D16  
D17  
RCS2  
RCS3  
RDQMB2  
RDQMB6  
DQM  
DQ0-DQ3  
CS DQM  
CS  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D12  
CS  
DQ16-DQ19  
DQ48-DQ51  
DQ0-DQ3  
D4  
D4  
D12  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
CS  
DQ0-DQ3  
D13  
DQ20-DQ23  
DQ52-DQ55  
D5  
D5  
D13  
RDQMB3  
RDQMB7  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
D14  
CS  
DQ24-DQ27  
DQ56-DQ59  
D6  
D6  
D14  
DQM  
DQ0-DQ3  
CS DQM  
DQ0-DQ3  
CS  
DQM CS  
DQ0-DQ3  
DQM  
DQ0-DQ3  
CS  
DQ28-DQ31  
DQ61-DQ63  
D7  
D7  
D15  
D15  
E2PROM  
(256 word x 8 Bit)  
CLK0  
12 pF  
PLL  
Stacked SDRAMs D0-D17  
CLK1, CLK2, CLK3  
SA0  
SA1  
SA2  
SCL  
SA0  
SA1 SDA  
SA2  
SCL  
12 pF  
CS0-CS3  
DQMB0-7  
BA0, BA1  
A0-A11, A12* )  
RAS  
CAS  
CKE0  
WE  
RCS0-RCS3  
WP  
RDQMB0-7  
RBA0, RBA1  
RA0-RA11  
RRAS  
RCAS  
RCKE0  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
Stacked SDRAMs D0-D17  
47 k  
Ω
VCC  
VSS  
D0-D17, Reg. DLL  
D0-D17, Reg. DLL  
C
RWE  
REGE  
1.) DQ wirding may differ from that decribed  
*) A12 is only used for  
128 M x 72 organisation  
10 k  
Ω
in this drawing; however DQ/DQB relationship  
must be maintained as shown  
VCC  
2.) All resistors are 10  
Ω
unless otherwise noted  
SPB04136  
Block Diagram: Two Bank 128M x 72 and 256M x 72 SDRAM DIMM Modules  
HYS 72V128320GR and HYS72V256320GR Using Stacked x4 Organized SDRAMs  
INFINEON Technologies  
7
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Absolute Maximum Ratings  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
VIN, VOUT – 1.0  
Input / Output voltage relative to VSS  
Power supply voltage on VDD  
V
4.6  
VDD  
TSTG  
PD  
– 1.0  
4.6  
+150  
1
V
Storage temperature range  
-55  
–
oC  
W
mA  
Power dissipation (per SDRAM component)  
Data out current (short circuit)  
IOS  
–
50  
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.  
Functional operation should be restricted to recommended operation conditions.  
Exposure to higher than recommended voltage for extended periods of time affect device reliability  
DC Characteristics  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V  
Parameter  
Symbol  
Limit Values  
max.  
Unit  
min.  
2.0  
Input High Voltage  
VIH  
VIL  
V
DD + 0.3  
V
Input Low Voltage  
– 0.5  
2.4  
0.8  
–
V
Output High Voltage (IOUT = – 4.0 mA)  
Output Low Voltage (IOUT = 4.0 mA)  
VOH  
VOL  
II(L)  
V
–
0.4  
10  
V
Input Leakage Current, any input  
– 10  
µA  
(0 V < VIN < 3.6 V, all other inputs = 0 V)  
Output Leakage Current  
IO(L)  
– 10  
10  
µA  
(DQ is disabled, 0 V < VOUT < VDD  
)
Capacitance  
TA = 0 to 70 °C 1); VDD = 3.3 V ± 0.3 V, f = 1 MHz  
Parameter  
Symbol  
Limit Values  
Unit  
One Bank Two Bank  
Modules Modules  
Input Capacitance  
CIN  
10  
20  
pF  
(all inputs except CLK and CKE)  
Input Capacitance (CLK)  
Input Capacitance (CKE)  
CCLK  
CCKE  
CIO  
30  
17  
10  
8
30  
30  
17  
8
pF  
pF  
pF  
pF  
pF  
Input/Output Capacitance(DQ0 - DQ63, CB0 - CB7)  
Input Capacitance (SCL, SA0 - 2)  
CSC  
CSD  
Input/Output Capacitance (SDA)  
8
8
INFINEON Technologies  
8
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Operating Currents per SDRAM Component  
TA = 0 to 70 °C 1), VDD = 3.3 V ± 0.3 V  
Parameter  
Test Condition Symbol 64  
128 256 512 Unit Note  
Mb Mb Mb Mb  
max.  
2)  
Operating current  
RC = tRC(MIN.), tCK = tCK(MIN.)  
–
t
110 160 270 tbd. mA  
ICC1  
Outputs open, Burst Length = 4,  
CL = 3. All banks operated in  
random access, all banks  
operated in ping-pong manner  
to maximize gapless data  
access  
2)  
2)  
Precharge stand-by current  
in Power Down Mode  
t
CK = min.  
ICC2P  
2
1.5  
40  
2
tbd. mA  
tbd. mA  
CS = VIH(MIN.), CKE ≤ VIL(MAX.)  
Precharge Stand-by Current  
in Non-Power Down Mode  
tCK = min.  
ICC2N  
40  
25  
CS = VIH (MIN.), CKE ≥ VIH(MIN.)  
2)  
2)  
No operating current  
CKE ≥ VIH(MIN.) ICC3N  
CKE ≤ VIL(MAX.) ICC3P  
50  
8
50  
10  
50  
10  
tbd. mA  
tbd. mA  
tCK = min., CS = VIH(MIN.),  
active state (max. 4 banks)  
2), 3)  
Burst operating current  
–
–
–
ICC4  
ICC5  
ICC6  
tCK = min.,  
70  
100 170 tbd. mA  
Read command cycling  
2)  
Auto refresh current  
140 230 240 tbd. mA  
tCK = min.,  
Auto Refresh command cycling  
2)  
Self refresh current  
1
1.5 2.5 tbd. mA  
Self Refresh Mode,CKE = 0.2 V  
INFINEON Technologies  
9
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
4), 5)  
AC Characteristics (SDRAM Device Specification)  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-7  
PC133-222  
-7.5  
PC133-333  
min.  
max.  
min.  
max.  
Clock and Access Time  
Clock Cycle Time  
tCK  
fCK  
tAC  
–
CAS Latency = 3  
CAS Latency = 2  
7.5  
7.5  
–
–
7.5  
10  
–
–
ns  
ns  
Clock Frequency  
–
MHz  
CAS Latency = 3  
CAS Latency = 2  
–
–
133  
133  
–
–
133  
100  
MHz  
Access Time from Clock  
CAS Latency = 3  
CAS Latency = 2  
–
–
–
5.4  
5.4  
–
–
5.4  
6
ns  
ns  
Clock High Pulse Width  
tCH  
tCL  
tT  
2.5  
2.5  
0.5  
–
2.5  
2.5  
0.5  
–
ns  
ns  
ns  
–
–
–
Clock Low Pulse Width  
Transition Time  
–
–
7.5  
10  
Setup and Hold Parameters  
Input Setup Time  
tIS  
1.5  
0.8  
–
–
–
1
–
–
1.5  
0.8  
–
–
–
1
–
–
ns  
–
–
–
–
–
Input Hold Time  
tIH  
ns  
Power Down Mode Entry Time  
Power Down Mode Exit Setup Time  
Mode Register Setup Time  
tSB  
tPDE  
tRCS  
CLK  
CLK  
CLK  
1
1
2
2
Common Parameters  
Row to Column Delay Time  
Row Precharge Time  
Row Active Time  
tRCD  
tRP  
tRAS  
tRC  
15  
15  
37  
60  
2
–
–
–
–
–
20  
20  
45  
67.5  
2
–
ns  
–
–
–
–
–
–
ns  
100k  
ns  
Row Cycle Time  
–
–
ns  
Activate (a) to Activate (b) Command tRRD  
CLK  
Period  
CAS(a) to CAS(b) Command Period  
tCCD  
1
–
1
–
CLK  
–
INFINEON Technologies  
10  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
AC Characteristics (SDRAM Device Specification) (cont’d) 4), 5)  
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns  
Parameter  
Symbol  
Limit Values  
Unit Note  
-7  
PC133-222  
-7.5  
PC133-333  
min.  
max.  
min.  
max.  
Refresh Cycle  
Refresh Period  
64&128MBit SDRAM Based Modules  
256&512MBit SDRAM Based Modules  
tREF  
–
µs  
µs  
–
–
15.6  
7.8  
–
–
15.6  
7.8  
6)  
Self Refresh Exit Time  
tSREX  
1
–
1
–
CLK  
Read Cycle  
Data Out Hold Time  
tOH  
tLZ  
3
0
3
–
–
–
7
2
3
0
3
–
–
–
7
2
ns  
–
7)  
Data Out to Low Impedance Time  
Data Out to High Impedance Time  
DQM Data Out Disable Latency  
ns  
7)  
tHZ  
ns  
tDQZ  
CLK  
–
Write Cycle  
Data Input to Precharge  
(write recovery)  
tWR  
2
0
–
–
2
0
–
–
CLK  
CLK  
–
–
DQM Write Mask Latency  
tDQW  
INFINEON Technologies  
11  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Notes  
1. The registered DIMM modules are designed to operate under system operating conditions  
between 0-55 deg C ambient, maximum sustained bandwidth and 0 LFM airflow. Operating at  
higher ambient temperatures needs sufficient air flow to limit the case temperature of the  
SDRAM components do not exceed 85oC.  
2. These parameters depend on the cycle rate. All values are measured at 133 MHz operation  
frequency. Input signals are changed once during tck excepts for Icc6 and for standby currents  
when tck = infinity.  
3. These parameters are measured with continous data stream during read access and all DQ  
toggling. CL=3 and BL=4 is assumed and the data-out current is excluded.  
4. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must  
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation  
can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize (tSTAB) before  
any operation can be guaranteed.  
5. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.4 V crossover  
point. The transition time is measured between VIH and VIL. All AC measurements assume  
tT = 1 ns with the AC output load circuit shown. Specified tAC and tOH parameters are measured  
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate  
between 0.8 V and 2.0 V.  
6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after  
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied  
after the Self Refresh Exit command is registered.  
7. Referenced to the time at which the output achieves the open circuit condition, not to output  
voltage levels.  
tCH  
2.4 V  
0.4 V  
1.4 V  
CLOCK  
tT  
tCL  
tIH  
tIS  
INPUT  
1.4 V  
tAC  
tAC  
tLZ  
tOH  
I/O  
OUTPUT  
1.4 V  
50 pF  
tHZ  
Measurement conditions for  
AC and tOH  
t
IO.vsd  
Serial Presence Detect  
A serial presence detect storage device - E2PROM 34C02 - is assembled onto the module.  
Information about the module configuration, speed, etc. is written into the E2PROM device during  
module production using a serial presence detect protocol (I2C synchronous 2-wire bus).The first  
128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end  
user.  
INFINEON Technologies  
12  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
SPD-Table for -7.5 Registered DIMM Modules  
Hex  
Byte# Description  
SPD  
Entry  
Value  
Number of SPD Bytes  
128  
80  
08  
04  
0
Total Bytes in Serial PD  
Memory Type  
256  
1
SDRAM  
12/13  
10/11/12  
1/2  
2
Number of Row Addresses  
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
0C  
0A  
01  
0C  
0A  
01  
0C  
0B  
01  
0D  
0A  
01  
0D  
0B  
01  
0D  
0B  
02  
0D  
0C  
01  
0D  
0C  
02  
3
4
5
6
72  
48  
00  
01  
75  
54  
02  
Module Data Width (cont’d)  
Module Interface Levels  
Cycle Time at CL = 3  
0
7
LVTTL  
7.5 ns  
8
9
Access Time from Clock at CL = 3 5.4 ns  
10  
11  
12  
13  
14  
DIMM Config (Error Det/Corr.)  
Refresh Rate/Type  
ECC  
15.6/7.8 µs  
x4 / x8  
x4 / x8  
80  
04  
04  
80  
08  
08  
80  
04  
04  
82  
08  
08  
82  
04  
04  
82  
04  
04  
82  
04  
04  
82  
04  
04  
SDRAM Width, Primary  
Error Checking SDRAM Data  
Width  
Minimum tCCD  
1 CLK  
01  
15  
16  
Burst Length Supported  
1, 2, 4, 8 & 8F  
(full page)  
0F  
0F  
0F  
0F  
0F  
0F  
0F  
Number of SDRAM Banks  
4
04  
06  
01  
01  
1F  
0E  
17  
18  
19  
20  
21  
22  
SDRAM Supported CAS Latencies 2 & 3  
SDRAM CS Latencies  
0
SDRAM WE Latencies  
0
SDRAM DIMM Module Attributes  
SDRAM Device Attributes  
with PLL  
VDD tol +/–  
10%  
Min. Clock Cycle Time at CL = 2  
10 ns  
A0  
60  
23  
24  
Max. Data Access Time from Clock 6.0 ns  
for CL = 2  
Min. Clock Cycle Time at CL = 1  
not  
supported  
00  
00  
25  
26  
Max. Data Access Time from Clock not supp.  
at CL = 1  
SDRAM Minimum tRP  
SDRAM Minimum tRRD  
SDRAM Minimum tRCD  
SDRAM Minimum tRAS  
20 ns  
15 ns  
20 ns  
45 ns  
14  
0F  
14  
2D  
27  
28  
29  
30  
INFINEON Technologies  
13  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
SPD-Table for -7.5 Registered DIMM Modules (cont’d)  
Hex  
Byte# Description  
SPD  
Entry  
Value  
Module Bank Density (per bank)  
128 MByte  
256 Mbyte  
512 MByte  
1 GByte  
20  
20  
40  
40  
80  
80  
01  
01  
31  
SDRAM Input Setup Time  
SDRAM Input Hold Time  
1.5 ns  
0.8 ns  
1.5 ns  
0.8 ns  
–
15  
08  
15  
08  
00  
32  
33  
SDRAM Data Input Setup Time  
SDRAM Data Input Hold Time  
34  
35  
36-61  
Superset Information  
(may be used in future)  
SPD Revision  
JEDEC 2  
12  
62  
Checksum for Bytes 0 - 62  
Manufacturer’s Information  
Frequency Specification  
Details of Clocks  
–
–
–
–
–
D8  
60  
79  
83  
BC  
BD  
3E  
3F  
63  
64-125  
126  
127  
128+  
64  
8F  
FF  
Unused Storage Locations  
1) HYS72V16300GR-7.5  
2) HYS72V16301GR-7.5  
3) HYS72V32301GR-7.5  
4) HYS72V32300GR-7.5  
INFINEON Technologies  
14  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
SPD-Table for -7 Registered DIMM Modules  
Hex  
Byte# Description  
SPD  
Entry  
Value  
Number of SPD Bytes  
128  
80  
08  
04  
0
1
Total Bytes in Serial PD  
Memory Type  
256  
SDRAM  
12/13  
10/11/12  
1/2  
2
Number of Row Addresses  
Number of Column Addresses  
Number of DIMM Banks  
Module Data Width  
0C  
0A  
01  
0C  
0A  
01  
0C  
0B  
01  
0D  
0A  
01  
0D  
0B  
01  
0D  
0B  
02  
0D  
0C  
01  
0D  
0C  
02  
3
4
5
72  
48  
00  
01  
75  
54  
02  
6
7
Module Data Width (cont’d)  
Module Interface Levels  
Cycle Time at CL = 3  
0
LVTTL  
7.5 ns  
8
9
Access Time from Clock at CL = 3 5.4 ns  
10  
11  
12  
13  
14  
DIMM Config (Error Det/Corr.)  
Refresh Rate/Type  
ECC  
15.6/7.8 µs  
x4 / x8  
x4 / x8  
80  
04  
04  
80  
08  
08  
80  
04  
04  
82  
08  
08  
82  
04  
04  
82  
04  
04  
82  
04  
04  
82  
04  
04  
SDRAM Width, Primary  
Error Checking SDRAM Data  
Width  
Minimum tCCD  
1 CLK  
01  
15  
16  
Burst Length Supported  
1, 2, 4, 8 &  
(full page)  
8F  
0F  
0F  
0F  
0F  
0F  
0F  
0F  
Number of SDRAM Banks  
4
04  
06  
01  
01  
1F  
0E  
17  
18  
19  
20  
21  
22  
SDRAM Supported CAS Latencies 2 & 3  
SDRAM CS Latencies  
0
SDRAM WE Latencies  
0
SDRAM DIMM Module Attributes  
SDRAM Device Attributes  
with PLL  
VDD tol +/–  
10%  
Min. Clock Cycle Time at CL = 2  
7.5 ns  
75  
54  
23  
24  
Max. Data Access Time from Clock 5.6 ns  
for CL = 2  
Min. Clock Cycle Time at CL = 1  
not  
supported  
00  
00  
25  
26  
Max. Data Access Time from Clock not supp.  
at CL = 1  
SDRAM Minimum tRP  
SDRAM Minimum tRRD  
SDRAM Minimum tRCD  
SDRAM Minimum tRAS  
15 ns  
14 ns  
15 ns  
37 ns  
0F  
0E  
0F  
25  
27  
28  
29  
30  
INFINEON Technologies  
15  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Hex  
Byte# Description  
SPD  
Entry  
Value  
Module Bank Density (per bank)  
128 MByte  
256 Mbyte  
512 MByte  
1024 MByte  
20  
20  
40  
40  
80  
80  
01  
01  
31  
SDRAM Input Setup Time  
SDRAM Input Hold Time  
1.5 ns  
0.8 ns  
1.5 ns  
0.8 ns  
–
15  
08  
15  
08  
00  
32  
33  
SDRAM Data Input Setup Time  
SDRAM Data Input Hold Time  
34  
35  
Superset Information  
(may be used in future)  
36-61  
SPD Revision  
JEDEC 2  
12  
62  
Checksum for Bytes 0 - 62  
Manufacturer’s Information  
Frequency Specification  
Details of Clocks  
–
–
–
–
–
8E  
16  
2F  
39  
72  
73  
F4  
F5  
63  
64-125  
126  
127  
128+  
64  
8F  
FF  
Unused Storage Locations  
1) HYS72V16300GR-7  
2) HYS72V16301GR-7  
3) HYS72V32301GR-7  
4) HYS72V32300GR-7  
INFINEON Technologies  
16  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Package Outlines for Raw Card AA  
Module Package  
JEDEC MO-161  
Registered DIMM Modules Raw Card AA (L-DIM168-44)  
133.35 ±  
0.15  
4 max.  
127.35  
Register  
42.18  
Register  
PLL  
3
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27±  
0.1  
3
1.27  
66.68  
2
85 94  
95  
124 125  
168  
Detail of Contacts  
1+0.5  
L-DIM-168-44  
1.27  
note: all outline dimensions and tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
17  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Package Outlines for Raw Card B  
Module Package  
JEDEC MO-161  
Registered DIMM Modules Raw Card B (L-DIM168-37)  
128MB, 256MB, 512MB & 1GB modules based on  
x4 SDRAM components  
±
0.15  
133.35  
127.35  
4 max.  
Register  
Register  
41  
PLL  
3
1
10  
11  
6.35  
40  
84  
1.27±  
0.1  
3
6.35  
1.27  
42.18  
66.68  
2
85 94  
95  
124 125  
168  
Register  
Detail of Contacts  
1+0.5  
L-DIM-168-37  
1.27  
note: all outline dimensions and tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
18  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Package Outlines for Raw Card B (with stacked components)  
Module Package  
JEDEC MO-161  
Registered DIMM Modules Raw Card B (L-DIM168-37)  
1 GByte and 2 GByte modules  
±
0.15  
133.35  
127.35  
6.8 max.  
Register Register  
PLL  
1
10  
11  
6.35  
40  
41  
6.35  
84  
1.27±  
0.1  
3
1.27  
42.18  
66.68  
2
85 94  
95  
124 125  
168  
Register  
Detail of Contacts  
1+0.5  
L-DIM-168-37-S  
1.27  
note: all outline dimensions and tolerances are in accordance with the JEDEC standard  
INFINEON Technologies  
19  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Functional Description  
All these PC133 168-pin Registered DIMMs conform to a compatible set of timing and operation  
characteristics intended to comply with the 133 MHz standards. The Registered DIMMs achieve  
high speed data transfer rate up to 133 MHz, when in “registered mode”. The “registered mode” is  
achieved when the REGE input signal is in “high” state or the pin is not connected. Operation in  
“buffered mode” (REGE = “low”) needs careful system design to compensate all input signals for the  
extra delay time of the register components when in “buffered mode”. “Buffered mode” is limited to  
66 Mhz maximum operation frequency.  
Registered Mode:  
All control and address signals are synchronized with the positive edge of externally supplied clocks  
and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM  
devices. The use of the on-board register reduces the capacitive loading of the DIMM on input  
control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM  
tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show  
DIMM operation at the tabs, not SDRAM operation.  
The picture below depicts an overview of the effect of the Registered Mode on the data outputs  
(DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS  
latency, in the case two clocks. With the register, the data is delayed according to the device CAS  
latency plus an additional clock cycle. This is known as the DIMM CAS latency, and in this example  
is four three. The data path can be thought of as a pipeline in which the register effectively lengthens  
the pipe by one clock cycle.  
Registered DIMM Burst Read Operation (BL = 4)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
Command  
Read A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Device  
CAS latency = 2  
DOUT A0 DOUT A1 DOUT A2 DOUT A3  
t
CK2, DQ’s  
DIMM  
CAS latency = 3  
DOUT A0 DOUT A1 DOUT A2 DOUT A3  
Added for on-DIMM pipeline register  
t
CK3, DQ’s  
One Clock  
Reg-DIMM Latency = 1  
SPT03968  
In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline  
register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the  
next clock cycle after the Write command is issued. the remaining data inputs must be supplied on  
INFINEON Technologies  
20  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
each subsequent rising clock edge until the burst length is completed. When the burst has finished,  
any additional data supplied to the DQ pins will be ignored.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
Command  
DQ’s  
NOP  
Write A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
don’t care  
DIN A0  
DIN A1  
DIN A2  
DIN A3  
The first data element and the Write  
are registered on the next clock edge  
Reg-DIMM Latency = 1 CLK  
Extra data is ignored after  
termination of a Burst.  
SPT03969  
Registered DIMM Burst Write Operation (BL = 4)  
INFINEON Technologies  
21  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
INFINEON Technologies  
22  
1.02  
HYS 72Vxx3xxGR  
PC133 Registered SDRAM-Modules  
Change List  
1.99  
First revision  
2.99  
Iol & Ioh changed to 4 mA, Input capacitances on CLK adjusted to 12 PF accor-  
ding to INTEL Rev.1.2 registered DIMM specification, thz max changed to 7 ns  
2.99  
2.99  
4.99  
Compliance Coded adjusted in accordance JEDEC PC133 Rev.0.9 specification  
Byte 21 changed from 16 to 1F according to JEDEC PC133 Rev.0.9 spec.  
Changed to final  
Infineon logo added  
6.5.99  
25.5.99  
15.7.99  
Some SPD codes changed for PC100 2-2-2 compartibility  
512 Mbyte and 1GB PC133 DIMM added  
Partnumber changes from HYS72Vxx200GR to HYS72Vxx300GR due to new  
gerber file L-DIMM168-37-2  
CL2 condition for 256Mb based modules changed from -8(222) to -8A(322)  
5.8.99  
31.8.99  
6.9.99  
256MByte module based on 128 Mbit SDRAMs added  
Drawings for Raw Card B added  
Databookversion from R+L used, 256MByte added  
1.10.99  
Checksum for 128Mb based module added  
some typoos corrected, Headline changed  
8.11.99  
Thickness dimensions for 1 GByte module drawing changed to 8 max.  
30.11.99  
Notes renumbered, note 1 added : Registered DIMM module operating tempe-  
rature conditions, some parameters changed according to INTELs PC133 speci-  
fiction  
13.12.99  
10.1.2000  
25.9.2000  
HYS72V32300GR-7.5 (256Mbit based 256Mbyte module added)  
HYS72V16301GR-7.5 added  
ICC currents on page 9 updated according to the latest values of the  
64M S19, 128Mb S17 and 256Mb S20 datasheet  
4.12.2000  
18.1.2001  
Thickness for 1 GByte modules changed from 8.00 mm max.(JEDEC) to  
6,40 typ. (actual)  
Clarification of “buffered mode”operation as a not tested functionality on these  
modules.  
Datasheet is for PC133 Registered DIMMs with components based on S17 pro-  
cess and further shrink versions only  
Changes in SPD-Code for 256Mb based modules in Byte 23, 127 and the  
Check sum in Byte 63 to make these module 100 % backward compatible to  
PC100-2-2-2 operation (TPCR_05 from 19.01.2001)  
14.02.2001  
-7 speed sort (PC133-222) added  
SPD Codes for -7 added  
3.4.2001  
6.6.2001  
2 GByte Module added  
Typo in SPB04130 corrected ( new: SPB04130-2)  
Outline drawings changed to L-DIM-168-44, 37 & 37S  
Absolute maximum rating table added  
06.09.2001  
1GByte module one bank with 512Mbit component added  
1 GByte and 2 Gbyte modules with “inhouse” stacking added  
SCR: Thickness of modules with stacked components changed  
from 6.4 to 6.8 max  
19.9.2001  
1 GByte and 2 Gbyte modules with “inhouse” stacking added  
17.12.2001  
SCR-028-2001-11-12 PC133 / TPCR_08 / JC42.5 Item 1138.5 :  
JEDEC changed Byte 62h (SPD Revision) from 02h to 12h  
Checksum changed therefore also  
INFINEON Technologies  
23  
1.02  
厂商 型号 描述 页数 下载

INFINEON

 		HYS64-72V2200GU-8 3.3V 2M ×64 /72- 1位BANK SDRAM模块3.3V 4M ×64 /72- 2位BANK SDRAM模块[ 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module ] 17 页

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INFINEON

 		HYS64D128020GBDL-6-A [ DDR DRAM Module, 128MX64, 0.7ns, CMOS, SO-DIMM-200 ] 11 页

ETC

 		HYS64D128020GBDL-7-A ？ 1GB （ 1024Mx64 ） PC2100 2银行？\n[ ?1GB (1024Mx64) PC2100 2-bank? ] 11 页

INFINEON

 		HYS64D128020GU-7-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

INFINEON

 		HYS64D128020GU-8-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

QIMONDA

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INFINEON

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