PYA28C64B - 8K x 8 EEPROM
OPERATIOꢀ
READ
infinitely wide, so long as the host continues to access the
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE re-
turning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
device within the byte load cycle time of 150µs.
DATA POLLIꢀꢂ
The PYA28C64B features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the PY-
A28C64B, eliminating additional interrupts or external
hardware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the comple-
ment of that data on I/O7 (i.e., write data=0xxx xxxx, read
data=1xxx xxxx). Once the programming cycle is com-
plete, I/O7 will reflect true data. Note: If the PYA28C64B
is in the protected state and an illegal write operation is
attempted, DATA Polling will not operate.
BYTE WRITE
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The PYA28C64B supports both a
CE and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first. A
byte write operation, once initiated, will automatically con-
tinue to completion.
TOꢂꢂLE BIT
PAꢂE WRITE
The PYA28C64B also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle, I/O6 will toggle from HIGH
to LOW and LOW to HIGH on subsequent attempts to
read the device. When the internal cycle is complete the
toggling will cease and the device will be accessible for
addtional read or write operations.
The page write feature of the PYA28C64B allows 1 to
64 bytes of data to be consecutively written to the PY-
A28C256 during a single internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the source
address), but the page address (A6 through A12) for each
subsequent valid write cycle to the part during this opera-
tion must be the same as the initial page address. The
bytes within the page to be written are specified with the
A0 through A5 inputs.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional 1 to 63 bytes in the same man-
ner as the first byte was written. Each successive byte
load cycle, started by the WE HIGH to LOW transition,
must begin within 150µs of the falling edge of the pre-
ceding WE. If a subsequent WE HIGH to LOW transition
is not detected within 150µs, the internal automatic pro-
gramming cycle will commence. There is no page write
window limitation. Effectively, the page write window is
Document # EEPROM111 REV OR
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