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Flash Cards

ATA45 Series

White Electronic Designs

ATA45 Series FLASH CARDS

8MB to 512MB

■

ISA standard and Read/Write unit is 512 bytes

(sector) sequential access

PRODUCT DESCRIPTION

ATA45 series Flash ATA cards are built with NAND flash

memory components operating as solid-state diskꢀ They

comply with the PC card ATA standard and are suitable

for use as a data storage memory medium for PCs or

other electronic equipmentꢀ The read/write unit is 1

sector (512 bytes) sequential accessꢀ

High performance:

Host data transfer rate

Flash data transfer rate

20ꢀ0 MB/sec

10ꢀ0 MB/sec

■

Maximum card density is 512 MB

3 variations of mode access

Memory card mode

I/O card mode

FEATURES

■

PC Card-ATA/True IDE/ I/O Card mode compatible

host interface

True-IDE mode

68 pin connector and type II stainless steel

housing

■

Internal self-diagnostic program operates at V_CC

power on

Automatic sensing of PC Card ATA and IDE mode

Included 256-byte CIS ROM

High data reliability

Endurance: 100,000 Program / Erase cycles

Support the five PC Card ATA addressing modes

Host Interface bus width: 8/16-bit Access

Flash Interface bus width: 8-bit Access

Support 3 power save mode: standby / idle / active

Auto power down function

High reliability based on internal ECC (Error

Correcting Code) function 2-bit ECC

Data reliability is 1 error in 10¹⁴bits readꢀ

■

Power Consumption

Active mode

Idle mode

Stop mode

30 mA (typꢀ), 40 mA (maxꢀ)

2-bit ECC function

10 mA

400 µA

■

Operating Voltage: 3ꢀ3 V and 5ꢀ0 V

CARD BLOCK DIAGRAM

Internal Vcc

Vcc

GND

Data

In/Out

Samsung

NAND

Flash

Host

Samsung

Interface

Controller

Control

July 2003 Revꢀ 0

ECO #16317

1

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Flash Cards

ATA45 Series

White Electronic Designs

CARD CAPACITIES (CF TYPE I BLANK HOUSING)

Capacity

8 MB

Part

Number

Sectors/CerardCylind

Sector/Track

Heads

WED7P008ATA4504C25

WED7P016ATA4504C25

WED7P032ATA4504C25

WED7P048ATA4504C25

WED7P064ATA4504C25

WED7P096ATA4504C25

WED7P128ATA4504C25

WED7P256ATA4504C25

WED7P512ATA4504C25

15,616

31,488

122

246

32

63

4

16 MB

32 MB

62,976

492

4

48 MB

94,464

738

4

64 MB

125,952

188,928

251,904

503,808

1,029,168

246

16

96 MB

369

128 MB

256 MB

512 MB

492

984

1,021

PHYSICAL SPECIFICATION

The ATA45 series physical specification complies with PCMCIA standard card formatꢀ

CARD SIZE AND OUTLINE

Type II

1.6mm

0.05

85.6mm

0.20

1.0mm

0.05

3.0m

MIN.

54.0mm

0.10

Substrate

1.0mm

0.05

10.0mm

MIN

Interconnect

3.3mm 0.10mm

5.0mm T1

0.197”

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Flash Cards

ATA45 Series

White Electronic Designs

INTERFACE SPECIFICATION

SIGNAL PIN ASSIGNMENTS

Memory Card Mode

Signal name

I/O Card Mode

True IDE Mode

Signal name

Pin NO&

1

I/O

Signal name

GND

D3

I/O

I

I/O

I

GND

D3

I/O

I

GND

D3

2

3

D4

4

D5

5

D6

6

D7

7

CE1

A10

OE

CE1

A10

OE

CE1

A10

ATASEL

8

I

9

I

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

I

A9

A8

I

A8

I

A8

I

WE

RDY/BSY

VCC

WE

IREQO

VCC

WE

NTRQO

VCC

O

I

A7

A6

I

A6

I

A6

I

A5

I

A5

I

A5

I

A4

I

A4

I

A4

I

A3

I

A3

I

A3

I

A2

I

A2

I

A2

I

A1

I

A1

I

A1

I

A0

I

A0

I

A0

I

D0

I/O

O

I/O

I

D0

I/O

O

I/O

I

D0

I/O

O

I/O

I

D1

D2

WP

GND

CD1

D11

D12

D13

D14

D15

CE2

VS1

IORD

IOWR

IOIS16

GND

CD1

D11

D12

D13

D14

D15

CE2

VS1

IORD

IOWR

IOIS16

GND

CD1

D11

D12

D13

D14

D15

CE2

VS1

IORD

IOWR

O

I

O

I

O

I

3

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Flash Cards

ATA45 Series

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SIGNAL PIN ASSIGNMENTS CONTꢀ

Memory Card Mode

Signal name

I/O Card Mode

Signal name

True IDE Mode

Signal name

Pin NO&

51

I/O

I

I/O

I

I/O

I

VCC

52

53

54

55

56

CSEL

VS2

RESET

WAIT

INPACK

REG

BVD2

BVD1

D8

CSEL

VS2

CSEL

VS2

57

O

58

I

RESET

WAIT

INPACK

REG

SPKR

STSCHG

D8

I

RESET

IORDY

INPACK

REG

DASP

PDIAG

D8

I

59

O

60

O

61

I

62

I/O

O

I/O

O

I/O

O

63

64

65

D9

66

D10

CD2

GND

D10

67

CD2

GND

CD2

GND

68

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Flash Cards

ATA45 Series

White Electronic Designs

INTERFACE SIGNALS DESCRIPTION

Symbol

Type

Name and Function

A⁰- A10

INPUT

ADDRESS BUS: These address lines along with the REG signal are used to select the following: The I/O port

address registers within the PC Storage Card, the memory mapped port address registers within the PC

Storage Card, a byte in the Cards information structure and its configuration control and status registers< This

signal is the same as the PC Card Memory Mode signal in PC Card I/O mode< In True IDE Mode only A [2:0]

are used to select the one of eight registers in the Task File, the remaining address lines should be grounded

by the host<

D⁰- D15

INPUT/

OUTPUT

DATA BUS: These signal lines carry the Data, Commands and Status information between the host and the

controller< D⁰is the LSB of the even byte of the word< D8 is the LSB of the odd byte of the word<

This signal is the same as the PC Card memory mode signal in PC Card I/O mode< In True IDE mode, all Task

File operations occur in byte mode on the low order bus D0-D7 while all data transfers are 16 bit using D0D15<

CE¹, CE2

INPUT

CARD ENABLE: CE1 and CE2 are card select signals, active low< These input signals are used both to select

the card and to indicate to the card whether a byte or a word operation is being performed< CE2 always

accesses the odd byte of the word< CE¹accesses the even byte or the Odd byte of the word depending on

A0 and CE2< A multiplexing scheme based on A0, CE1, CE2 allows 8 bit hosts to access all data on

D0-D7< This signal is the same as the PC card memory mode signal in PC Card I/O mode< In the True IDE

mode, CE1 is the chip select for the task file registers while CE2 is used to select the Alternate Status

Register and the Device Control Register<

OE, ASTEL

WE

INPUT

OUTPUT ENABLE, ATA SELECT: OE is used for the control of data read in Attribute area or Common memory

area< To enable True IDE Mode this input should be grounded by the host (in power up)<

WRITE ENABLE: WE is used for the control of data write in Attribute memory area or Common memory area<

This is a signal driven by the host and used for strobing memory write data to the registers of the PC Card

when the card is configured in the memory interface mode< It is also used for writing the configuration

registers< In PC Card I/O mode, this signal is used for writing the configuration registers< In True IDE mode,

this input signal is not used and should be connected to VCC by the host<

IORD

IOWR

INPUT

I/O READ: IORD is used for control of read data in the Task File area< This card does not respond to IORD

until I/O card interface setting up<

I/O WRITE: IOWR is used for control of data write in the Task File area< This card does not respond to IOWR

until I/O card interface setting up< This signal is not used in memory mode< The I/O write strobe pulse is used

to clock I/O data on the card data bus into the PC Card controller registers when the PC Card is configured to

use the I/O interface< The clocking will occur on the negative to positive edge of the signal (trailing edge)< In

True IDE mode, this signal has the same function as in PC Card I/O Mode<

RDY/BSY,

IREQ, INTRQ

OUTPUT

READY/BUSY INTERRUPT REQUEST: In memory mode, this signal is set high when the PC Card is

ready to accept a new data transfer operation and held low when the card is busy< The host memory card

socket must provide a pull-up resistor< At power up and at reset, the RDY/BSY signal is held low (busy) until

the PC Card has completed its power up or reset function< No access of any type should be made to the PC

Card during this time< The RDY/BSY signal is held high (disabled from being busy) whenever the following

condition is true: The PC Card has been powered up with RESET continuously disconnected or asserted< I/O

operation - After the PC Card has been configured for I/O operation, this signal is used as Interrupt request<

This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt< In True IDE

mode, this signal is the active high Interrupt request to the host<

CD¹, CD2

OUTPUT

CARD DETECTION: CD1 and CD2 are the card detection signals< CD1 and CD2 are connected to ground in

this card, so the host can detect if the card is inserted or not<

WP, IOIS16

WRITE PROTECT, 16 BIT I/O PORT: In memory card mode, WP is held low because this card does not have a

write protect switch< In the I/O card mode, IOIS16 is asserted when Task File registers are accessed in 16-bit

mode< In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer

cycle<

REG

INPUT

ATTRIBUTE MEMORY AREA SELECTION: REG should be high level during common memory area accessing,

and low level during Attribute area accessing< The attribute memory area is located only in an even address, so

D⁰to D7 are valid and D8 to D15 are invalid in the word access mode< Odd addresses are invalid in the byte

access mode< The signal must also be active (low) during I/O cycles when the I/O address is on the Bus< In

True IDE Mode this input signal is not used and should be connected to VCC<

BVD2, SPKR, INPUT/

BATTERY VOLTAGE DETECTION, DIGITAL AUDIO OUTPUT, DISK ACTIVE/SLAVE PRESENT: In memory card

mode, BVD2 outputs the battery voltage status in the card< This card has no battery, so this output is high

level constantly< In the I/O card mode, SPKR is held High because this card does not have digital audio output<

In True IDE Mode DASP is the Disk Active/Slave Present signal in the Master/Slave handshake protocol<

DASP

OUTPUT

RESET,

RESET

INPUT

RESET: By assertion of the RESET signal, all registers of this card are cleared and the RDY/BSY signal turns

to high level< In True IDE Mode RESET is the active low hardware reset from the host<

5

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Flash Cards

ATA45 Series

White Electronic Designs

INTERFACE SIGNALS DESCRIPTION CONTꢀ

Symbol

Type

Name and Function

WAIT, IORDY OUTPUT

WAIT: This signal outputs low level for the purpose of delaying memory access cycle or I/O access cycle< In

True IDE Mode this output signal may be used as IORDY< As for this controller, this output is high impedance

state constantly<

INPACK

OUTPUT

INPUT ACKNOWLEDGE: This signal is not used in the memory card mode< The Input acknowledge signal is

asserted by the PC Card when the card is selected and responding to an I/O read cycle at the address that is

on the address bus< This signal is used by the host to control the enable of any input data buffers between the

PC Card and the CPU< In True IDE mode, this output signal is not used and should be connected to V^CCat

the host<

BVD1,

STSCHG,

PDIAG

INPUT/

OUTPUT

BATTERY VOLTAGE DETECTION, STATUS CHANGE, PASS DIAGNOSTIC: In the memory card mode, BVD1

outputs the battery voltage status in the card< This card has no battery, so this output is high level constantly<

In the I/O card mode, STSCHG is used for changing the status of the Configuration status register in the

Attribute area, while the card is set I/O card interface< In True IDE Mode, PDIAG is the Pass Diagnostic signal

in the Master/Slave handshake protocol<

VS¹, VS2

OUTPUT

INPUT

VCC VOLTAGE SENSE: These signals are intended to notify the socket of the PC Cards CIS VCC requirement<

VS1 is held low and VS2 is not connected in this card<

CSEL

CARD SELECT: This signal is not used in the memory card mode and I/O card mode< This internally pulled up

signal is used to configure this device as a Master or a Slave when configured in the True IDE Mode< When

this pin is grounded, this device is configured as a Master< When the pin is open, this device is configured as

a Slave<

PCMCIA-ATA REGISTER MAPPING ADDRESSꢀ

PCMCIA-ATA I/O MAPPING ADDRESS

REG

Primary I/O

A[10:0]

Secondary I/O Independent I/O IORD = L

IOWR = L

A[10:0]

170H

171H

172H

173H

174H

175H

176H

177H

-

A[3:0]

L

1F0H

1F1H

1F2H

1F3H

1F4H

1F5H

1F6H

1F7H

-

0H

Read Even Data

Error Register

Write Even Data

Feature Register

Sector Count

1H

2H

Sector Count

3H

Sector Number

Cylinder Low

Sector Number

Cylinder Low

4H

5H

Cylinder High

6H

Drive/Head

7H

Status Register

Duplicate Read Even Data

Duplicate Read Odd Data

Duplicate Error

Alternate Status

Drive Address

Command

8H

Duplicate Write Even Data

Duplicate Write Odd Data

Duplicate Feature

Device Control

Reserved

-

9H

-

0DH

0EH

0FH

3F6H

3F7H

376H

377H

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Flash Cards

ATA45 Series

White Electronic Designs

PCMCIA-ATA MEMORY MAPPING ADDRESS

REG

H

A10

L

A[9:4]

X

A[3]

L

A[2]

L

A[1]

L

A[0]

L

IORD = L

IOWR = L

Read Data

Write Data

H

L

X

L

H

L

Error Register

Sector Count

Feature

H

L

X

L

H

L

Sector Count

H

L

X

L

H

L

Sector Number

Cylinder Low

Sector Number

Cylinder Low

H

L

X

L

H

L

H

L

X

L

H

L

Cylinder High

Drive/Head

H

L

X

L

H

L

Drive/Head

H

L

X

L

H

L

Status Register

Duplicate Read Even Data

Duplicate Read Odd Data

Duplicate Error

Alternate Status

Drive Address

Read Even Data

Read Odd Data

Command

H

L

X

H

X

Duplicate Write Even Data

Duplicate Write Odd Data

Duplicate Feature

Device Control

Reserved

H

L

X

L

H

L

H

L

X

H

X

L

H

L

X

H

X

H

L

X

H

L

H

X

Write Even Data

Write Odd Data

H

X

H

THE ATA REGISTERS AND PCMCIA REGISTERS

STATUS REGISTER

DIRECTION - This register is read-only by the hostꢀ

ACCESS RESTRICTION - The contents of this register, except for BSY, will be ignored when BSY is set to oneꢀ BSY

is valid at all timeꢀ The contents of the register and all other Command Block registers are not valid while a device

is in the Sleep modeꢀ

FUNCTIONAL DESCRIPTION - This register contains the device statusꢀ The contents of this register are updated to

reflect the current state of the device and the progress of any command being executed by the deviceꢀ

BIT DESCRIPTION

7

6

5

4

3

2

1

0

BSY

DRDY

DF

DSC

DRQ

CORR

IDX

ERR

BIT 0 ERR (Error) indicates that an error occurred during execution of the previous commandꢀ The Error register has

additional information regarding the cause of the error when this bit is assertedꢀ

BIT 1 IDX (Index) is vendor specificꢀ

BIT 2 CORR (Corrected Data) is used to indicate a correctable data errorꢀ The definition of what constitutes a

correctable error is vendor specificꢀ

BIT 3 DRQ (Data Request) indicates that the device is ready to transfer a word or byte between the host and the

deviceꢀ

BIT 4 DSC (Device Seek Complete) indicates that the device heads are settled over a trackꢀ

BIT 5 DF (Device Fault) indicates a device fault error has been detectedꢀ The internal status or internal conditions that

causes this error to be indicated is vendor specificꢀ

BIT 6 DRDY (Device Ready) is set to indicate that the device is capable of accepting all command codesꢀ This bit will

be cleared at power onꢀ

BIT 7 BSY (Busy) is set whenever the device has control of the command block registersꢀ When the BSY bit is equal

to one, the commands written to this register will be ignored by the deviceꢀ

7

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Flash Cards

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COMMAND REGISTER

DIRECTION - This register is write-only by hostꢀ

ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zeroꢀ The contents of this

register and all other Command Block registers are not valid while a device is in the Sleep modeꢀ

FUNCTIONAL DESCRIPTION - This register contains the command code being sent to the deviceꢀ Command

execution begins immediately after this register is writtenꢀ

BIT DESCRIPTION

7

6

5

4

3

2

1

0

Command Code

ERROR REGISTER

DIRECTION - This register is read-only by hostꢀ

ACCESS RESTRICTION - The contents of this register shall be valid when BSY and DRQ are equal to zero and ERR

is assertedꢀ

FUNCTIONAL DESCRIPTION - This register contains the operation status for the current commandꢀ

BIT DESCRIPTION

7

6

5

4

3

2

1

0

R

UNC

MC

IDNF

MCR

ABRT

TKONF

AMNF

BIT 0

AMNF (Address Mark Not Found) indicates the data address mark has not been found after finding the correct

ID fieldꢀ

BIT 1

BIT 2

TKONF (Track 0 Not Found) indicates the track 0 has not been found during a RECALIBRATE commandꢀ

ABRT (Aborted Command) indicates the requested command has been aborted because the command code or a

command parameter is invalid or some other error has occurredꢀ

MCR (Media Change Requested) is used by removable media devicesꢀ

IDNF (ID Not Found) indicates the requested sectors ID field could not be foundꢀ

MC (Media Change) is used by removable media devicesꢀ

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

UNC (Uncorrectable Data Error) indicate an uncorrectable data error has been encounteredꢀ

Reserved

FEATURE REGISTER

DIRECTION - This register is write-only by hostꢀ

ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zeroꢀ

FUNCTIONAL DESCRIPTION - This register is command specificꢀ

BIT DESCRIPTION

7

6

5

4

3

2

1

0

Command Specific

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Flash Cards

ATA45 Series

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SECTOR NUMBER REGISTER

DIRECTION - This register is bi-directional for the drive and hostꢀ

ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zeroꢀ

FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the

starting sector number for any media accessꢀ If the LBA bit is set to one in the Device/Head register, this register

contains Bits 7-0 of the LBA for any media accessꢀ

BIT DESCRIPTION

CHS

7

6

5

4

3

2

1

0

Sector (7:0)

LBA

3

LBA (7:0)

SECTOR COUNT REGISTER

DIRECTION - This register is bi-directional for the drive and hostꢀ

ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zeroꢀ

FUNCTIONAL DESCRIPTION - This register contains the number of sector of data requested to be transferred on a

read or write operation between the host and the deviceꢀ If the value in this register is zero, a count of 256 sectors is

specifiedꢀ

BIT DESCRIPTION

7

6

5

4

3

2

1

0

Sector Count

CYLINDER LOW REGISTER

DIRECTION - This register is bi-directional for the drive and hostꢀ

ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zeroꢀ

FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the

low order bits of the starting cylinder address for any media accessꢀ If the LBA bit is set to one in the Device/Head

register, this register contains Bits 15-8 of the LBA for any media accessꢀ

BIT DESCRIPTION

CHS

7

6

5

4

3

2

1

0

Cylinder (7:0)

LBA

3

LBA (15:8)

9

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CYLINDER HIGH REGISTER

DIRECTION - This register is bi-directional for the drive and hostꢀ

ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zeroꢀ

FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the

low order bits of the starting cylinder address for any media accessꢀ If the LBA bit is set to one in the Device/Head

register, this register contains Bits 23-16 of the LBA for any media accessꢀ

BIT DESCRIPTION

CHS

7

6

5

4

3

2

1

0

Cylinder (7:0)

LBA

3

LBA (15:8)

DEVICE/HEAD REGISTER

DIRECTION - This register is bi-directional for the drive and hostꢀ

ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zeroꢀ

FUNCTIONAL DESCRIPTION - This register selects the device, defines address translation as CHS or LBA, and

provides the head address if CHS mode or LBA (27:24) if LBA modeꢀ

BIT DESCRIPTION

CHS (CYLINDER-HEAD-SECTOR)

7

6

5

4

3

2

1

0

1

LBA

1

DEV

HS3

HS2

HS1

HS0

LBA (LOGIC BLOCK ADDRESS)

7

6

5

4

3

2

1

0

1

LBA

1

DEV

LBA

(27:24)

BIT 0~3 If LBA is equal to zero (CHS), these contain the head address of the starting CHS addressꢀ The HS3 bit is the

most significant bitꢀ If LBA is equal to one (LBA), these bits represent bits 27 through 24 of the LBAꢀ

BIT 4

DEV is the device addressꢀ When the DEV bit is equal to zero, Device 0 is selectedꢀ When the DEV bit is equal to

one, Device 1 is selectedꢀ

BIT 5

BIT 6

BIT 7

Bit 5 is set to one for backward compatibilityꢀ

LBA mode if this bit is set to one, otherwise, CHS modeꢀ

Bit 7 is set to one for backward compatibilityꢀ

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Flash Cards

ATA45 Series

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DATA REGISTER

DIRECTION - This register is bi-directional for the drive and hostꢀ

ACCESS RESTRUCTIONS - This register can be written or the content is valid on read when DRQ is set to oneꢀ

FUNCTIONAL DESCRIPTION - The data register is 16-bit wideꢀ

BIT DESCRIPTION

15

14

13

12

11

Data (15:8)

10

9

8

7

6

5

4

3

2

1

0

Data (7:0)

PCMICA CONFIGURATION OPTION REGISTER

DIRECTION - This register is read-only by hostꢀ

FUNCTION DESCRIPTION - Direct map to 0x200H in the Attribute Memoryꢀ

BIT DESCRIPTION

7

6

5

4

3

2

1

0

SRESET

LevlReq

Configuration Index

BIT 0~5 Configuration Index:

0 : common memory mode

1 : Independent IO mode

2 : Primary IO mode

3 : Secondary IO mode

BIT 6

BIT 7

LevlReq (level Mode IREQ#) : Level Mode Interrupts are selected when this bit is set to one, otherwise it is Pulse

Mode Interruptsꢀ

SRESET (Soft Reset): Setting this bit to one places the card in the reset stateꢀ This is equivalent to assertion of

the RESET signalꢀ

PCMICA CARD CONFIGURATION AND STATUS REGISTER

DIRECTION - This register is bi-directional for the drive and hostꢀ

FUNCTION DESCRIPTION - Direct map to 0x202H in the Attribute Memoryꢀ

BIT DESCRIPTION

7

6

5

4

3

2

1

0

SCDect

SigChg

IOis8

ResrV

SPKR/DASP

PwrDn

Intr

ResrV

BIT 0 Reserved

BIT 1 Intr (Interrupt Request Pending) : The real time status of the host interrupt signal pinꢀ

BIT 2 PwrDn (Power Down): This bit will enable the power down modeꢀ

BIT 3 SPKR/DASP: Setting this bit to 1 will enable DASP- to the BVD2 pin of the PCMCIA connector, otherwise, the BVD2

will be held at high-impedanceꢀ

BIT 4 ResrV: Reserved bit must be 0ꢀ

BIT 5 IOis8 (I/O Cycles Occur Only as 8-bit Transfer): When the host can provide I/O cycle only using the D7:D0 data

path, the PCMCIA software will set this bit to 1ꢀ

11

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Flash Cards

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White Electronic Designs

BIT 6 SigChg (Signal Change Enable/Disable): If this bit is set to one, the Signal Changed output is enabledꢀ

BIT 7 SCDect (Status Change Detected): This bit indicates that at least one bit of the Pin replacement Register is set oneꢀ

PCMICA PIN REPLACEMENT REGISTER

DIRECTION - This register is read-only by hostꢀ

FUNCTION DESCRIPTION - Direct map to 0x204H in the Attribute Memoryꢀ

BIT DESCRIPTION

7

6

5

4

3

2

1

0

ResrV

CRdy

CWProt

ResrV

CSRdy

CSWProt

BIT 0

BIT 1

CSWProt (Current State of Write Protect) : This bit represents the current the state of the Write Protectꢀ

CSRdy (Current State of Ready) : This bit represents the internal state of the READY signalꢀ

BIT 2~3 Reservedꢀ

BIT 4

BIT 5

CWProt (Change Write Protect) : This bit is set to one when CSWProt changes stateꢀ

CRdy (Changed Ready) : This bit is set to one when CSRdy changes stateꢀ

BIT 6~7 ResrV : Reserved bit must be 0ꢀ

PCMICA SOCKET AND COPY REGISTER

DIRECTION - This register is bi-directional for the drive and hostꢀ

FUNCTION DESCRIPTION - Direct map to 0x206H in the Attribute Memoryꢀ

BIT DESCRIPTION

7

6

5

4

3

2

1

0

ResrV

Copy Number

Socket Number

BIT 0~2 Socket Number : The first Socket is numbered 0ꢀ

BIT 3~5 Copy Number

BIT 6~7 ResrV : Reserved bit must be 0ꢀ

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12

Flash Cards

ATA45 Series

White Electronic Designs

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Symbol

VDD

Parameter

Ratings

0<3 to + 7<0

0<3 to V DD + 0<3

10

Unit

V

Supply voltage

Input voltage

VIN

V

IIN

DC input current

Storage temperature

mA

°C

T^STG

40 to + 80

RECOMMENDED OPERATING CONDITIONS

Symbol

V^DD

Parameter

Ratings

Unit

5V

3<3V

4<5 to + 5<5

3<0 to 3<6

V

DC supply voltage

Ta

Storage temperature

0 to + 60

°C

DꢀCꢀ ELECTRICAL CHARACTERISTICS @ 3ꢀ3V

(TA = 0 TO +60°C, VCC = 3ꢀ3V ± 5%)

Symbol

VIH

Parameter

Conditions

Min

Typ

Max

1<0

Unit

V

High level input voltage

Low level input voltage

Switching threshold

CMOS

2<0

VIL

V

VT

1<4

V

V^T+

Switching trigger,

2<0

V

positive-going threshold

V^T-

Switching trigger,

CMOS

1<0

V

negative-going threshold

Input buffer

Input buffer with pull-up

Input buffer

10

60

I^IH

High level input current

Low level input current

VIN = VDD

VIN = VSS

uA

30

10

160

2<4

10

I^IL

Input buffer with pull-up

30

10

VOH

VOL

IOZ

High level output voltage

Low level output voltage

Tri-state output leakage current

Maximum operating current

Idle current

IOH = 8 mA

V

IOL = 8 mA

0<4

10

VOUT = VSS or VDD

10

uA

mA

uA

I^DD

30

40

V^DD= 5<0V,

Iidle

Ids

10

f^MCLK= 20 MHz

Stop current

300

13

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Flash Cards

ATA45 Series

White Electronic Designs

ELECTRICAL CHARACTERISTICS @ 5V

(TA = 0 TO 60°C, VCC = 5V ± 10%)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CMOS

TTL

3<5

2<0

V^IH

High level input voltage

V

CMOS

TTL

1<5

0<8

V^IL

Low level input voltage

Switching threshold

V

CMOS

TTL

2<5

1<4

V^T

V^T+

Switching trigger,

positive-going threshold

CMOS

TTL

4<0

2<0

V

V^T-

Switching trigger,

negative-going threshold

CMOS

TTL

1<0

0<8

V

Input buffer

Input buffer with pull-up

Input buffer

10

100

10

I^IH

High level input current

Low level input current

VIN = VDD

VIN = VSS

uA

50

10

100

2<4

I^IL

uA

Input buffer with pull-up

50

10

VOH

VOL

IOZ

High level output voltage

Low level output voltage

Tri-state output leakage current

Maximum operating current

Idle current

IOH = 8 mA

V

IOL = 8 mA

0<4

10

VOUT = VSS or VDD

10

uA

mA

uA

I^DD

30

40

V^DD= 5<0V,

Iidle

Ids

10

f^MCLK= 24 MHz

Stop current

400

ENVIRONMENTAL AND RELIABILITY SPECIFICATIONS

ITEM

SPECIFICATION

Vibration

Operating

Non-Operating

15G peak to peak Max<

Shock

Operating

Non-Operating

2,000G Max<

Relative Humidity

(non-condensing)

Operating

Non-Operating

8% ~ 95%

MTBF

Operating

> 1,000,000 hours

Endurance

Data Reliability

³ 100,000 erase program cycles

ꢀ 1 non-recoverable error in 10¹⁴bits read

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14

Flash Cards

ATA45 Series

White Electronic Designs

INTERFACE SIGNAL TIMING

There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, a direct mapped

I/O transfer and a memory accessꢀ The two timing sequences are explained in detail in the PCMCIA PC Card

Standardꢀ The PC Card conforms to the timing in that reference documentꢀ

PC CARD INTERFACE

ATTRIBUTE MEMORY READ TIMING

300ns

Parameter

Symbol

IEEE Symbol

Min& ns

Max& ns

Read Cycle Time

tC(R)

tA(A)

TAVAV

TAVQV

TELQV

TGLQV

TEHQZ

TGHQZ

tAVWL

tELQNZ

tGLQNZ

tAXQX

300

Address Access Time

300

150

100

Card Enable Access Time

Output Enable Access Time

Output Disable Time from CE

Output Disable Time from OE

Address Setup Time

tA(CE)

tA(OE)

tDIS(CE)

tDIS(OE)

tSU(A)

30

5

Output Enable Time from CE

Output Enable Time from OE

Data Valid from Address Change

tEN(CE)

tEN(OE)

t^V(A)

5

0

NOTE: All times are in nanosecondꢀ Dout signifies data provided by the PC Card to the systemꢀ The CE signal or both

the OE signal & the WE signal must be de-asserted between consecutive cycle operationsꢀ

ATTRIBUTE MEMORY READ TIMING DIAGRAM

tC

(R)

An

tA

(A)

REG

tSU (A)

tV (A)

t

A

(CE)

(OE)

CE

OE

tEN (CE)

tDIS (CE)

t

A

tDIS (OE)

tEN (OE)

D

OUT

15

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Flash Cards

ATA45 Series

White Electronic Designs

ATTRIBUTE MEMORY WRITE TIMING

Note: A host cannot write to CISꢀ This timing is specified

only for the write to Configuration Registerꢀ

250ns

Max& ns

Parameter

Symbol

IEEE Symbol

Min& ns

250

150

30

Write Cycle Time

tC(W)

tW(WE)

tAVAV

tWLWH

tAVWL

tWMAX

tDVWH

tWMDX

Write Pulse Width

Address Setup Time

Write Recovery Time

Data Setup Time for WE

Data Hold Time

tSU(A)

tREC(WE)

tSU(D-WEH)

t^H(D)

30

80

30

NOTE: All times are in nanosecondꢀ Din signifies data provided by the system to the PC Cardꢀ

ATTRIBUTE MEMORY WRITE TIMING DIAGRAM

tC (W)

REG

An

tREC (WE)

tSU (A)

tW (WE)

WE

CE

tSU (D-WEH)

tH (D)

OE

DOUT

Data In Valid

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16

Flash Cards

ATA45 Series

White Electronic Designs

COMMON MEMORY READ TIMING

Parameter

Symbol

IEEE Symbol

Min& ns

Max& ns

125

Output Enable Access Time

Output Disable Time from OE

Address Setup Time

ta (OE)

tGLQV

tGHQZ

tAVGL

tdis (OE)

tsu (A)

100

30

20

0

Address Hold Time

th (A)

tGHAX

CE Setup before OE

tsu (CE)

th (CE)

tELGL

CE Hold following OE

Wait Delay Falling from OE

Data Setup for Wait Release

Wait Width Time

tGHEH

tGLWTV

tQVWTH

tWTLWTH

20

tv (WT-OE)

tv (WT)

tw (WT)

35

0

350

NOTE: The maximum load on WAIT is 1 LSTTL with 50pF total loadꢀ All times are in nanosecondsꢀ D^OUTsignifies data

provided by the PC Card to the systemꢀ The WAIT signal may be ignored if the OE cycle-to-cycle time is greater than the

Wait Width timeꢀ The Max Wait Width time can be determined from the Card Information Structureꢀ The Wait Width time

meets the PCMCIA specification of 12s but is intentionally less in this specificationꢀ

COMMON MEMORY READ TIMING DIAGRAM

An

tSU (A)

tH (A)

REG

tH (CE)

tSU (CE)

CE

tDIS (CE)

tA (OE)

OE

tW (WT)

WAIT

tDIS (OE)

tV

(WT)

tV (WT-OE)

D

OUT

17

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Flash Cards

ATA45 Series

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COMMON MEMORY WRITE TIMING

Parameter

Symbol

tsu (D-WEH)

th (D)

IEEE Symbol

Min& ns

80

Max& ns

Data Setup before WE

Data Hold following WE

WE Pulse Width

tDVWH

tlWMDX

tWLWH

tAVWL

30

tw (WE)

tsu (A)

150

30

Address Setup Time

CE Setup before WE

Write recovery Time

Address Hold Time

tsu (CE)

trec (WE)

th (A)

tELWL

0

tWMAX

30

tGHAX

20

CE Hold following WE

Wait Delay Falling from WE

WE High from Wait Release

Wait Width Time

th (CE)

tGHEH

20

tv (WT-WE)

tv (WT)

tWLWTV

tWTHWH

tWTLWTH

35

0

tw (WT)

350

NOTE: The maximum load on WAIT is 1 LSTTL with 50pF total loadꢀ All times are in nanosecondsꢀ D^INsignifies data

provided by the system to the PC Cardꢀ The WAIT signal may be ignored if the WE cycle-to-cycle time is greater than the

Wait Width timeꢀ The Max Wait Width time can be determined from the Card Information Structureꢀ The Wait Width time

meets the PCMCIA specification of 12s but is intentionally less in this specificationꢀ

COMMON MEMORY WRITE TIMING DIAGRAM

An

tSU (A)

tH (A)

REG

tH (CE)

tSU (CE)

CE

tREC (WE)

tW (WE)

WE

tW (WT)

WAIT

DIN

tV (WT)

tV (WT-WE)

tH (D)

tSU (D-WEH)

DIN Valid

White Electronic Designs Corporation Marlborough, MA (508) 485-4000

18

Flash Cards

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White Electronic Designs

I/O INPUT (READ) TIMING

Parameter

Symbol

IEEE Symbol

Min& ns

Max& ns

Data Delay after IORD

td (IORD)

tlGLQV

tlGHQX

tlGLIGH

tAVIGL

100

Data Hold following IORD

IORD Width Time

th (IORD)

0

165

70

20

5

tw (IORD)

Address Setup before IORD

Address Hold following IORD

CE Setup before IORD

tsuA (IORD)

thA (IORD)

tlGHAX

tsuCE (IORD)

thCE (IORD)

tsuREG

tELIGL

CE Hold following IORD

tlGHEH

tRGLIGL

tlGHRGH

tlGLIAL

tlGHIAH

tAVISL

20

5

REG Setup before IORD (IORD)

REG Hold following IORD

INPACK Delay Falling from IORD

INPACK Delay Rising from IORD

IOIS16 Delay Falling from Address

IOIS16 Delay Rising from Address

Wait Delay Falling from IORD

Data Delay from Wait Rising

Wait Width Time

thREG (IORD)

tdfINPACK (IORD)

tdrINPACK (IORD)

tdfIOIS16 (ADR)

tdrIOIS16 (ADR)

tdWT (IORD)

td (WT)

0

45

35

0

tAVISH

tlGLWTL

tWTHQV

tWTLWTH

tw (WT)

350

NOTE: The maximum load on WAIT, INPACK and IOIS16 is 1 LSTTL with 50pF total loadꢀ All times are in nanosecondsꢀ

Minimum time from WAIT high to IORD high is 0nsec, but minimum IORD width must still be metꢀ D^OUTsignifies data

provided by the PC Card to the systemꢀ The Wait Width time meets the PCMCIA specification of 12s but is intentionally

less in this specificationꢀ

I/O READ TIMING DIAGRAM

An

t

SU (IORD)

t

H

A (IORD)

RE (IORD)

t

SUREG (IORD)

REG

t

H

tSUCE (IORD)

tHCE (IORD)

CE

tWIORD

IORD

tDRINPACK (IORD)

INPACK

IOIS16

WAIT

tDFINPACK (IORD)

tDRIOIS16 (ADR)

tD

(IORD)

tDFIOIS16 (ADR)

tD (WT)

tDWT (IORD)

tW

(WT)

tH (IORD)

D

OUT

19

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Flash Cards

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White Electronic Designs

I/O INPUT (WRITE) TIMING

Parameter

Symbol

IEEE Symbol

Min& ns

Max& ns

Data Setup before IOWR

Data Hold following IOWR

IOWR Width Time

tsu (IOWR)

tDVIWH

tlWHDX

tlWLIWH

tAVIWL

60

30

165

70

20

5

th (IOWR)

tw (IOWR)

Address Setup before IOWR

Address Hold following IOWR

CE Setup before IOWR

tsuA (IOWR)

thA (IOWR)

tlWHAX

tsuCE (IOWR)

thCE (IOWR)

tsuREG (IOWR)

thREG (IOWR)

tdfIOIS16 (ADR)

tdrIOIS16 (ADR)

tdWT (IOWR)

tdrIOWR (WT)

tw (WT)

tELIWL

CE Hold following IOWR

REG Setup before IOWR

REG Hold following IOWR

IOIS16 Delay Falling from Address

IOIS16 Delay Rising from Address

Wait Delay Falling from IOWR

IOWR high from Wait high

Wait Width Time

tlWHEH

tRGLIWL

tlWHRGH

tAVISL

20

5

0

35

tAVISH

tlWLWTL

tWTJIWH

tWTLWTH

0

350

NOTE: The maximum load on WAIT, INPACK, and IOIS16 is 1 LSTTL with 50pF total loadꢀ All times are in nanosecondsꢀ

Minimum time from WAIT high to IOWR high is 0nsec, but minimum IOWR width must still be metꢀ D^INsignifies data

provided by the system to the PC Cardꢀ The Wait Width time meets the PCMCIA specification of 12s but is intentionally

less in this specificationꢀ

I/O WRITE TIMING DIAGRAM

An

t

SU (IOWR)

t

H

A (IOWR)

RE (IOWR)

t

SUREG (IOWR)

REG

t

H

tSUCE (IOWR)

tHCE (IOWR)

CE

tWIORD

IOWR

IOIS16

WAIT

tDRIOIS16 (ADR)

tSU (IOWR)

tDFIOIS16 (ADR)

t

W (WT)

tD

WT (IOWR)

tH

(IOWR)

tDRIOWR (WT)

D

IN

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Flash Cards

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IDE MODE INTERFACE

IDE MODE READ TIMING

Parameter

Symbol

IEEE Symbol

Min& ns

Max& ns

Data Delay after IORD

Data Hold following IORD

IORD Width Time

td (IORD)

tlGLQV

tlGHQX

tlGLIGH

tAVIGL

tlGHAX

tELIGL

tlGHEH

tAVISL

tAVISH

100

th (IORD)

0

165

70

20

5

tw (IORD)

Address Setup before IORD

Address Hold following IORD

CE Setup before IORD

CE Hold following IORD

IOIS16 Delay Falling from Address

IOIS16 Delay Rising from Address

tsuA (IORD)

thA (IORD)

tsuCE (IORD)

thCE (IORD)

tdfIOIS16 (ADR)

tdrIOIS16 (ADR)

20

35

NOTE: The maximum load on IOIS16 is 1 LSTTL with 50pF total loadꢀ All times are in nanosecondsꢀ Minimum time from

WAIT high to IORD high is 0nsec, but minimum IORD width must still be metꢀ D^OUTsignifies data provided by the PC Card

to the systemꢀ

IDE MODE READ TIMING DIAGRAM

An

tSU (IORD)

tHA (IORD)

tSUCE (IORD)

tHCE (IORD)

CE

tWIORD

IORD

IOIS16

DOUT

tDRIOIS16 (ADR)

tH (IORD)

tD (IORD)

tDFIOIS16 (ADR)

21

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Flash Cards

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IDE MODE WRITE TIMING

Parameter

Symbol

IEEE Symbol

Min& ns

60

Max& ns

Data Setup before IOWR

Data Hold following IOWR

IOWR Width Time

tsu(IOWR)

tDVIWH

tlWHDX

tlWLIWH

tAVIWL

tlWHAX

tELIWL

tlWHEH

tAVISL

th(IOWR)

30

twI(OWR)

165

70

Address Setup before IOWR

Address Hold following IOWR

CE Setup before IOWR

tsuA(IOWR)

thA(IOWR)

20

tsuCE(IOWR)

thCE(IOWR)

tdfIOIS16(ADR)

tdrIOIS16(ADR)

5

CE Hold following IOWR

20

IOIS16 Delay Falling from Address

IOIS16 Delay Rising from Address

35

tAVISH

NOTE: The maximum load on IOIS16 is 1 LSTTL with 50pF total loadꢀ All times are in nanosecondsꢀ Minimum time from -

WAIT high to IOWR high is 0nsec, but minimum IOWR width must still be metꢀ D^INsignifies data provided by the system to

the PC Cardꢀ

IDE MODE WRITE TIMING DIAGRAM

An

tSU (IOWR)

tHA (IOWR)

tSUCE (IOWR)

tHCE (IOWR)

CE

tWIOWR

IOWR

IOIS16

DIN

tDRIOIS16 (ADR)

tH (IOWR)

tDFIOIS16 (ADR)

tSU (IOWR)

White Electronic Designs Corporation Marlborough, MA (508) 485-4000

22

Flash Cards

ATA45 Series

White Electronic Designs

RESET TIMING

Parameter

Symbol

tset

Min

Typ

Max

Unit

ms

Level Set before Power On

Power on Reset

Reset time

1

tpor

10

ms

trst

ms

RESET TIMING DIAGRAM

VCC

POR

(Internal)

Reset Pin

T_RST

T_POR

RDY/BSY Pin

T_SET

OE Pin

CSEL Pin

POWER ON RESET CHARACTERISTICS

All card status are reset automatically when V_CCvoltage goes over about 2ꢀ3 Vꢀ

Parameter

Symbol

tsu(VCC)

tpr

Min

100

0<1

Typ

Max

Unit

ms

Test conditions

CE setup time

V^CCrising up time

100

ms

t_PR

POWER ON RESET TIMING

C

V

t

SU(VCC)

CE1 , CE2

Please notice that the card insertion/removal should be

executed after card internal operations are completed

(status register bit 7 turns from 1 to 0)ꢀ

Attention for Card Use

In the reset or power off, all register information is

clearedꢀ

Before the card insertion Vcc cannot be supplied to the

cardꢀ After confirmation that CD1, CD2 pins are inserted,

supply Vcc to the cardꢀ

All card status are cleared automatically when Vcc

voltage turns below about 2ꢀ5Vꢀ

Notice that the card insertion/removal should not be

executed during host is active, if the card is used in true

IDE modeꢀ

OE must be kept at the Vcc level during power on reset

in memory card mode and I/O card modeꢀ OE must be

kept constantly at the GND level in True IDE modeꢀ

After the card hard reset, soft reset, or power on reset, the

card cannot access during +READY pin is low levelꢀ

Unused pins of data bus (D0 to D15) signals should not

be openedꢀ

23

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Flash Cards

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White Electronic Designs

CARD INFORMATION STRUCTURE (CIS) & IDENTIFY DRIVE (ID) INFORMATION

IDENTIFY DRIVE INFORMATION

Word8MB

16MB

848A

32MB

848A

48MB

848A

64MB

848A

02E2

0000

0004

0000

0200

0020

0001

7100

0000

All 2020

0000

0002

0004

*1

96MB

848A

128MB

848A

256MB

848A

01EC

0000

0010

0000

0200

0020

0003

D800

0000

All 2020

0000

0002

0004

1

0

848A

03D8

0000

0010

0000

0200

0020

0007

B000

0000

All 2020

0000

0002

0004

*1

1

007A

0000

0004

0000

0200

0020

0000

3D00

0000

All 2020

0000

0002

0004

*1

00F6

0000

0004

0000

0200

0020

0000

7B00

0000

All 2020

0000

0002

0004

*1

01EC

0000

0004

0000

0200

0020

0000

F600

0000

All 2020

0000

0002

0004

*1

00F6

0000

0010

0000

0200

0020

0001

EC00

0000

All 2020

0000

0002

0004

*1

0171

0000

0010

0000

0200

0020

0002

E200

0000

All 2020

0000

0002

0004

*1

2

3

4

5

6

7-8

9

10-19

20

21

22

23-26

27-46

47

*2

2

*2

0004

0000

0200

0000

0200

0000

0001

007A

0004

0020

3D00

0000

0100

3D00

0000

All 0000

0000

All 0000

0000

All 0000

0004

0000

0200

0000

0200

0000

0001

00F6

0004

0020

7B00

0000

0100

7B00

0000

All 0000

0000

All 0000

0000

All 0000

0004

0000

0200

0000

0200

0000

0001

01EC

0004

0020

F600

0000

0100

F600

0000

All 0000

0000

All 0000

0000

All 0000

0004

0000

0200

0000

0200

0000

0001

02E2

0004

0020

7100

0001

0100

7100

0001

All 0000

0000

All 0000

0000

All 0000

0004

0000

0200

0000

0200

0000

0001

00F6

0010

0020

EC00

0001

0100

EC00

0001

All 0000

0000

All 0000

0000

All 0000

0004

0000

0200

0000

0200

0000

0001

0171

0010

0020

E200

0002

0100

E200

0002

All 0000

0000

All 0000

0000

All 0000

0004

0000

0200

0000

0200

0000

0001

01EC

0010

0020

D800

0003

0100

D800

0003

All 0000

0000

All 0000

0000

All 0000

0004

0000

0200

0000

0200

0000

0001

03D8

0010

0020

B000

0007

0100

B000

0007

All 0000

0000

All 0000

0000

All 0000

48

49

50

51

52

53

54

55

56

57-58

59

60-61

62-127

128

129-159

160

161-255

Note 1ꢀ Firmware Version: Rev 1ꢀ15 (52 65 76 20 31 2E 31 35)

2ꢀ Model Number: SAMSUNG CF/ATA (53 41 4d 53 55 4e 47 20 43 46 2f 41 54 41 20 20 20 20 20 20)

White Electronic Designs Corporation Marlborough, MA (508) 485-4000

24

Flash Cards

ATA45 Series

White Electronic Designs

CARD INFORMATION STRUCTURE

AttributeOffset

000h

002h

Data

01

04

7

6

5

4

3

2

1

0

Description of Contents

Device Info Tuple

Link is 4bytes

CIS Function

Tuple Code

Link to next tuple

CISTPL_DEVICE

004h

DF

Device Type Code

Dh=I/O

W

1

Speed

7h

2h

I/O device,

No Write Protects,

Device Speed = 400ns

2Kbyte of address Space

End of Devices

Other Condition Device Info Tuple Tuple Code

Link is 4bytes

3<3V Vcc Operation

I/O device, No Write Protects,

Device Speed=250ns

Device ID

WPS, Speed

006h

008h

00Ah

00Ch

00Eh

010h

012h

4A

01

FF

1 C

04

X

9h

Device Size

List End Marker

CISTPL_DEVICE_OC

Device Size

End Marker

Link to next tuple

OC Info

Device ID WPS, Speed

02

D9

0

Reserved, 0

VccU

Speed

1h

M

Device Type Code

Dh=I/O

W

1

014h

016h

018h

01Ah

01Ch

01Eh

01

FF

18

02

DF

01

Device Size

List End Marker

CISTPL_JEDEC_C

2Kbyte of address Space

End of Devices

JEDEC ID Common Mem

Link is 2bytes

First Byte of JEDEC ID

Second Byte of JEDEC ID

Device Size

End Marker

Tuple Code

Link to next tuple

JEDEC ID of Device 1

JEDEC ID

PCMCIA Manufacture s ID

PCMCIA Code for PC Card-ATA

No Vpp Required

020h

022h

024h

026h

028h

02Ah

02Ch

20

04

CE

00

15

CISTPL_MANFID

Manufacture ID String

Link is 4bytes

Tuple Code

Link to next tuple

TPLMID_MANF

TPLMID_CARD

Tuple Code

PC Card Manufactures ID Code

Manufacture Information

CISTPL_VERS_1

Level 1 Version/Product

Infor mation

02Eh

030h

032h

034h

036h

038h

03Ah

03Ch

03Eh

040h

042h

044h

046h

048h

04Ah

04Ch

04Eh

050h

052h

054h

056h

058h

05Ah

05Ch

05Eh

060h

062h

064h

066h

068h

20

04

01

53

41

4D

53

55

4E

47

20

00

52

65

76

20

31

2E

31

35

20

Link is 20bytes

PCMCIA 2<1

JEIDA 4<2

S

A

M

S

U

N

Link to next tuple

TPLLV1_MAJOR

TPLLV1_MINOR

String 1

Major Version Number

Minor Version Number

Manufacture Information

G

Name of Manufacture

End of Manufacture Information

Product Information

Null Terminator

End String 1

String 2

R

e

v

1

<

1

5

Firmware Revision

25

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Flash Cards

ATA45 Series

White Electronic Designs

CARD INFORMATION STRUCTURE CONTꢀ

AttributeOffset

06Ah

06Ch

06Eh

070h

072h

074h

076h

Data

00

FF

21

02

7

6

5

4

3

2

1

0

Description of Contents

Null Terminator

CIS Function

End String 2

End of Product Information

End of CIS Revision Number

List End Marker

End Marker

Tuple Code

Link to next tuple

TPLFID_FUNCTION

TPLFID_SYSINIT

CISTPL_FUNCID

Function ID Tuple

Link is 2bytes

Fixed Disk Function

System Initialization Bit Mask,

Power-On-Self Test

04

01

IC Card Function Code

RFU, 0

R

P

078h

07Ah

07Ch

07Eh

080h

082h

084h

086h

088h

22

02

01

22

03

02

0C

0F

CISTPL_FUNCE

Function Extention Tuple

Link is 2bytes

Disk Device Interface

PCCard-ATA Interface

Function Extention Tuple

Link is 3bytes

Disk Device Interface

Silicon/Rotating, ID/SN is unique

Auto, Idle, Standby, Sleep Mode

supported

Tuple Code

Link to next tuple

TPLFE_TYPE

TPLFE_DATA

Tuple Code

Link to next tuple

TPLFE_TYPE

TPLFE_DATA

Disk Function Extension Tuple Type

Interface Type Code

CISTPL_FUNCE

Disk Function Extension Tuple Type

RFU

R

U

P3

S

V

I

E

N

P2 P1

P0

08Ah

08Ch

08Eh

090h

1A

05

01

03

CISTPL_CONFIG

Configuration Tuple

Link is 5bytes

RASZ Size of Fields Byte

Entry Index 03h

Tuple Code

Link to next tuple

TPCC_SZ

RFSZ

TPCC_LAST

RMSZ

Last entry of

Configuration table

092h

00

TPCC_RADR

Configuration Registers are

located at 200h

Location of Config

Registers

094h

096h

02

0F

TPCC_RADR

RFU

S

P

C

I

4 Configuration Registers are

present

TPCC_RMSK

098h

09Ah

09Ch

1B

08

C0

CISTPL_CFTABLE_ENTRY

Configuration Entry Tuple

Link is 8bytes

Memory Mapped I/O, D: Default

Configuration, I: Interface Byte

Follows

Memory Only Interface, Bvd & WP TPCE_IF

not used, RDY/BSY & Wait used

for Memory Cycle

Vcc power-description structure only, TPCE_FS

MS: Single 2-byte length specified

Tuple Code

Link to next tuple

TPCE_INDX

I

D

R

Configuration Entry Number

09Eh

0A0h

0A2h

C0

A1

01

M

W

P

B

V

Interface Type

M

MS

I

R

QM:

AI

IO

SI

T Power

Misc

field

R

X

DI PI

H

V

L

V

N

V

Nominal Operating Supply Voltage, Power Parameters for Vcc

No Extension

Vcc Nominal is 5V

Length of Mem Space is 2KB

Start at 0 on Card

Power Down

0A4h

0A6h

0A8h

0AAh

0ACh

0AEh

0B0h

0B2h

55

08

00

20

1B

06

00

01

Ah

5h

Vcc Nominal Value

TPCE_MS Length LSB

TPCE_MS Length MSB

TPCE_MI

Tuple Code

Link to next tuple

TPCE_INDX

Length in 256 bytes pages(LSB)

Length in 256 bytes pages(MSB)

X

R

P

R

A

Twin

CISTPL_CFTABLE_ENTRY

Configuration Entry Tuple

Link is 6bytes

I

D Configuration Entry Number

M

MS

IR

Q

IO

T

Power

Vcc power-description structure only TPCE_FS

0B4h

21

R

DI

PI

AI

SI

H

V

L

V

N

V

Maximum Current required averaged TPCE_PD

over 10ms, Nominal Operating

Supply Voltage, With Extension

0B6h

0B8h

B5

1E

X

6h

5h

1V x3

Vcc Nominal is 3<3V

Vcc Nominal Value

1Eh(30d)

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Flash Cards

ATA45 Series

White Electronic Designs

CARD INFORMATION STRUCTURE CONTꢀ

AttributeOffset

0BAh

0BCh

0Beh

0C0h

Data

4D

1B

0A

C1

7

X

6

5

4

3

2

1

5h

0

Description of Contents

Peak I is 45mA

Configuration Entry Tuple

Link is 10bytes

I/O Mapped Contiguous 16

Registers Configuration, D: Default

Configuration, I: Interface Byte

Follows

CIS Function

Peak I Value

Tuple Code

Link to next tuple

TPCE_INDX

9h

CISTPL_CFTABLE_ENTRY

I

D

Configuration Entry Number

0C2h

41

W

R

P

B

Interface Type

I/O Interface, Bvd & WP not used, TPCE_IF

RDY/BSY active, Wait not used

for memory access

0C4h

0C6h

99

01

M

R

MS

DI

IR

IO

T

Power

Misc & IRQ field are present, Vcc

structure

Nominal Operating supply Voltage TPCE_PD

TPCE_FS

Qpower-description

AI

only

PI

SI

H

V

L

V

N

V

0C8h

0CAh

55

64

X

R

Ah

5h

Vcc Nominal is 5V

Support 16/8 bit I/O access,

I/O Address Lines are 16

Vcc Nominal Value

TPCE_IO

Bus 16/8

P

I/O AddrLines

0CCh

F0

S

L

M

V

B

I

N

IRQ Sharing

TPCE_IR

S: Share Logic active

P: Pulse IRQ supported

L: Level IRQ supported

M: Bit Mask of IRQ

0CEh

0D0h

0D2h

FF

20

IRQ Levels to be routed 0-7

recommended

IRQ Levels to be routed 8-15

recommended

TPCE_IR Mask

Extension

TPCE_IR Mask

Extension

X

R

P

R

O

A

T

Power Down supported

TPCE_MI

0D4h

0D6h

0D8h

0DAh

1B

06

01

CISTPL_CFTABLE_ENTRY

Configuration Entry Tuple

Link is 6 bytes

Tuple Code

Link to next tuple

TPCE_INDX

I

D

Configuration Entry Number

M

MS

IR

Q

IO

T

Power

Vcc power-description structure only TPCE_FS

0DCh

21

R

DI

PI

AI

SI

H

V

L

V

N

V

Nominal Operating supply Voltage, TPCE_PD

Maximum Current required averaged

over 10ms

0DEh

0E0h

0E2h

0E4h

0E6h

0E8h

0EAh

B5

1E

4D

1B

0F

C2

41

X

6h

5h

1Vx3

Vcc Nominal Value

1Eh(30d)

Vcc Nominal is 3<3V

Peak I is 45mA

Configuration Entry Tuple

Link is 15bytes

9h

Peak I Value

Tuple Code

Link to next tuple

TPCE_INDX

CISTPL_CFTABLE_ENTRY

I

W

D

R

Configuration Entry Number

P

B

Interface Type

I/O Interface, Bvd & WP not used, TPCE_IF

RDY/BSY active, Wait not used

for memory access

0ECh

0EEh

0F0h

99

01

55

M

R

X

MS

IR

IO

T

Power

Misc & IRQ field are present, Vcc

structure

Nominal Operating supply Voltage TPCE_PD

TPCE_FS

Qpower-description

AI

only

DI

PI

SI

H

V

L

V

5h

N

V

Ah

Vcc Nominal is 5V Vcc Nominal Value

27

White Electronic Designs Corporation (508) 485-4000 wwwꢀwhiteedcꢀcom

Flash Cards

ATA45 Series

White Electronic Designs

CARD INFORMATION STRUCTURE CONTꢀ

AttributeOffset

Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

0F2h

EA

R

Bus 16/8

I/O AddrLines

I/O range description, Support

16/8 bit I/O access, A 1 Kbyte

I/O address space

TPCE_IO

0F4h

61

Size of

length

Size of

address

Number of I/O

Address Ranges

Length is 1 byte long, Address is

2 byte long, 1 I/O Address Range Byte

Description field

I/O Range Description

0F6h

0F8h

0FAh

0FCh

0FEh

100h

102h

F0

01

07

F6

03

01

EE

Start of I/O Address Block First(LSB)

Start of I/O Address Block First(MSB)

First I/O Range Length

Start of I/O Address Block Second(LSB)

Start of I/O Address Block Second(MSB)

Second I/O Range Length

S

P

L

M

V

B

I

N

IRQ Sharing

TPCE_IR

S: Share Logic active,

P: Pulse IRQ supported,

L: Level IRQ supported,

V: Vendor-Specific supported,

B: Bus-Error supported,

I: I/O-check supported

104h

20

X

R

P

R

O

A

T

Power Down supported

TPCE_MI

106h

108h

10Ah

10Ch

1B

06

02

01

CISTPL_CFTABLE_ENTRY

Configuration Entry Tuple

Link is 6bytes

Tuple Code

Link to next tuple

TPCE_INDX

TPCE_FS

I

D

Configuration Entry Number

M

MS

IR

I

T

Power

Vcc power-description structure

QO

only

10Eh

21

R

DI

PI

AI

SI

H

V

L

V

N

V

Nominal Operating supply Voltage, TPCE_PD

Maximum Current required

averaged over 10ms

110h

112h

114h

116h

118h

11Ah

11Ch

B5

1E

4D

1B

0F

C3

41

X

6h

1Eh(30d)

9h

5h

1Vx3

Vcc Nominal Value

Vcc Nominal is 3<3V

Peak I is 45mA

Configuration Entry Tuple

Link is 15bytes

Peak I Value

Tuple Code

Link to next tuple

TPCE_INDX

CISTPL_CFTABLE_ENTRY

I

W

D

R

Configuration Entry Number

P

B

Interface Type

I/O Interface, Bvd & WP not used, TPCE_IF

RDY/BSY active, Wait not used

for memory access

11Eh

120h

99

01

M

R

MS

IR

QO

AI

I

T

Power

Misc & IRQ field are present, Vcc TPCE_FS

power-description

structure

only

DI

PI

SI

H

V

L

V

N

V

Nominal Operating supply Voltage TPCE_PD

122h

124h

55

EA

X

R

Ah

5h

Vcc Nominal is 5V

Vcc Nominal Value

TPCE_IO

Bus

16/8

I/O AddrLines

I/O range description, Support

16/8 bit I/O access, A 1 Kbyte I/O

address space

White Electronic Designs Corporation Marlborough, MA (508) 485-4000

28

Flash Cards

ATA45 Series

White Electronic Designs

CARD INFORMATION STRUCTURE CONTꢀ

AttributeOffset

Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

126h

61

Size of

length

Size of

address

Number of I/O

Address Ranges

Length is 1 byte long, Address is

2 byte long, 1 I/O Address Range

Description field

I/O Range Description

Byte

128h

12Ah

12Ch

12Eh

130h

132h

134h

70

01

07

76

03

01

EE

Start of I/O Address Block First (LSB)

Start of I/O Address Block First (MSB)

First I/O Range Length

Start of I/O Address Block Second(LSB)

Start of I/O Address Block Second(MSB)

Second I/O Range Length

S

P

L

M

V

B

I

N

IRQ Sharing

TPCE_IR

TPCE_MI

S: Share Logic active,

P: Pulse IRQ supported,

L: Level IRQ supported,

V: Vendor-Specific supported,

B: Bus-Error supported,

I: I/O-check supported

136h

20

X

R

P

R

O

A

T

Power Down supported

138h

13Ah

13Ch

13Eh

1B

06

03

01

CISTPL_CFTABLE_ENTRY

Configuration Entry Tuple

Link is 6bytes

Tuple Code

Link to next tuple

TPCE_INDX

TPCE_FS

I

D

Configuration Entry Number

M

MS

IR

I

T

Power

Vcc power-description structure

QO

only

140h

21

R

DI

PI

AI

SI

H

V

L

V

N

V

Nominal Operating supply Voltage, TPCE_PD

Maximum Current required

averaged over 10ms

142h

144h

146h

148h

14Ah

14Ch

B5

1E

4D

14

X

6h

1Eh(30d)

9h

5h

1Vx3

Vcc Nominal Value

Vcc Nominal is 3<3V

Peak I is 45mA

Peak I Value

Tuple Code

CISTPL_NO_LINK

No Bytes Following

End of CIS Tuple Chain

No Link to Common Memory

Link Length is 0 byte

End of CIS

00

Link to next tuple

Tuple Code

FF

29

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Flash Cards

ATA45 Series

White Electronic Designs

TRUE IDE TO PCMCIA INTERFACE

True IDE

40pin

RESET

GND

D7

PCMCIA ATA

No(#)

1

No(#)

68pin

58

RESET

2

1,8,9,11,12,22,23,24,25,26,34,35,68, (56)

GND, A10-A3, OE, CSEL (56)

3

6

D7

4

D8

64

D8

5

D6

5

D6

6

D9

65

D9

7

D5

4

D5

8

D10

66

D10

9

D4

3

D4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

D11

27

D11

D3

2

D3

D12

38

D12

D2

32

D2

D13

39

D13

D1

31

D1

D14

40

D14

D0

30

D0

D15

41

D15

GND

(keypin)

DMACK

GND

IOWR

GND

IORD

GND

IORDY

CSEL

DMACK

GND

IREQ16

IOIS16

A1

1,8,9,11,12,22,23,24,25,26,34,35,68, (56)

GND, A10-A3, OE, CSEL(56)

60

INPACK

1,8,9,11,12,22,23,24,25,26,34,35,68, (56)

GND, A10-A3, OE, CSEL(56)

45

IOWR

1,8,9,11,12,22,23,24,25,26,34,35,68, (56)

GND, A10-A3, OE, CSEL(56)

44

IORD

1,8,9,11,12,22,23,24,25,26,34,35,68, (56)

GND, A10-A3, OE, CSEL(56)

59

WAIT

56

CSEL

61

REG

1,8,9,11,12,22,23,24,25,26,34,35,68, (56)

GND, A10-A3, OE, CSEL(56)

RDY/BSY

33

WP

28

A1

PDIAG

A0

63

BVD1

29

A0

A2

27

A2

CS0

7

CS0

CS1

42

CS1

DASP

GND

62

BVD2

1,8,9,11,12,22,23,24,25,26,34,35,68, (56)

GND, A10-A3, OE, CSEL(56)

White Electronic Designs Corporation Marlborough, MA (508) 485-4000

30

Flash Cards

ATA45 Series

White Electronic Designs

PRODUCT MARKING

WED 7P016ATA4503C25 C995 0322

COMPANYNAME

PARTNUMBER

LOT CODE/TRACE NUMBER

DATECODE

PART NUMBERING

7 P 256 ATA45 03 C 25

CARD TECHNOLOGY

7

8

FLASH

SRAM

PC CARD

P

R

Standard

Ruggedized

CARDCAPACITY

256 256MB

CARD FAMILY AND VERSION

PACKAGINGOPTION

03 Standard WEDC logo type II

TEMPERATURERANGE

C = Commercial 0°C to +70°C

CARD ACCESS TIME

25 250ns

31

White Electronic Designs Corporation (508) 485-4000 wwwꢀwhiteedcꢀcom

Flash Cards

ATA45 Series

White Electronic Designs

ORDERING INFORMATION

7P XXX ATA45 SS T ZZ

XXX (unformatted capacity)

008 8MB

016 16MB

032 32MB

048 48MB

064 64MB

096 96MB

128 128MB

256 256MB

512 512MB

ATA45

Samsung based

SS

03

04

05

WEDC Flash ATA logo Type II

Blank Housing Type II

Blank Housing Type II Recessed

T

C

Commercial Temperature Range

250ns

ZZ

25

White Electronic Designs Corporation Marlborough, MA (508) 485-4000

32

Flash Cards

ATA45 Series

White Electronic Designs

Document Title

Flash Cards ATA45 Series

Revision History

Rev level

Description

Initial release

Date

Rev 0

May 16, 2003

33

White Electronic Designs Corporation (508) 485-4000 wwwꢀwhiteedcꢀcom

厂商	型号	描述	页数
WEDC	7P001FEA0200C15	[ Flash Card, 1MX8, 150ns, CARD-68 ]	6 页
WEDC	7P001FEA0300C15	[ Flash Card, 1MX8, 150ns, CARD-68 ]	6 页
WEDC	7P001FLG0100C15	[ Flash Card, 512MX16, 150ns, CARD-68 ]	11 页
ETC	7P001FLG0100C20	周边其他\n[ Peripheral Miscellaneous ]	13 页
WEDC	7P001FLG0100I15	[ Flash Card, 512MX16, 150ns, CARD-68 ]	11 页
WEDC	7P001FLG0100I20	[ Flash Card, 512MX16, 200ns, CARD-68 ]	11 页
WEDC	7P001FLG0101C15	[ Flash Card, 512MX16, 150ns, CARD-68 ]	11 页
WEDC	7P001FLG0101C20	[ Flash Card, 512MX16, 200ns, CARD-68 ]	11 页
WEDC	7P001FLG0101I15	[ Flash Card, 512MX16, 150ns, CARD-68 ]	11 页
ETC	7P001FLG0101I20	周边其他\n[ Peripheral Miscellaneous ]	13 页