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TZA3054A

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

Rev. 01 — 12 August 2004

Objective data sheet

1. General description

The TZA3054A is a highly sensitive A-rate™ Limiting ampliﬁer featuring ACE (Automatic

Current Engine) functionality, Logarithmic Level Detect (LLD), Loss-of-Signal (LOS)

detector and output jam function. The ACE functionality provides a limiting ampliﬁer which

achieves optimum performance (sensitivity, bandwidth, jitter and output eye pattern) for

any bit rate with very low power consumption. This is achieved through automatic

adjustment of the input bandwidth and the output slew rate by using built-in performance

monitors. Manual adjustment is possible by programming the I²C-bus registers.

The integrated I²C-bus controller allows for ﬂexible conﬁguration with a microcontroller,

which minimizes the number of external connections and external components needed.

Adjustment of the LOS threshold can be done either via the I²C-bus or with an external

resistor. The output amplitude is selectable between a high or low value, or adjustable via

the I²C-bus. The detected logarithmic signal level is indicated directly by a voltage on pin

LLD, or by a binary value of an I²C-bus register. Furthermore, the junction temperature,

the internal supply voltage and an external voltage can all be monitored through a built-in

Analog-to-Digital Converter (ADC) which supports several diagnostic functions.

These features make the TZA3054A ideally suited for application in modules, including

Small Form Factor (SFF/SFP/iSFP) modules.

The TZA3054A comes in a compact 3 × 4 mm²HVQFN20 package, with the exposed die

pad serving as the main ground connection.

2. Features

■ A-rate limiting ampliﬁer; supporting any data rate between 100 Mbit/s and 3.2 Gbit/s,

including data rates such as OC3, OC48, FC, 2FC and GE

■ Very low power

■ I²C-bus programmable

■ Highly sensitive data input with 2.5 mV sensitivity

■ On-chip DC offset compensation without external capacitor

■ Automatic bandwidth and slew rate adjustment (ACE)

■ Pin selectable output level, 500 mV or 1500 mV (p-p) differential

■ Rise and fall times 40 ps typical at 3.2 Gbit/s

■ Deterministic Jitter typically below 10 ps (p-p)

■ Logarithmic Level Detect (LLD) from 1 mV to 1200 mV

■ Input amplitude related Loss Of Signal (LOS) indicator with adjustable threshold

■ 2.9 V to 3.5 V supply voltage

■ SFF-8074i and SFF-8472 compliant

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

■ Additional features with I²C-bus:

◆ Microcontroller controllable

◆ Temperature readout

◆ Supply voltage readout

◆ Logarithmic level detect readout

◆ External voltage readout

◆ Readout calibration

◆ Adjustable output level from 0 mV to 2000 mV (p-p) differential

◆ Adjustable LOS threshold without external components

◆ Programmable LOS hysteresis

◆ Offset compensation disable

◆ Status and interrupt reporting

◆ Polarity inversion

◆ Conﬁgurable LOS and JAM I/Os

◆ Auto Jam

◆ Adjustable bandwidth and slew rate.

3. Applications

■ Fiber optic modules: SFP, SFF, GBIC, 1 × 9 and 2 × 9

■ Digital ﬁber optic receivers for Fiber Channel (FC), gigabit ethernet, inﬁniband and

telecom applications.

4. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

TZA3054AHN

HVQFN20 plastic heat sink bottom chip carrier; 20 leads; SOT797-1

body 3 × 4 × 0.65 mm

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

2 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

5. Block diagram

TZA3054A

8

SCL

SDA

INTERRUPT/

STATUS

READOUT

2

I C-BUS

7

INTERFACE

5

EXT

T

j

19

RREF

REFERENCE

CIRCUITS

DIAGNOSTIC

READOUT

ADC

LOS

V

CC

17

LOSTH

9

2

I C-bus

LOS

LLD

18

LLD

2

3

13

12

BANDWIDTH

ADJUSTMENT

LIMITING

AMPLIFIER

SLEW RATE

RF

OUTPUT

OUT

IN

OUTQ

INQ

2

I C-bus

10

16

JAM

LVL

2

I C-bus

2

I C-bus

001aab364

Fig 1. Block diagram.

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

3 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

6. Functional diagram

Tj > 125 C

T-alarm

8

SCL

INTERRUPT/

STATUS

READOUT

2

V

< 3.0 V

CC

I C-BUS

VCC-alarm

7

INTERFACE

SDA

666 kΩ

5

EXT

ADC

ADC-EXT

T

j

19

RREF

ADC

ADC-TJ

REFERENCE

CIRCUITS

333 kΩ

V

CC

ADC-VCC

ADC-LOSTH

ADC-LLD

TZA3054A

I2CLOSTH

LOSIOTYPE

17

LOSTH

VLOSTH

LLD

LOS

9

1, 4

LOS

LLD

V

DAC

LOSTH

CCI

0 to 7 dB

6, 15, 20, 21

LOSPOL

HYST

GND

18

LLD

11, 14

V

CCO

75 Ω

2

IN

13

BANDWIDTH

ADJUSTMENT

LIMITING

AMPLIFIER

SLEW RATE

SLEWOCT

RF

OUTPUT

50 Ω

OUT

50 Ω

12

3

OUTQ

INQ

1.6 V

10 pF

OFFSET

POLINV

BWOCT

AUTOJAM

V

CC

JAMPOL

I2CJAM

10

16

JAM

LVL

JAM

V

CC

I2CRFLVL

RFLVL

001aab373

Fig 2. Functional diagram.

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

4 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

7. Pinning information

7.1 Pinning

terminal 1

index area

1

2

3

4

14

13

12

11

V

CCO

CCI

IN

OUT

TZA3054A

INQ

OUTQ

V

CCO

CCI

001aab365

Transparent top view

Fig 3. Pin conﬁguration.

7.2 Pin description

Table 2:

Pin description

Symbol Pin

Description

V_CCI

IN

1

supply voltage for RF input part

non-inverted RF input

2

INQ

3

inverted RF input

V_CCI

EXT

GND

SDA

SCL

LOS

JAM

V_CCO

OUTQ

OUT

V_CCO

GND

LVL

4

supply voltage for RF input part

external voltage input

5

6

ground

7

I²C-bus data signal bi-directional

I²C-bus clock signal input

LOS open-drain output (active LOW)

jam input (active LOW)

8

9

10

11

12

13

14

15

16

17

18

19

20

21

supply voltage for RF output part; analog part and digital part

inverted RF output

non-inverted RF output

supply voltage for RF output part; analog part and digital part

ground

RF output signal level select

LOSTH

LLD

loss of signal threshold adjustment

logarithmic level detection

RREF

GND

reference pin; for generating an external resistor related precision current

ground

RF ground plus die pad

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

5 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

8. Functional description

8.1 RF input

The TZA3054A is a highly sensitive limiting ampliﬁer with an input voltage range from

2.5 mV to 1200 mV (p-p) Single-Ended (SE). It is assumed that the inputs, requiring

AC-coupling, carry a complementary signal with the speciﬁed peak-to-peak value (true

differential excitation).

1 V

TZA3054A

IN

50 Ω

1.6 V

10 pF

INQ

die pad (21)

001aab366

Fig 4. RF input conﬁguration.

The TZA3054A includes a DC offset cancellation loop with a very low bandwidth of

approximately 1 kHz. The TZA3054A can support transmission standards allowing

extremely long sequences of consecutive identical bits by disabling the DC offset

cancellation, but at the expense of reduced sensitivity. The DC offset cancellation can be

disabled with I²C-bus bit OFFSET in I²C-bus register LIMCNF (12H). This also allows for

burst mode applications.

As part of the ACE functionality, the TZA3054A has an automatic bandwidth adjustment

loop to achieve optimum performance over temperature at all bit rates. This means that

the input bandwidth is reduced automatically at lower bit rates. Wide band noise of the

optical front-end (photo detector and transimpedance ampliﬁer) is thus reduced for lower

bit rates.

The automatic bandwidth adjustment of the input stage can be overruled by manual

settings via the I²C-bus. This may be needed in the event of non-randomized or

burst-mode signals; see Section 8.6.

8.2 Logarithmic level detect

The signal strength at the input is measured with a Logarithmic Level Detector (LLD) and

presented at pin LLD. The LLD reading has a sensitivity (S_LLD) of typically 17 mV/dB for a

V_i(p-p)(SE)range of 1 mV to 1200 mV, which is available as a voltage on pin LLD, or can be

retrieved from the I²C-bus register 0Ah in binary form.

V_{IN(p – p)}

V_LLD= V_LLD= V_{LLD(10 mV)}+ S_LLD× 20LOG

, (expressed in mV).

-----------------------

10 mV

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

1220

LLD

V

(mV)

880

540

200

S

LLD

1

10

100

1000

V

(mV)

IN(p-p)

001aab367

Fig 5. LLD voltage as a function of the RF input voltage.

8.3 Loss of signal indicator

Besides the analog LLD output, a digital LOS indication circuit is also incorporated in the

TZA3054A. The LLD level is internally compared with a loss of signal threshold, which can

be set via an external resistor connected to pin LOSTH (this is the default mode after

power-up) or by means of an internal Digital-to-Analog Converter (DAC). If the DAC is

used, programmed with I²C-bus bit I2CLOSTH in I²C-bus register LOSCNF (10h), the

value of the required threshold needs to be programmed into the I²C-bus register LOSTH

(11h). The default value is 00h, so no LOS can be generated.

If the received signal strength is below the threshold value the LOS open-drain output will

be pulled LOW. The LOS open-drain output requires an external pull-up resistor in the

range of 4.7 kΩ to 10 kΩ. A default hysteresis of 3 dB is applied in the comparator.

I²C-bus register LOSCNF (10h) provides more ﬂexibility, e.g. a programmable hysteresis

of 0 dB to 7 dB in steps of 1 dB, a CMOS style LOS output instead of the default

open-drain conﬁguration and programmable LOS polarity. These features provide

“any-interface” in the application; see Figure 6.

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

7 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

V

CCO

CONTROL

LOGIC

AND

LEVEL

SHIFT

ESD

CLAMP

LOS

GND

polarity

001aab368

CMOS/

open-drain

Fig 6. LOS output conﬁguration.

8.4 Setting LOSTH reference level by external resistor

V

CCO

LLD

1.23 V

LOS

V

ref

LOS compare

RREF

LOSTH

R1

10 kΩ

I

R2

GND

001aab369

R2 ≤ R1

Fig 7. Setting the LOSTH reference level by external resistors.

The loss of signal threshold can also be programmed by applying an external voltage to

pin LOSTH (this is the default mode after power-up). The reference voltage level at pin

LOSTH can be set by connecting an external resistor (R2) from the pin to ground. The

voltage on the pin is determined by the resistor ratio between R2 and R1; see Figure 7.

For resistor R1 the value must be 10 kΩ, with 1 % accuracy, thus yielding a current of

R2

123 µA. The LOSTH voltage equals

× V

.

ref

------

R1

Voltage V_refrepresents a temperature stabilized and accurate reference voltage of 1.23 V.

The minimum threshold level corresponds to 0 V and the maximum to 1.23 V. Hence, the

value of R2 may not be higher than R1. The accuracy of the LOSTH voltage depends

mainly on the matching of the two external resistors.

Apart from using resistors (R1 and R2) to set the LOS threshold an accurate external

voltage source can also be used, provided that it has a low output impedance.

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

8 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

The omission of R2 results in maximum LOS threshold, thereby generating LOS

constantly. LOSTH may be short-circuited to ground to circumvent this situation. If the

I²C-bus DAC is used, R2 may be omitted or connected to ground.

1000

V

IN(p-p)

100

LOS

10

1

200

540

880

1220

V

(mV)

LOSTH

001aab370

Fig 8. RF input voltage as a function of the LOSTH voltage.

8.5 RF output

TZA3054A

V

CCO

75 Ω

OUT

50 Ω

OUTQ

I

swing

001aab371

Fig 9. RF output conﬁguration.

The RF CML output has a programmable signal amplitude between 500 mV to

2000 mV (p-p) (differential) in 7 steps of 250 mV, by I²C-bus bits RFLVL[2:0] (I²C-bus

register RFLVL; 13h). The output can also be switched off using this RFLVL register: this

might be useful to save power in case only the LLD and LOS functions of the TZA3054A

are used in the application. The default amplitude is 1500 mV (p-p, differential).

Furthermore, the termination scheme can be either DC or AC-coupled.

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

9 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

If the I²C-bus setting for the output level is set to pin selection, the signal amplitude of the

output buffer can be selected from two ﬁxed values. By applying a HIGH level to pin LVL

1570 mV (p-p, differential) is selected (this is the default mode after power-up due to the

internal pull-up resistor). By applying a LOW level to pin LVL 500 mV (p-p, differential) is

selected.

As part of the ACE functionality, the slew rate of the output is adjusted automatically for

any bit rate to approximately 10 % of the corresponding Unit Interval time, by a built-in

slew rate control loop. The slew rate control loop eases ElectroMagnetic Compatibility

(EMC) and ElectroMagnetic Interference (EMI) compliance of the ﬁnal module design, as

well as dramatic power saving, especially for lower bit rates. To estimate the power

dissipation use Figure 17 Core supply current as a function of bit rate, and Figure 18 RF

output supply current as a function of output voltage swing. By adding both independent

currents the total supply current can be calculated.

The automatic slew rate adjustment can be overruled by manual setting of the output

stage via the I²C-bus. This may be required in the event of non-randomized or burst-mode

signals; see the Section 8.6.

8.5.1 JAM

The RF output can be forced into the logic 0 state by applying a LOW-level to the JAM pin

(pin JAM is active LOW). Hence in the event of a loss of signal situation, the output can be

jammed to suppress the ampliﬁed noise from the optical front-end. The JAM pin has an

internal pull-up, to prevent jamming of the output if the JAM pin is not connected.

If CMOS compatibility is required, pin JAM can be programmed to be active HIGH with

I²C-bus bit JAMPOL (I²C-bus register RFLVL; 13h).

Jamming can also be done via the I²C-bus, using I²C-bus bit I2CJAM to enable this

function and I²C-bus bit JAM to actually jam the output (I²C-bus register RFLVL; 13h).

JAM can also be programmed to work automatically when loss of signal occurs. This can

be done by connection pin LOS to pin JAM directly or with I²C-bus bit AUTOJAM (I²C-bus

register RFLVL; 13h).

V

CCO

CMOS

input

SECONDARY

ESD CLAMP

GND

001aab372

Fig 10. CMOS input conﬁguration.

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

10 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

8.5.2 Diagnostic support

The TZA3054A supports several diagnostic functions, including:

• Junction temperature

• Supply voltage

• Input signal strength (LLD)

• External voltage (EXT input).

The junction temperature, supply voltage, LLD voltage and an external voltage (EXT

input) can be measured with a built-in 8-bit ADC, based on the successive approximation

principle. The value of the measured quantity can then be read in the appropriate ADC

result register. A supervisory algorithm can be implemented in a microcontroller, to realize

the required diagnostic functionality e.g. the i-SFP standard, SFF-8472.

8.5.2.1 Junction temperature

The junction temperature can be measured in a range of −40 °C to +85 °C with

approximately 3 °C resolution. The result can be read from ADC register 08h. The

following formula can be applied to convert the ADC reading into a temperature:

T = 478.43 − 2.93 × ADC_value

.

8.5.2.2 Supply voltage

The supply voltage can be measured in a range of 2.4 V to 3.7 V with approximately 5 mV

resolution. The result can be read from ADC register 09h. The formula to convert the ADC

reading into the supply voltage is: V_CC= 2.4 + 4.82 × 10⁻³× ADC_value

.

8.5.2.3 LLD voltage

The LLD voltage can be measured from 0 mV to 1200 mV with approximately 5 mV

resolution. The result can be read from ADC register 0Ah. The formula to convert the ADC

reading into the supply voltage is: V_LLD= 4.82 × 10⁻³× ADC_value. The LLD voltage can be

converted to an input voltage by using Figure 5.

8.5.2.4 External voltage

The external input voltage (EXT) can be measured between 0 V and 3.6 V with

approximately 15 mV resolution. The result can be read from ADC register 0Bh. The

formula to convert the ADC reading into the supply voltage is:

V_EXT= 14.45 × 10⁻³× ADC_value

.

8.5.3 Power supply connections

Two separate supply domains (V_CCIand V_CCO) provide isolation between the various

functional blocks of the TZA3054A. Each supply domain should be connected to a

common V_CCvia a separate ﬁlter. All supply and ground pins, including the exposed

die pad, must be connected. The die pad should be connected with the lowest

inductance possible. Since the die pad is also used as the main ground return of the chip,

the connection should also have a low DC impedance. The voltage supply levels should

be in accordance with the values speciﬁed in Section 11.

All external components should be surface mounted devices, preferably of size 0603 or

smaller. The components must be mounted as close to the IC as possible, especially

supply decoupling capacitors.

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

11 of 32

TZA3054A

Philips Semiconductors

8.5.4 Power-up

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

At power-up an internal safe condition signal is generated once the V_CCvoltage is

sufﬁciently high for proper operation and the internal reference voltage has settled. This

signal is used to generate a Power-On-Reset (POR) signal that resets all internal circuits

to their default value.

8.5.5 Default at power-up

All I²C-bus registers are reset to their default setting at power-up, which are:

• DC offset compensation: on

• Automatic bandwidth adjustment (ACE on)

• Automatic slew rate adjustment (ACE on)

• Pin adjustable / selectable LOSTH, JAM and LVL

• LOS hysteresis 3 dB

• LOS output open drain (active LOW)

• JAM active LOW.

8.5.6 Interrupt controller

The TZA3054A features an interrupt controller, based on status ﬂags. These ﬂags are:

• Loss of signal

• Temperature alarm (> 125 °C with a hysteresis of approximately 4 °C)

• Supply voltage alarm (< 2.85 V with a hysteresis of approximately 50 mV).

The controller contains two I²C-bus registers, namely the I²C-bus interrupt register

(INTERRUPT at address 00h) and the I²C-bus status register (STATUS at address 01h).

The I²C-bus interrupt register stores the history, while the I²C-bus status register always

shows the present state of the receiver.

The I²C-bus interrupt and status registers can be polled by an I²C-bus read action. The

read action of the I²C-bus interrupt register clears all interrupt ﬂags. If the alarm condition

is still present, the ﬂag is immediately reset in the I²C-bus interrupt register. The I²C-bus

status register is not reset since it always shows the present state of the TZA3054A.

8.5.7 I²C-bus

The chip can be conﬁgured by using the I²C-bus connections SDA and SCL.

The I²C-bus address of the TZA3054A is D2h for writing and D3h for reading.

A detailed list of all I²C-bus registers and an explanation of their contents is given in

Section 8.7.

During power-up, all I²C-bus registers are reset to their default value as indicated in

Table 3.

Table 3:

I²C-bus address of TZA3054A

A6

A5

A4

A3

A2

A1

A0

R/W

1

0

1

0

1

X

9397 750 13466

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Rev. 01 — 12 August 2004

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

8.6 Manual settings

In the default operating mode of the TZA3054A ACE is switched on. This means that the

input bandwidth and output slew rate are adjusted automatically using the built-in

performance monitors. This allows for an optimum performance over the temperature

range at all bit rates in combination with very low power consumption.

As well as the fully automatic mode, two other modes are available:

• Semi-automatic mode: manual selection of bit rate range with automatic bandwidth

and slew rate adjustment within this range

• Full manual mode: manual selection of bandwidth and slew rate values.

Control is done via two I²C-bus registers: BW (15h) for the input stage and SLEW (14h)

for the output stage. Each register contains two control parameters: performance monitor

control (BW[4:0] and SLEW[4:0] respectively) and the octave selection (BWOCT[2:0] and

SLEWOCT[2:0] respectively).

An overview of the possible modes and the I²C-bus control values is given in Table 4. The

typical behavior of the rise and fall time in the different modes is illustrated in Figure 13. A

similar picture can be made for the input bandwidth.

Table 4:

Mode

The possible modes and the I²C-bus control values

SLEW[4:0] =

BW[4:0] = variable

BW[4:0] = 00000

SLEWOCT[2:0] = BWOCT[2:0] = 111

fully automatic

semi-automatic

not applicable

manual mode

SLEWOCT[2:0] = BWOCT[2:0] = variable

8.6.1 Fully automatic mode: automatic bandwidth and slew rate adjustment over

all bit rates

In the default and fully automatic mode SLEWOCT[2:0] and BWOCT[2:0] are equal to

111, which means that ACE is switched on.

By default, the performance monitor control values BW[4:0] and SLEW[4:0] are set to

01011. This leads to a bandwidth that is equal to approximately 70 % of the input data

rate, and the slew rate is adjusted so that the rise and fall times are equal to approximately

0.1 UI.

This mode gives a good trade off between performance and power consumption and is

the recommended setting.

Optimization of the relative bandwidth and relative slew rate is possible by changing the

BW[4:0] and OCT[4:0] values.

A low value for the bits BW[4:0] means that the bandwidth is maximized but still adjusted

according to the incoming bit rate. Increasing the value means that the bandwidth will be

smaller. This allows for optimization of the input stage with respect to the used optical

receiver, i.e. (A)PD + TIA; see Figure 11.

A similar approach is possible with the bits SLEW[4:0]. A low value give fast edges on the

output stage while increasing the value minimizes the slew rate. This allows for

optimization of the output stage with respect to EMI/EMC and power consumption; see

Figure 12.

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

G

BW = 11111

BW = 00001

f

B

i

001aab376

Fig 11. Adapting the bandwidth control.

001aab377

4

10

t , t

r

f

(ps)

3

2

10

(1)

(2)

10

2

3

4

10

bit rate (Mbit/s)

(1) Slew = 00001.

(2) Slew = 11111.

The values are not based on measurements.

Fig 12. Adapting the slew rate control.

8.6.2 Semi-automatic mode: manual selection of bit rate range with automatic

bandwidth and slew rate adjustment within this range

In this mode, the range of bit rates where the automatic selection of bandwidth and slew

rate is operating is limited. However, within this range of bit rates, the optimum bandwidth

and slew rate are automatically chosen.

This mode can be achieved by setting the SLEWOCT[2:0] and BWOCT[2:0] bits to the

required range of bit rates. The ACE functionality is operating but limited to this range of

bit rates.

Again, with the bits SLEW[4:0] and BW[4:0] further optimization of the relative bandwidth

and relative slew rate is possible.

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

t , t

r

t , t

r f

f

fully

automatic

mode

competitor

behavior

Mbit/s (MHz)

t , t

r

semi

automatic

mode

t , t

r f

manual

mode

f

Mbit/s (MHz)

001aab378

Fig 13. Graphic overview of all modes for rise and fall time adjustment.

8.6.3 Full manual mode: manual selection of bandwidth and slew rate

By setting both BW[4:0] and SLEW[4:0] to 00000, the automatic bandwidth and the slew

rate adjustment of the TZA3054A are completely switched off and the values for the

bandwidth and slew rate can be controlled manually.

The bandwidth of the input stage and the slew rate of the output stage can be controlled

with the bits BWOCT[2:0] in I²C-bus register BW (15h) and the bits SLEWOCT[2:0] in

I²C-bus register SLEW (14h) respectively. By using the values given in Table 14 and

Table 15 the right settings can be chosen.

In this mode the user gets 6 different limiting ampliﬁers, all optimized for their respective

bandwidth range. The bandwidth spans from 1 kHz to the highest frequency of the chosen

octave.

In the event that the DC cancellation loop is disabled as well, the lowest frequency is

determined by the input coupling capacitor in combination with the input impedance. This

enable burst mode operation.

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Philips Semiconductors

8.7 I²C-bus

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

General characteristics of the I²C-bus can be found in “The I²C-bus speciﬁcation”, version

2.1, January 2000, available at “http://www.semiconductors.philips.com/buses/”.

Table 5:

I²C-bus address (D2h)

A7

A6

A5

A4

A3

A2

A1

R/W

1

0

1

0

1

X

The TZA3054A contains both read only registers and read / write registers; see Table 6.

Table 6:

Address

00h

Address of all registers

Name

Function

R/W

R

Default

00h

INTERRUPT

STATUS

ADC_TJ

interrupt register

status register

01h

R

00h

08h

junction temperature ADC

result register

R

00h

09h

0Ah

0Bh

ADC_VCC

ADC_LLD

ADC_EXT

supply voltage ADC result

register

R

00h

logarithmic level detect

ADC result register

external voltage ADC result R

register

0Ch

10h

ADC_LOSTH

LOSCNF

los threshold result register R

00h

23h

loss of signal detector

conﬁguration register

R/W

11h

12h

13h

14h

15h

LOSTH

LIMCNF

RFLVL

SLEW

BW

loss of signal threshold

register

R/W

00h

B6h

15h

08h

limiter conﬁguration

register

RF output conﬁguration

register

RF output slew rate control R/W

register

RF bandwidth control

register

R/W

8.7.1 Write protocol

During a write action, the I²C-bus controller in the TZA3054A allows one or more registers

to be written to. Specifying the register address before writing the data is mandatory for

each register; see Figure 14.

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Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

R/W

0 A

S

slave address

register address

A

data

A

P

n bytes

001aab379

Fig 14. Write protocol.

8.7.2 Read protocol

During a read action, the I²C-bus controller in the TZA3054A automatically increments the

address pointer (auto-increment), allowing sequential registers to be read in a quick

fashion; see Figure 15. Auto-increment reading is not possible when reading the ADC

registers (08h, 09h, 0Ah, 0Bh and 0Ch); see Figure 16.

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

R/W

1 A

S

slave address

0 A

register address

A

RS

slave address

acknowledge

from master

not acknowledge

from master

data

A

data

A

P

bytes 1 to (n−1)

byte n

001aab380

Fig 15. Auto-increment reading.

start of reading

1st ADC register

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

R/W

S

slave address

0 A

register address

A

RS

slave address

1 A

data

A

P

start of reading

2nd ADC register

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

not acknowledge

from master

R/W

1 A

S

slave address

0 A

register address

A

RS

slave address

data

A

P

001aab381

Fig 16. Example of reading two ADC registers.

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

Table 7:

Bit

INTERRUPT - I²C-bus register (address 00h) bit description

Symbol

Description

7 to 3

2

-

reserved

LOS

Loss Of Signal

1 = no signal present (loss of signal condition)

0 = signal present (default value)

1

0

VCCALARM supply voltage alarm

1 = supply voltage < 3.0 V

0 = supply voltage 3.0 V (default value)

temperature alarm

TALARM

1 = junction temperature ≥ 125 °C

0 = junction temperature < 125 °C (default value)

Table 8:

Bit

STATUS - I²C-bus register (address 01h) bit description

Symbol

Description

7 to 3

2

-

reserved

LOS

Loss Of Signal

1 = no signal present (loss of signal condition)

0 = signal present (default value)

1

VCCALARM supply voltage alarm

1 = supply voltage < 3.0 V

0 = supply voltage 3.0 V (default value)

temperature alarm

0

TALARM

Table 9:

Bit

ADC - I²C-bus register (address 08h. 09h, 0Ah, 0Bh and 0Ch) bit description

Symbol

Description

7 to 0

ADC[7:0]

analog-to-digital conversion result^[1]

1 = maximum value

0 = minimum value (default value)

[1] For corresponding values, see Section 8.5.2.

Table 10: LOSCNF - I²C-bus register (address 10h; default value = 23h) bit description

Bit

7

Symbol

Description

-

reserved

6

LOSIOTYPE loss of signal output polarity

1 = CMOS

0 = open-drain (default value)

5

4

LOSPOL

loss of signal output polarity

1 = inverted (active LOW) (default value)

0 = CMOS (active HIGH)

reserved

-

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

Table 10: LOSCNF - I²C-bus register (address 10h; default value = 23h) bit description

Bit

Symbol

I2CLOSTH loss of signal detection

1 = loss of signal detection set by I²C-bus

Description

3

0 = loss of signal detection set by pin LOSTH (default value)

2 to 0

HYST[2:0]

loss of signal detection hysteresis (default value = 011)

000 = 0 dB

001 = 1 dB

010 = 2 dB

011 = 3 dB

100 = 4 dB

101 = 5 dB

110 = 6 dB

111 = 7 dB

Table 11: LOSTH - I²C-bus register (address 11h; default value = 00h) bit description

Bit

Symbol

LOSTH[7:0] loss of signal detection threshold

1 = maximum LOS threshold, 1228 mV (p-p)

0 = minimum LOS threshold, 0 mV (p-p) (default value)

Description

7 to 0

Table 12: LIMCNF - I²C-bus register (address 12h; default value = B6h) bit description

Bit

7 to 2

1

Symbol

-

Description

reserved

OFFSET

offset control

1 = offset control on (default value)

0 = offset control off

limiter polarity

0

POLINV

1 = inverting

0 = normal (default value)

Table 13: RFLVL - I²C-bus register (address: 13h; default value = 15h) bit description

Bit

Symbol

Description

7

JAMI2C

jam function enabling^[1]

1 = JAM function enabled by I²C-bus

0 = JAM function enabled by pin JAM (default value)

RF output jamming

6

5

JAM

1 = output jammed with logic 0 on output

0 = output not jammed (default value)

jam setting

AUTOJAM

1 = automatic jamming in the event of LOS

0 = no automatic jamming (default value)

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

Table 13: RFLVL - I²C-bus register (address: 13h; default value = 15h) bit description

Bit

Symbol

Description

4

JAMPOL

jam input polarity

1 = inverted (active LOW) (default value)

0 = normal (active HIGH; CMOS)

RF output signal level setting

1 = I²C-bus setting enabled

0 = pin LVL setting enabled (default value)

3

I2CRFLVL

2 to 0

RFLVL[2:0] RF output signal level (default value = 101)

000 = RF output off, no dissipation in output stage

001 = minimum RF output level, 500 mV (p-p) (differential)

111 = maximum RF output level, 2000 mV (p-p) (differential)

[1] Step size 250 mV (p-p) (differential).

Table 14: SLEW - I²C-bus register (address: 14h; default value = E8h) bit description

Bit

Symbol

Description

7 to 5

SLEWOCT[7:5] RF output slew rate octave selection

000 = 3200 to 1800 Mbit/s

001 = 1800 to 900 Mbit/s

010 = 900 to 450 Mbit/s

011 = 450 to 225 Mbit/s

100 = 225 to 112 Mbit/s

101 = 112 to 56 Mbit/s

110 = reserved

111 = fully automatic (default value)

4 to 0

SLEW[4:0]

RF output slew control (default value = 01011)

00000 = automatic slew control off (selection with SLEWOCT)

00001 = maximum slew rate (fastest edges)

11111 = minimum slew rate (slowest edges)

Table 15: BW - I²C-bus register (address: 15h; default value = E8h) bit description

Bit

Symbol

Description

7 to 5

BWOCT[7:5] limiting ampliﬁer bandwidth octave selection

000 = 3200 to 1800 Mbit/s

001 = 1800 to 900 Mbit/s

010 = 900 to 450 Mbit/s

011 = 450 to 225 Mbit/s

100 = 225 to 112 Mbit/s

101 = 112 to 56 Mbit/s

110 = reserved

111 = fully automatic (default value)

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

Table 15: BW - I²C-bus register (address: 15h; default value = E8h) bit description

Bit

Symbol

Description

4 to 0

BW[4:0]

limiting ampliﬁer bandwidth control (default value = 01011)

00000 = automatic bandwidth control off (selection with BWOCT)

00001 = highest bandwidth

11111 = lowest bandwidth

9. Limiting values

Table 16: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).; All voltages are referenced to ground; positive

currents ﬂow into the IC.

Symbol

V_CC

V_n

Parameter

Conditions

Min

−0.3

−1.0

−40

-

Max

Unit

V

supply voltage

+3.5

voltage on all input and output pins

input current on pin

ambient temperature

junction temperature

storage temperature

V_CC+ 0.3

+1.0

V

I_n

mA

°C

T_amb

T_j

+85

110

T_stg

−65

+125

10. Thermal characteristics

Table 17: Thermal characteristics

In compliance with JEDEC standards JESD51-5 and JESD51-7.

Symbol

Parameter

Conditions

Typ

Unit

K/W

R_th(j-a)

thermal resistance from junction to in free air

ambient

53

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

11. Characteristics

Table 18: Characteristics

T_amb= −40 °C to +85 °C; V_CC= 2.9 V to 3.5 V; positive currents ﬂow into the IC; all voltages are referenced to ground; all

values apply to default conﬁguration; ACE on, 2.5 Gbit/s; V_o= 1500 mV (p-p) (diff); LOS and LLD active; no jam; RF input

values are listed as single-ended; RF output values are listed differential; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply: pins V_CCIand V_CCO

V_CC

supply voltage

2.9

3.3

3.5

V

I_CC(core)

core supply current

see Figure 17

[1]

OC48/STM-16; ACE on

OC48/STM-16; ACE off

GE; ACE off

10

9

20

17

12

9

26

21

15

10

90

74

54

38

mA

mW

5

OC3/STM-1; ACE off

OC48/STM-16, ACE on

OC48/STM-16, ACE off

GE, ACE off

5

P_core

core power

dissipation

35

33

20

19

67

57

41

30

OC3/STM-1, ACE off

see Figure 17 and Figure 18

OC48/STM-16, ACE on

OC48/STM-16, ACE off

GE, ACE off

P_tot

total power

dissipation

[1] [2] [3]

110

108

85

146

135

119

108

180

170

145

130

mW

OC3/STM-1, ACE off

75

RF input: pins IN and INQ

V_i(p-p)

input voltage swing

(peak-to-peak value)

limiting output

differential

2.5

-

1200

-

mV

V

[4]

V_i(CM)

input common mode

voltage

1.6

Z_i

input impedance

80

-

100

1

120

-

Ω

f_−3dB

offset compensation

low −3 dB cut-off

frequency

kHz

DR

data rate

100

-

3200

Mbit/s

RF output; pins OUT and OUTQ

V_o(p-p)

output voltage range R_L(ext)= 50 Ω (per pin)

(peak-to-peak value)

400

-

2300

1685

mV

default output voltage R_L(ext)= 50 Ω (per pin)

1440

1570

(peak-to-peak value)

Z_o

output impedance

rise time

single-ended to V_CC

60

-

75

40

0.1

9

90

-

Ω

t_r

20 % to 80 %; ACE OFF

80 % to 20 %; ACE ON

ps

UI

ps

t_f

fall time

-

DJ_(p-p)

deterministic output

jitter

R_L= 50 Ω; V_i= 100 mV;

OC-48; K28.5 pattern

-

(peak-to-peak value)

RJ_(rms)

random output jitter

(RMS value)

R_L= 50 Ω; V_i= 10 mV

-

2

-

ps

9397 750 13466

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Rev. 01 — 12 August 2004

22 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

Table 18: Characteristics …continued

T_amb= −40 °C to +85 °C; V_CC= 2.9 V to 3.5 V; positive currents ﬂow into the IC; all voltages are referenced to ground; all

values apply to default conﬁguration; ACE on, 2.5 Gbit/s; V_o= 1500 mV (p-p) (diff); LOS and LLD active; no jam; RF input

values are listed as single-ended; RF output values are listed differential; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Logarithmic level detect (LLD)

V_i(p-p)

S_LLD

V_LLD

input voltage swing

(peak-to-peak value)

1

-

1200

20

mV

LLD sensitivity

valid for input voltage above

V_i= 10 mV (p-p) (SE)

14

460

17

540

mV/dB

mV

LLD output voltage

V_i= 10 mV (p-p) (SE)

640

Analog output; pin LLD

[4]

Z_o

output impedance

-

2

-

10

−1

1

Ω

I_O(source)

I_O(sink)

LOS detector

output source current

mA

output sink current

-

hys

hysteresis

default value

-

3

-

dB

µs

hysteresis range

assert time

0

-

7

5

t_a

t_d

∆V_i(p-p)= 3 dB

-

de-assert time

-

Open-drain output; pin LOS (default)

V_OL

LOW-level output

voltage

I_OL= 1 mA

0

-

0.2

10

V

I_OH

HIGH-level output

current

V_OH= V_CC

µA

CMOS output; pin LOS (re-conﬁgured)

V_OL

LOW-level output

voltage

I_OL= 1 mA

0

-

0.2

V

V_OH

HIGH-level output

voltage

I_OH= −1 mA

V

_CC− 0.2

V_CC

CMOS input; pin JAM and LVL

V_IL

V_IH

I_IL

LOW-level input

voltage

0

-

0.33V_CC

V

HIGH-level input

voltage

0.7V_CC

−200

-

V_CC

-

V

LOW-level input

current

V_IL= 0 V

V_IH= V_CC

µA

I_IH

HIGH-level input

current

10

Analog input; pin EXT

V_I

I_i

input voltage

input current

0

-

3.5

10

-

V

[4]

-

µA

MΩ

Z_i

input impedance

-

1

Reference; pin RREF

V_ref

reference voltage

10 kΩ resistor to GND

1.17

1.23

1.28

V

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

23 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

Table 18: Characteristics …continued

T_amb= −40 °C to +85 °C; V_CC= 2.9 V to 3.5 V; positive currents ﬂow into the IC; all voltages are referenced to ground; all

values apply to default conﬁguration; ACE on, 2.5 Gbit/s; V_o= 1500 mV (p-p) (diff); LOS and LLD active; no jam; RF input

values are listed as single-ended; RF output values are listed differential; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I²C-bus pins; SCL and SDA

V_IL

LOW-level input

voltage

0

-

0.33V_CC

V

V_IH

V_hys

V_OL

HIGH-level input

voltage

0.7V_CC

0.05V_CC

0

V_CC

-

hysteresis of Schmitt

trigger inputs

SDA LOW-level

output voltage

(open-drain)

I_OL= 3 mA

0.4

I_L

leakage current

-

µA

I_IL

LOW-level input

current

−200

I_IH

HIGH-level input

current

-

10

µA

C_i

input capacitance

pF

I²C-bus timing

f_SCL

SCL clock frequency

-

100

kHz

µs

t_LOW

SCL LOW time

1.3

0.6

-

t_HD;STA

hold time START

condition

µs

t_HIGH

SCL HIGH time

0.6

-

µs

t_SU;STA

set-up time START

condition

t_HD;DAT

t_SU;DAT

t_SU;STO

data hold time

0

-

0.9

µs

ns

µs

data set-up time

100

0.6

-

set-up time STOP

condition

t_r

SCL and SDA rise

time

20

-

300

ns

t_f

SCL and SDA fall time

20

-

300

-

ns

t_BUF

bus free time between

STOP and START

1.3

µs

C_b

capacitive load for

each bus line

-

400

pF

ns

V

t_SP

V_nL

V_nH

pulse width of

allowable spikes

0

50

-

noise margin at

LOW-level

0.1V_CC

0.2V_CC

noise margin at

HIGH-level

-

V

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24 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

[1] Clariﬁcation of used abbreviations:

a) OC3 and OC48 are SONET based standards, 155.52 Mbit/s and 2488.32 Mbit/s respectively.

b) STM-1 and STM-16 are SDH based standards, 155.52 Mbit/s and 2488.32 Mbit/s respectively.

c) GE is Gigabit Ethernet, 1250 Mbit/s.

[2] Adding both independent currents of Figure 17 and Figure 18 yields the total I_CC

.

[3] Power listed is the power dissipated by the TZA3054A, excluding the power dissipated in the 50 Ω load.

[4] Guaranteed by design.

001aab374

001aab375

21

40

I

CC

(mA)

CC(core)

(mA)

17

13

9

30

(1)

20

10

0

(2)

5

2

3

4

10

bit rate (Mbit/s)

0

500

1000

1500

2000

(mV)

V

o

(1) ACE on.

(2) ACE off.

Fig 17. Core supply current as a function of bit rate.

Fig 18. RF output supply current as a function of

output voltage swing.

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

12. Package outline

HVQFN20: plastic thermal enhanced very thin quad flat package; no leads;

20 terminals; body 4 x 3 x 0.85 mm

SOT797-1

D

B

A

E

terminal 1

index area

A

1

c

detail X

C

e

1

y

v

M

C

A B

C

1

e

b

w

1/2 e

5

10

L

4

1

11

e

E

h

2

1/2 e

14

terminal 1

index area

20

15

X

D

h

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

D

E

h

e

L

v

w

y

1

2

1

h

max.

0.05 0.30

0.00 0.18

4.1

3.9

2.75

2.45

3.1

2.9

1.75

1.45

0.5

0.3

mm

1

0.2

0.5

2.5

1.5

0.1

0.05 0.05

0.1

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-03-19

SOT797-1

- - -

Fig 19. Package outline.

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

13. Soldering

13.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

13.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

13.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

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TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

13.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

13.5 Package related soldering information

Table 19: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

28 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

29 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

14. Revision history

Table 20: Revision history

Document ID

Release date Data sheet status

20040812 Product data sheet

Change notice Order number

9397 750 13466

Supersedes

TZA3054A_1

-

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

30 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

15. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Right to make changes — Philips Semiconductors reserves the right to

16. Deﬁnitions

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

18. Licenses

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

Purchase of Philips I²C-bus components

Purchase of Philips I²C-bus components conveys a

license under the Philips’ I²C-bus patent to use the

components in the I²C-bus system provided the system

conforms to the I²C-bus speciﬁcation deﬁned by

Koninklijke Philips Electronics N.V. This speciﬁcation

can be ordered using the code 9398 393 40011.

17. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

19. Trademarks

A-rate — is a trademark of Koninklijke Philips Electronics N.V.

20. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 13466

Objective data sheet

Rev. 01 — 12 August 2004

31 of 32

TZA3054A

Philips Semiconductors

100 Mbit/s to 3.2 Gbit/s A-rate limiting ampliﬁer

21. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4

13.3

13.4

13.5

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 27

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 28

Package related soldering information. . . . . . 28

14

15

16

17

18

19

20

Revision history . . . . . . . . . . . . . . . . . . . . . . . 30

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 31

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Contact information . . . . . . . . . . . . . . . . . . . . 31

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8

Functional description . . . . . . . . . . . . . . . . . . . 6

RF input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logarithmic level detect . . . . . . . . . . . . . . . . . . 6

Loss of signal indicator . . . . . . . . . . . . . . . . . . . 7

Setting LOSTH reference level by external

8.1

8.2

8.3

8.4

resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

RF output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

JAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Diagnostic support . . . . . . . . . . . . . . . . . . . . . 11

Junction temperature . . . . . . . . . . . . . . . . . . . 11

Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . 11

LLD voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

External voltage . . . . . . . . . . . . . . . . . . . . . . . 11

Power supply connections . . . . . . . . . . . . . . . 11

Power-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Default at power-up. . . . . . . . . . . . . . . . . . . . . 12

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12

I²C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Manual settings. . . . . . . . . . . . . . . . . . . . . . . . 13

Fully automatic mode: automatic bandwidth

8.5

8.5.1

8.5.2

8.5.2.1

8.5.2.2

8.5.2.3

8.5.2.4

8.5.3

8.5.4

8.5.5

8.5.6

8.5.7

8.6

8.6.1

and slew rate adjustment over all bit rates . . . 13

Semi-automatic mode: manual selection of

bit rate range with automatic bandwidth

and slew rate adjustment within this range. . . 14

Full manual mode: manual selection of

8.6.2

8.6.3

bandwidth and slew rate. . . . . . . . . . . . . . . . . 15

I²C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Write protocol . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read protocol . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.7

8.7.1

8.7.2

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 21

Thermal characteristics. . . . . . . . . . . . . . . . . . 21

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 22

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26

10

11

12

13

13.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 27

13.2

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 12 August 2004

Document order number: 9397 750 13466

Published in The Netherlands

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