S8401/S8501
HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET
Figure 5. Functional Waveform
S
REFCLK
(Input)
8
4
D0/D1 D2/D3 D4/D5 D6/D7 D8/D9 D10/D11 D12/D13 D14/D15
PARALLEL
DATA BUS
(Input)
0
1
D2
D0
D1
D3
D5
D4
D6
D8
D7
D9
D10 D11 D12
D14
D13
D15
SERIAL DATA
S
8
5
RCLK
(Output)
PARALLEL
D0/D1 D2/D3 D4/D5 D6/D7 D8/D9 D10/D11 D12/D13 D14/D15
0 DATA BUS
(Output)
1
Framing
S8501 RECEIVER
Framing is performed off-chip. Typically, an FPGA
would be used to implement descrambling and Word/
Frame synchronization as required by SMPTE 292M.
Architecture/Functional Description
The S8501 receiver is designed to implement SMPTE
292M Specification receiver functions. A block dia-
gram showing the basic chip function is provided in
Figure 4.
Lock Detect
The S8501 lock detect function indicates the state of
the phase-locked loop (PLL) clock recovery unit. The
PLL will indicate lock within 2.5µs after the start of
receiving serial data inputs. If the serial data inputs
have an instantaneous phase jump (from a serial
switch, for example) the PLL will not indicate an out-
of-lock state, but will recover the correct phase
alignment within 250 bit times. If a run length of 80-
160 bits is exceeded the loop will declare loss of lock.
Input data rate variation (compared to REFCLK) can
also cause loss of lock. Table 3 shows the response
of the PLL loop circuit to input data rate variation.
When lock is lost, the PLL will attempt to re-acquire
bit synchronization, and will shift from the serial input
data to the reference clock so that the correct fre-
quency downstream clocking will be maintained.
Whenever a signal is present, the S8501 attempts to
achieve bit synchronization of the received encoded
bit stream. Received data from the incoming bit stream
is provided on the device’s parallel data outputs.
The S8501 accepts serial encoded data from a fiber
optic or coaxial cable interface. The serial input stream
is the result of the serialization of scrambled data by
a compatible transmitter. Clock recovery is performed
on-chip, with the output data presented to the trans-
mission layer as 20-bit parallel data. The chip operates
at the HD-SDI frequency of 1.485Gb/s.
Serial/Parallel Conversion
Serial data is received on the RX, RY pins. The PLL
clock recovery circuit will lock to the data stream if the
clock to be recovered is within ±100 PPM of the inter-
nally generated bit rate clock. The recovered clock is
used to retime the input data stream. The data is then
clocked into the serial to parallel output registers.
The LOCKDETN output will go inactive (High) when
no data is present on the serial data inputs. When
LOCKDETN is in the inactive (high) state, it indicates
that the PLL is locking to the local reference clock to
maintain downstream clocking. When LOCKDETN is
in the active (low) state, it indicates that the PLL is
attempting to lock to the incoming serial data. When
serial data is restored, the LOCKDETN output will
stay in the active state.
Reference Clock Input
The reference clock input must be supplied with a
PECL single-ended AC coupled crystal clock source
at ±100 PPM tolerance. See Table 2 for reference
clock frequency.
4
December 10, 1999 / Revision C
