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7P256ATA1002I25

型号：

7P256ATA1002I25

品牌：

MICROSEMI[ Microsemi ]

页数：

25 页

PDF大小：

224 K

下载PDF手册
PCMCIA Flash Memory Card  
ATA10 Series  
ATA Flash card  
Features  
WEDC ATA10 Series (ATA10) flash memory cards  
are ATA compatible cards and are suitable for usage  
as a data storage memory medium for PC’s or any  
other electronic equipment.  
• PC Card ATA compatible  
- 68 pin two piece connector and type I or type II housing  
(5mm)  
- PCMCIA/JEIDA 4.1  
• x8/x16 PCMCIA standard interface  
• Single 3 Volt / 5 Volt Supply  
Packaged in a PCMCIA type I or type II housing, the  
WEDC ATA series cards provide a lightweight, low  
power, reliable nonvolatile storage medium.  
• ISA standard, Read/Write unit is 1 sector (512 bytes)  
- Sector Read/Write transfer rate: 8 MB/s burst  
- High reliability based on internal ECC function (Error  
Correcting Code) and wear leveling functions.  
Built in to the card controller, Error Correcting Code  
(ECC) provides a high level of reliability and MTBF  
(Mean Time Between Failures)  
• Card Capacity  
WEDC’s standard cards are shipped with the WEDC  
FLASH Logo. Cards are also available with blank  
housings (no Logo). The blank housings are available  
in both a recessed (for label) and flat housing. Please  
contact your WEDC sales representative for further  
information on Custom artwork.  
- 8 MB to 512 MB (unformatted)  
• Card Access mode:  
- Memory card mode  
- I/O card mode  
- True-IDE mode  
• Data Write Endurance is 100k program/erase cycles  
• Data reliability is 1 error in 1014 bits read  
• Auto Sleep Function  
Block Diagram  
Memory Array  
Code/software  
DATA  
ADRS  
...  
DATA I/O  
CONTROLLER  
OSC  
CONTROL  
1
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Block Diagram  
Internal Vcc  
Vcc  
GND  
A0 to A10  
Reset IC  
-CE1, -CE2  
-OE, -ATASEL  
-WE  
X’tal  
-IORD  
-IOWR  
Flash  
Memory  
Bus  
-REG  
RESET/-RESET  
64Mb, 128Mb  
or 256Mb  
Controller  
-CSEL  
NAND Flash  
D0 TO D15  
RDY/-BSY/-IREQ/INTRQ  
WP/-IOIS16  
Control signal  
-INPACK  
BVD1/STSCHG/-PDIAG  
Code/  
D0 to D15  
A0 to A10  
-WAIT/IORDY  
Software  
VS1  
VS2  
OPEN  
BVD2/-SPKR/-DASP  
-CD1  
-CD2  
2
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Mechanical  
Type I  
Interconnect area  
1.6mm ± 0.05  
(0.063”)  
10.0mm MIN  
(0.400”)  
3.0mm MIN  
1.0mm ± 0.05  
(0.039”)  
Substrate area  
54.0mm ± 0.10  
(2.126”)  
85.6mm ± 0.20  
(3.370”)  
1.0mm ± 0.05  
(0.039”)  
10.0mm MIN  
(0.400”)  
3.3mm ± T1 (0.130”)  
T1=0.10mm interconnect area  
T1=0.20mm substrate area  
Type II  
1.6mm ± 0.05  
0.063”  
85.6mm ± 0.20  
3.370”  
1.0mm ±0.05  
0.039’  
3.0mm  
MIN.  
Substrate area  
54.0mm ± 0.10  
2.126”  
1.0mm ±0.05  
0.039’  
10.0mm MIN  
0.400”  
Interconnect area  
3.3mm ± 0.10mm  
5.0mm ± T1  
0.197”  
3
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Card Capacity  
Because of card formatting, user available capacity is smaller than the original memory size. The table below  
presents the relation between card capacity and formatted capacity.  
Note: Other capacities are available: contact your company sales representative for details.  
Formatted  
Card type  
Capacity Capacity  
7P008ATA1003C25 8MB  
7P016ATA1003C25 16MB  
7P032ATA1003C25 32MB  
7P048ATA1003C25 48MB  
7P064ATA1003C25 64MB  
7P080ATA1003C25 80MB  
7P096ATA1003C25 96MB  
7.38MB  
15.42MB  
30.88MB  
47.23MB  
63.07MB  
76.00MB  
91.20MB  
7P112ATA1003C25 112MB 106.40MB  
7P128ATA1003C25 128MB 121.60MB  
7P192ATA1003C25 192MB 183MB  
7P256ATA1003C25 256MB 244MB  
System Performance  
Item  
Performance  
Data transfer rate  
8.0 MB/s burst  
1.0 MB/s sustained read  
600 kB/s sustained write  
recoverable error in 10^14 bits read.  
2ms (max)  
Data reliability  
Start up time (Sleep to Idle)  
Start up time (Reset to Ready)  
50ms (typ)  
Card controller provides PCMCIA compatibility.  
Card supports fast ATA host to buffer burst transfer rates up to 20MB/s (with PIO mode 4) and fast transfer rate  
to/from flash memory up to 8MB/s  
4
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Absolute Maximum Ratings (1)  
Note:  
Operating Temperature TA (ambient)  
Commercial  
(1) Stress greater than those listed under  
“Absolute Maximum ratings” may cause  
permanent damage to the device. This is a  
stress rating only and functional operation at  
these or any other conditions greater than  
those indicated in the operational sections  
of this specification is not implied. Exposure  
to absolute maximum rating conditions for  
extended periods may affect reliability.  
0°C to +60 °C  
Industrial  
Storage Temperature  
Commercial  
Industrial  
Voltage on any pin relative to VSS  
VCC supply Voltage relative to VSS  
-40°C to +85 °C  
-20°C to +85 °C  
-40°C to +85 °C  
-0.5V to VCC+0.5V (1)  
-0.5V to +7.0V  
Recommended DC Operating Conditions  
Parameter  
Operating temp  
Vcc voltage  
Symbol  
Ta  
Vcc  
Min  
0
4.5  
Max  
60  
5.5  
Unit  
C
V
Note  
25  
5
DC Characteristics (1)  
CMOS Test Conditions: VIL = VSS ± 0.2V, VIH = VCC ± 0.2V  
Symbol Parameter  
Notes Min  
Typ  
Max Units Test Conditions  
5.5V  
Vcc  
Power Supply Voltage  
4.5V  
ICC1  
ICC2  
ICCS  
Sector READ current  
Sector WRITE current  
2
2
50  
50  
mA CMOS level  
mA CMOS level  
VCC Sleep/Standby Current 1, 2  
0.5  
mA Control Signals = VCC  
VCC = VCCMAX  
ILI  
Input Leakage Current  
Output Leakage Current  
1, 3  
±20  
µA  
Vin =VCC or VSS  
VCC = VCCMAX  
Vout =VCC or VSS  
ILO  
±20  
0.8  
µA  
VIL  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
V
V
V
V
VIH  
VOL  
VOH  
2.0  
2.4  
0.4  
IOL = 3.2mA  
IOH = -2.0mA  
Notes:  
1. Control Signals: CE1#, CE2#, OE#, WE#, REG#, IORD#, IOWR#.  
2. Typical: VCC = 5V, T = +25C.  
3. Exceptions: Leakage currents on control signals will be < 500 µA when VIN = GND due to  
internal pull-up resistors.  
5
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Pinout  
Memory card m ode  
I/O Card Mode  
Signal Name  
GND  
D3  
True IDE Mode  
Signal Name  
GND  
D3  
Pin Number Signal Name  
I/O  
I/O  
I/O  
1
2
GND  
D3  
I/O  
I/O  
I/O  
3
D4  
I/O  
D4  
I/O  
D4  
I/O  
4
D5  
I/O  
D5  
I/O  
D5  
I/O  
5
D6  
I/O  
D6  
I/O  
D6  
I/O  
6
D7  
I/O  
D7  
I/O  
D7  
I/O  
7
8
9
CE1#  
A10  
OE#  
N.C.  
A9  
I
I
I
-
I
I
-
-
I
CE1#  
A10  
OE#  
N.C.  
A9  
I
I
I
-
I
I
-
-
I
CE1#  
A10  
ATASEL#  
N.C.  
A9  
I
I
I
-
I
I
-
-
I
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
A8  
A8  
A8  
N.C.  
N.C.  
WE#  
RDY/BSY  
Vcc  
N.C.  
N.C.  
WE#  
IREQ#  
Vcc  
N.C.  
N.C.  
N.C.  
N.C.  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
D0  
N.C.  
N.C.  
WE#  
INTRQ  
Vcc  
N.C.  
N.C.  
N.C.  
N.C.  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
D0  
O
O
O
N.C.  
N.C.  
N.C.  
N.C.  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
D0  
D1  
D2  
WP  
GND  
-
-
-
-
I
I
I
I
I
-
-
-
-
I
I
I
I
I
-
-
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O  
I/O  
I/O  
O
I/O  
I/O  
I/O  
O
I/O  
I/O  
I/O  
O
D1  
D2  
IOIS16#  
GND  
D1  
D2  
IOIS16#  
GND  
6
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Pinout (Cont.)  
Memory card mode  
I/O Card Mode  
Signal Name  
GND  
CD1#  
D11  
True IDE Mode  
Signal Name  
GND  
CD1#  
D11  
Pin Number Signal Name  
I/O  
I/O  
I/O  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
GND  
CD1#  
D11  
O
O
I/O  
I/O  
I/O  
I/O  
I
I
O
I
I
O
I/O  
I/O  
I/O  
I/O  
I
I
O
I
I
I/O  
D12  
I/O  
D12  
D13  
D14  
D15  
CE2#  
VS1  
IORD#  
IOWR#  
NC  
NC  
NC  
NC  
NC  
Vcc  
NC  
NC  
NC  
NC  
CSEL#  
VS2  
RESET  
Wait#  
INPACK#  
REG#  
SPKR#  
STSCHG#  
D8  
D12  
D13  
D14  
D15  
CE2#  
VS1  
IORD#  
IOWR#  
NC  
NC  
NC  
NC  
NC  
Vcc  
NC  
NC  
NC  
NC  
CSEL#  
VS2  
RESET#  
IORDY  
INPACK#  
REG#  
DASP  
PDIAG#  
D8  
D13  
I/O  
D14  
I/O  
D15  
CE2#  
VS1  
IORD#  
IOWR#  
NC  
NC  
NC  
NC  
NC  
Vcc  
NC  
NC  
NC  
NC  
CSEL#  
VS2  
I
I
O
I
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
O
I
O
O
I
-
-
-
-
I
-
-
-
-
I
O
I
O
O
I
I/O  
I/O  
I/O  
I/O  
O
O
O
I
O
O
I
I/O  
I/O  
I/O  
I/O  
O
O
RESET  
Wait#  
INPACK#  
REG#  
BVD2  
BVD1  
D8  
D9  
D10  
CD2#  
GND  
I/O  
I/O  
I/O  
I/O  
O
O
D9  
D10  
CD2#  
GND  
D9  
D10  
CD2#  
GND  
Note: CD1# and CD2# are grounded internal to PC Card.  
7
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Card Signal Description  
Symbol  
A0 – A10  
Type  
INPUT  
Name and Function  
ADDRESS INPUTS: A0 through A10 Signal A0 is not used in word  
access mode. A10 is the most significant bit. In True IDE Mode only  
HA[2..0] are used for selecting the eight registers in the Task File, the  
remaining address lines should be grounded.  
D0 - D15  
INPUT/OUT  
PUT  
DATA INPUT/OUTPUT: D0 THROUGH D15 constitute the bi-  
directional databus. D0 - D7 constitute the lower (even) byte and D8 -  
D15 the upper (odd) byte. D15 is the MSB.  
CE1#, CE2#  
INPUT  
CARD ENABLE 1 AND 2: active low signals; CE1# enables even  
byte accesses, CE2# enables odd byte accesses. In True IDE Mode  
CE2#is used to select the Alternate Status Register and the Device  
control Register while CE1# is the cheap select for the other task file  
registers.  
OE#,  
ASTEL#  
INPUT  
OUTPUT ENABLE, ATA Select: Active low signal enabling read  
data from Attribute and Common memory area. To enable True IDE  
Mode this input should be grounded by the host.  
WE#  
INPUT  
WRITE ENABLE: Active low signal gating write data to the memory  
card. In true IDE Mode this input signal is not used and should be  
connected to Vcc.  
RDY/BSY #  
IREQ #  
INTRQ  
OUTPUT  
Ready/Busy, Interrupt Request: In I/O mode this signal is is  
IREQ #pin. The signal of low level indicates that the card is requesting  
software service to host, and high level indicate that the card is not  
requesting. In memory mode, the signal is set high when the ATA card  
is ready to accept new data transfer operation and held low when card  
is busy.  
At power up and at Reset, the RDY/BSY is low until (busy) until the  
card has completed its power up or reset function.  
Host should provide a pull up resistor  
CD1#, CD2#  
OUTPUT  
OUTPUT  
CARD DETECT 1 and 2: Provide card insertion detection. These  
signals are connected to ground internally on the memory card. The  
host socket interface circuitry shall supply 10K-ohm or larger pull-up  
resistors on these signal pins.  
Write Protect, 16 bit I/O port: In memory mode, WP is held low:  
always writable). In I/O mode , IOIS16#is asserted low when Task  
File Registers are accessed in 16 bit mode. In True IDE mOde this  
signal is asserted low when this device is expecting a word data transfer  
cycle.  
WP  
IOIS16#  
VPP1, VPP2  
N.C.  
PROGRAM/ERASE POWER SUPPLY: No Connection for ATA  
card.  
VCC  
GND  
REG#  
CARD POWER SUPPLY: 5.0V for all internal circuitry.  
GROUND: for all internal circuitry.  
ATTRIBUTE MEMORY SELECT: Used to enable access to  
Attribute space. Should be in high level during common memory area  
access. In True IDE Mode input signal is not used and should be  
connected to Vcc.  
Reset, Reset #: Active signal will clear all registers on the card (power  
on default). In True IDE Mode Reset# is the active low hardware reset  
from the host.  
INPUT  
INPUT  
Reset  
Reset#  
8
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Card Signal Description (Cont.)  
Symbol  
WAIT #  
Type  
OUTPUT  
Name and Function  
WAIT: This signal outputs low level for purpose of delaying memory  
or I/O access cycle. In True IDE Mode this signal can be used as  
IORDY.  
BVD2  
SPKR #  
DASP#  
Input/Output  
Input/Output  
Battery Voltage Detect 2, Data audio output, Disk active/slave  
present: In memory card mode, BVD2 is always high. In I/O mode,  
SPKR #is held high: no digital audio signals. In True IDE Mode  
DASP# is Disk Active/Slave Present signal in Master/Slave  
handshake protocol.  
Battery Voltage Detect 1, Status Change, Pass Diagnostic: In  
memory card mode BVD1 Is set to high level. In I/O mode  
STSCHNG#is used to alert the host to changes in Status registers. In  
True IDE mode PDIG is the Pass Diagnostic signal in Master/Slave  
handshake protocol.  
BVD1  
STSCHNG#  
PDIAG#  
VS1, VS2  
CSEL#  
OUTPUT  
Input  
VOLTAGE SENSE: Notifies the host socket of the card's VCC  
requirements. VS1 and VS2 are open to indicate a 5V, 16 bit card has  
been inserted.  
Card Select: This signal is not used in memory and I/O mode. With  
internal pull up resistor this signal is used to configure this card as  
Master or Slave when configured in True IDE Mode. When this pin is  
GND, selected Master config, when pin is open the card is configured  
as a Slave.  
INPACK#  
Output  
Input Acknowledge: This signal is not used in memory mode. It is  
asserted by the card when the card is selected and responding to an  
I/O read cycle at the address that is on the address bus. This signal is  
used for the input data buffer control. In True IDE Mode this signal is  
not used and should not be connected at the host.  
IORD #  
IOWR #  
Input  
Input  
I/O Read: is used for control of read data in Task File area. This card  
respond to this signal only in I/O interface mode  
I/O Write: is used for control of data write in Task File area. This card  
respond to this signal only in I/O interface mode  
9
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Card Function Explanation  
Register Construction  
§
Attribute Region  
•
Configuration Register  
Configuration Option Register  
Configuration and Status Register  
Pin Replacement Register  
Socket and Copy Register  
•
CIS (Card Information Structure)  
§
Task File Region  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Error Register  
Feature Register  
Sector Count Register  
Sector Number Register  
Cylinder Low Register  
Cylinder High Register  
Drive/Head Register  
Status Register  
Command Register  
Disk Address Pointer  
Buffer RAM Size Control Register  
Host Interrupt Status Register  
Host Interrupt Enable Register  
ECC Control Register  
ECC 0-2 Registers  
DMA Control Register  
10  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Host Access Specification  
1. Attribute Access Specification  
When the CIS-ROM region or Configuration register region is accessed, read and write operations are executed  
under the condition of REG# = Low as follows. That region can be accessed by Byte/Word/Odd-byte modes which  
are defined by the PC card standard specification.  
Attribute Read Access Mode  
Mode  
Standby Mode  
Byte access  
REG# CE2# CE1# A0 OE# WE# D15 - D8  
D7 - D0  
High Z  
even byte  
invalid  
even byte  
High Z  
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
L
L
L
L
X
H
H
H
H
High Z  
High Z  
High Z  
invalid  
invalid  
Word access (16 bit)  
Odd Byte access (8 bit  
L
Attribute Write Access Mode  
Mode  
REG# CE2# CE1# A0 OE# WE# D15 - D8  
D7 - D0  
Standby Mode  
Byte access  
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
Don't care Don't care  
Don't care even byte  
Don't care Don't care  
Don't care even byte  
Don't care Don't care  
Word access (16 bit)  
Odd Byte access (8 bit  
L
11  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
2. Task File Register Access Specification  
There are two cases of Task File register mapping, one is the mapped I/O address area, the other is  
the Mapped Memory address area. Each case of the Task File register read and write operation is  
executed under the following conditions. The area can be accessed by Byte/Word/Odd Byte mode  
which is defined by the PC card standard specification.  
(a) I/O address map  
Task File Register Read Access Mode (a)  
Mode  
Standby Mode  
Byte access  
REG# CE2# CE1# A0 IORD# IOWR# OE# WE# D15 - D8  
D7 - D0  
High Z  
even byte  
odd byte  
even byte  
High Z  
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
High Z  
High Z  
High Z  
odd byte  
odd byte  
Word access (16 bit)  
Odd Byte access (8 bit  
L
Task File Register Write Access Mode (a)  
Mode  
REG# CE2# CE1# A0 IORD# IOWR# OE# WE# D15 - D8  
D7 - D0  
Standby Mode  
Byte access  
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
Don't care Don't care  
Don't care even byte  
Don't care  
odd byte  
odd byte  
odd byte  
even byte  
Don't care  
Word access (16 bit)  
Odd Byte access (8 bit  
L
(b) Memory address map  
Task File Register Read Access Mode (b)  
Mode  
Standby Mode  
Byte access  
REG# CE2# CE1# A0 IORD# IOWR# OE# WE# D15 - D8  
D7 - D0  
High Z  
even byte  
odd byte  
even byte  
High Z  
X
H
H
H
H
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
High Z  
High Z  
High Z  
odd byte  
odd byte  
Word access (16 bit)  
Odd Byte access (8 bit  
L
Task File Register Write Access Mode (b)  
Mode  
REG# CE2# CE1# A0 IORD# IOWR# OE# WE# D15 - D8  
D7 - D0  
Standby Mode  
Byte access  
X
H
H
H
H
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
X
L
L
L
L
Don't care Don't care  
Don't care even byte  
Don't care  
odd byte  
odd byte  
odd byte  
even byte  
Don't care  
Word access (16 bit)  
Odd Byte access (8 bit  
L
12  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
3. True IDE Mode  
The card can be configured in a True IDE Mode of operation. This card is configured in this mode only  
when the OE# input signal is asserted low by the host during the power off to power on cycle. In this True  
IDE Mode the PCMCIA protocol and configuration are disabled and only an I/O operation to the Task File  
registers is allowed. In this mode no Memory or Attribute registers are accessible to the host. The card  
permits 8 bit access if the user issues a Set feature Command to put the device in the 8 bit Mode.  
True IDE Mode Read I/O function  
Mode  
Invalid Mode  
Standby Mode  
Data Register Access  
All status access  
Other task file access  
CE2# CE1# A0..A2 IORD# IOWR# D15 - D8  
D7 - D0  
High Z  
High Z  
even byte  
status out  
data  
L
H
H
L
L
H
L
H
L
X
X
0h  
X
X
L
L
L
X
X
H
H
H
High Z  
High Z  
odd byte  
High Z  
High Z  
6h  
H
1-7h  
True IDE Mode Read I/O function  
Mode  
CE2# CE1# A0..A2 IORD# IOWR# D15 - D8  
D7 - D0  
Invalid Mode  
L
H
H
L
L
H
L
H
L
X
X
0h  
6h  
1-7h  
X
X
H
H
H
X
X
L
L
L
Don't care Don't care  
Don't care Don't care  
Standby Mode  
Data Register Access  
All status access  
Other task file access  
odd byte  
Don't care  
Don't care  
even byte  
control in  
data  
H
13  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Configuration Register Specifications  
This card supports four Configuration registers for the purpose of the configuration and  
observation of this card.  
1. Configuration Option Register (Address 200H)  
This register is used for the configuration of the card configuration status and for the issuing the  
soft reset to the card.  
bit7  
bit6  
bit5  
bit4  
bit3  
bit2  
bit1  
bit0  
SRESET  
LevlREQ  
INDEX  
Note: initial value: 00H  
Name  
R/W Function  
SRESET  
(HOST->)  
R/W Setting this bit to "1", places the card in the reset state (Card Hard Reset). This  
operation is equal to Hard Reset, except this bit is not cleared. Then this bit is set to "0",  
places the card in the reset state of Hard Reset (This bit is set to "0" by Hard Reset) .  
Card configuration status is reset and the card internal initialized operation starts when  
Card Hard Reset is executed, so the next access to the card should be the same  
sequence as the power on sequence.  
LevlREQ  
(HOST->)  
R/W This bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode  
interrupt is selected.  
R/W  
INDEX  
(HOST->)  
This bit is used to select the operation mode of the card as follows.  
When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose  
of Memory card interface recognition.  
INDEX bit assignment  
INDEX bit  
5
0
0
0
0
4
0
0
0
0
3
0
0
0
0
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
Card mode  
Task File register address  
Mapping mode  
Memory card 0H to FH, 400H to 7FFH  
memory mapped  
I/O card  
I/O card  
I/O card  
xx0H to xxFH  
contiguous I/O mapped  
primary I/O mapped  
secondary I/O mapped  
1F0H to 1F7H, 3F6H to 3F7H  
170H to 177H, 376H to 377H  
14  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
2. Configuration and Status Register (Address 202H)  
This register is used for observing the card state.  
bit7  
bit6  
bit5  
bit4  
bit3  
bit2  
bit1  
bit0  
CHGED  
SIGCHG  
IOIS8  
0
0
PWD  
INTR  
0
Note: initial value: 00H  
Name  
R/W Function  
CHGED  
(CARD->)  
R
This bit indicates that the CRDY/-BSY bit on the Pin Replacement register is set to "1".  
When CHGED bit is set to "1", the -STSCHG pin is held "L" at the condition of SIGCHG  
bit set to "1" and the card configured for the I/O interface.  
SIGCHG  
(HOST->)  
R/W This bit is set or reset by the host for enabling and disabling the status-change signal (-  
STSCHG pin). When the card is configured I/O card interface and this bit is set to "1", -  
STSCHG pin is controlled by the CHGED bit. If this bit is set to "0", the -STSCHG pin is  
kept "H".  
IOIS8  
(HOST->)  
R/W The host sets this field to "1" when it can provide I/O cycles only with on 8 bit data bus  
(D7 to D0).  
R/W  
PWD  
(HOST->)  
When this bit is set to "1", the card enters the sleep state (Power Down mode). When  
this bit is reset to "0", the card transfers to the idle state (active mode). RRDY/-BSY bit  
on the Pin Replacement Register becomes BUSY when this bit is changed. RRDY/-  
BSY will not become Ready until the power state requested has been entered. This  
card automatically powers down when it is idle, and powers back up when it receives a  
command.  
R
INTR  
(CARD->)  
This bit indicates the internal state of the interrupt request. This bit state is available  
whether the I/O card interface has been configured or not. This signal remains true until  
the condition which caused the interrupt request has been serviced. If interrupts are  
disabled by the -IEN bit in the Device Control Register, this bit is a zero.  
15  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
3. Pin Replacement Register (Address 204H)  
t7  
bit6  
bit5  
bit4  
bit3  
bit2  
bit1  
bit0  
0
0
CRDY/-BSY 0  
1
1
RRDY/-BSY 0  
Note: initial value: 0CH  
Name  
R/W Function  
CRDY/-BSY R/W This bit is set to "1" when the RRDY/-BSY bit changes state. This bit may also be  
(HOST->)  
written by the host.  
R/W  
RRDY/-BSY  
(HOST->)  
When read, this bit indicates +READY pin states. When written, this bit is used for  
CRDY/-BSY bit masking.  
4. Socket and Copy Register (Address 206H)  
This register is used for identification of the card from the other cards. The host can read and  
write this register. This register should be set by the host before this card's Configuration Option  
register set.  
bit7  
bit6  
bit5  
bit4  
bit3  
bit2  
bit1  
bit0  
0
0
0
DRV#  
0
0
0
0
Note: initial value: 00H  
Name  
R/W Function  
R/W This field is used for the configuration of the plural cards.  
DRV#  
(HOST->)  
16  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Sector Transfer Protocol  
1. Sector read: 1 sector read procedure after the card configured I/O interface is shown as follows.  
Start  
I/O Access index = 1  
Set the cylinder low / high register  
Set the head No. of drive head register  
(1) Set the logical sector number  
Set the sector number register  
Set “01H” in sector count register  
Set “20H” in command register  
(2)  
Read Status register  
(3)  
58H  
Read 256 times the data (512 bytes)  
(4) Burst data transfer  
Read Status register  
50H  
(5)  
Wait the command input  
(1)  
4H 5H 6H 3H 2H 7H  
(2)  
(3)  
(4)  
(5)  
7H  
7H  
0H  
0H  
7H 7H  
A0 to A10  
-CE1  
-CE2  
-IOWR  
-IORD  
01H20H 80H  
58H (Transfer data)  
80H  
50H  
D0 to D15  
-IREQ  
17  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
2. Sector write: 1 sector write procedure after the card configured I/O interface is shown as follows.  
Start  
I/O Access index = 1  
Set the cylinder low / high register  
Set the head No. of drive head register  
(1) Set the logical sector number  
Set the sector number register  
Set “01H” in sector count register  
Set “30H” in command register  
(2)  
Read Status register  
(3)  
58H  
Write 256 times the data (512 bytes)  
(4) Burst data transfer  
Read Status register  
50H  
(5)  
Wait the command input  
(1)  
4H 5H 6H 3H 2H 7H  
(2)  
(3)  
(4)  
(5)  
7H  
7H  
0H  
0H  
7H 7H  
A0 to A10  
-CE1  
-CE2  
-IOWR  
-IORD  
01H30H 80H  
58H (data Transfer)  
80H  
50H  
D0 to D15  
-IREQ  
18  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
DC Current Waveform (Example of sector read or write: VCC = 5 V, Ta = 25°C)  
Power on Operation (Reference Only)  
DC  
Time  
Power on  
19  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Sector Read  
ICCR(peak)  
ICCR(DC)  
Time  
Complete of sector read  
Command write  
Sector Write  
ICCW(peak)  
ICCW(DC)  
Time  
Command write  
Complete of sector write  
20  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
AC Characteristics  
Read Timing Parameters  
250ns  
Min  
SYM  
Parameter  
Max  
Unit  
(PCMCIA)  
TC(R)  
Read Cycle Time  
250  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ta(A)  
Address Access Time  
Card Enable Access Time  
Output Enable Access Time  
Address Setup Time  
250  
250  
150  
ta(CE)  
ta(OE)  
tsu(A)  
tsu(CE)  
th(A)  
30  
0
Card Enable Setup Time  
Address Hold Time  
20  
th(CE)  
tv(A)  
Card Enable Hold Time  
20  
0
Output Hold from Address  
Change  
tdis(CE)  
tdis(OE)  
Ten(CE)  
Ten(OE)  
Output Disable Time from CE#  
100  
100  
ns  
ns  
ns  
ns  
Output Disable Time from OE#  
Output Enable Time from CE#  
Output Enable Time from OE#  
5
5
Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications.  
Read Timing Diagram  
tc(R)  
th(A)  
ta(A)  
A[25::0], /REG  
/CE1, /CE2  
tv(A)  
ta(CE)  
tsu(CE)  
NOTE 1  
NOTE 1  
th(CE)  
ta(OE)  
tsu(A)  
tdis(CE)  
/OE  
tdis(OE)  
ten(OE)  
D[15::0]  
DATA VALID  
Note: Signal may be high or low in this area.  
21  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Write Timing Parameters  
250ns  
Min  
SYM  
Parameter  
Max  
Unit  
(PCMCIA)  
tC(W)  
Write Cycle Time  
250  
150  
30  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tw(WE)  
Write Pulse Width  
tsu(A)  
Address Setup Time  
Address Setup Time for WE#  
tsu(A-WEH)  
180  
180  
80  
tsu(CE-WEH) Card Enable Setup Time for WE#  
tsu(D-WEH)  
th(D)  
Data Setup Time for WE#  
Data Hold Time  
30  
trec(WE)  
tdis(WE)  
tdis(OE)  
Write Recover Time  
30  
Output Disable Time from WE#  
Output Disable Time from OE#  
Output Enable Time from WE#  
Output Enable Time from OE#  
Output Enable Setup from WE#  
Output Enable Hold from WE#  
Card Enable Setup Time from OE#  
Card Enable Hold Time  
100  
100  
ten(WE)  
Ten(OE)  
tsu(OE-WE)  
th(OE-WE)  
tsu(OE)  
5
5
10  
10  
0
th(CE)  
20  
Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications.  
Write Timing Diagram  
tc(W)  
A[25::0], /REG  
tsu(A-WEH)  
trec(WE)  
th(CE)  
tsu(CE-WEH)  
tsu(CE)  
/CE1, /CE2  
NOTE 1  
NOTE 1  
/OE  
th(OE-WE)  
th(D)  
tw(WE)  
tsu(A)  
/WE  
tsu(OE-WE)  
NOTE 2  
tsu(D-WEH)  
D[15::0](Din)  
DATA INPUT  
tdis(WE)  
tdis(OE)  
ten(OE)  
ten(WE)  
NOTE 2  
D[15::0]( Dout)  
Notes:  
1. Signal may be high or low in this area.  
2. When the data I/O pins are in the output state, no signals shall be applied to the  
data pins (D15 - D0) by the host system.  
22  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
PRODUCT MARKING  
WED7P016ATA1000C15 C995 9915  
EDI  
Date code  
Lot code / trace number  
Part number  
Company Name  
Note:  
Some products are currently marked with our pre-merger company name/acronym (EDI). During our transition period,  
some products will also be marked with our new company name/acronym (WED). Starting October 2000 all PCMCIA  
products will be marked only with the WED prefix.  
PART NUMBERING  
7P016ATA1000C15  
Card access time  
15  
25  
150ns  
250ns  
Temperature range  
C
I
Commercial 0°C to +70°C  
Industrial -40°C to +85°C  
Packaging option  
00  
Standard, type 1  
Card family and version  
- See Card Family and Version Info. for details (next page)  
Card capacity  
016  
16MB  
PC card  
P
Standard PCMCIA  
R
Ruggedized PCMCIA  
Card technology  
7
8
FLASH  
SRAM  
23  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Ordering Information  
7P XXX ATA YY SS T ZZ  
where  
XXX:  
008  
016  
032  
048  
064  
080  
096  
112  
128  
192  
224  
256  
320  
384  
448  
512  
8MB  
16MB  
32MB  
48MB  
64MB  
80MB  
96MB  
112MB  
128MB  
192MB  
224MB  
256MB  
320MB  
384MB  
448MB  
512MB  
YY:  
SS:  
10  
Standard, 5V Only: (Controller type = MX)  
00  
01  
02  
03  
04  
05  
14  
WEDC FLASH Logo,  
Blank Housing,  
Type I  
Type I  
Blank Housing,  
WEDC FLASH Logo,  
Blank Housing,  
Type I Recessed  
Type II  
Type II  
Blank Housing,  
Blank Housing,  
Type II Recessed  
Type III  
T:  
C
I
Commercial  
Industrial  
ZZ:  
25  
250ns  
24  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
PCMCIA Flash Memory Card  
ATA10 Series  
Revision History:  
rev level  
rev 0  
rev 1  
description  
initial release  
Logo change  
date  
June 1, 1998  
May 27, 1999  
New card capacity  
New flowcharts added  
New timing diagrams  
added  
New form factor  
options added  
rev 2  
rev 3  
Sep 10, 1999  
Oct. 18, 1999  
New Flowcharts added  
New current waveforms  
added  
Register list added  
Max capacity change to 512MB  
rev 4  
rev 5  
Dec 19, 1999  
Timing corrections on Pgs 21 & 22. June 2, 2000  
Page 23 added, Page Header  
changed  
White Electronic Designs Corporation  
One Research Drive, Westborough, MA 01581, USA  
tel: (508) 366 5151  
fax: (508) 836 4850  
www.whiteedc.com  
25  
June 2000 Rev. 5 - ECO #12901  
PC Card Products  
厂商 型号 描述 页数 下载

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