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CYWUSB6942-100AC

型号：

CYWUSB6942-100AC

品牌：

CYPRESS[ CYPRESS ]

页数：

18 页

PDF大小：

160 K

下载PDF手册
CYWUSB6942  
WirelessUSB™ EX Baseband IC  
1.0  
Features  
2.0  
Applications  
• Low-cost, low-power, 2.4-GHz WirelessUSB EX base-  
band IC  
The CYWUSB6942 is targeted for a variety of wireless HID  
applications, including  
• Frequency-hopping, spread-spectrum (FHSS)  
• Coexists with other 2.4-GHz systems  
• Low latency, high throughput  
• Mice  
• Keyboards  
• USB bridges  
• Game controllers.  
• Bidirectional communication  
• Forward Error Correction (FEC) and automatic packet  
retry  
• Low battery power detection  
• Supports up to seven peripherals (multi-drop)  
• Direct support of optical mouse  
• Direct support of 18 x 8 keyboard scan matrix  
• Direct support of Cypress enCoRe IC for USB bridge  
applications  
• Wide operating voltage (2.7 to 3.6V)  
• Commercial temperature range (0°C to +70°C)  
• Low power/sleep mode (ISB < 1.0 µA typical)  
• Small package 100-pin TQFP (14 x 14 x1.4 mm)  
4
32-Byte  
FIFO  
SPI  
CYWUSB6941  
2.4 GHz Radio  
13  
Framer  
6
GPIO  
GPO  
GPI  
13  
8
7
System  
RAM  
Protocol /  
Application  
Engine  
(8KB)  
4
Boot  
EEPROM  
CYWUSB6942  
W irelessUSB EX  
Baseband  
Loader  
Figure 2-1. CYWUSB6942 Top-level Block Diagram  
Cypress Semiconductor Corporation  
Document #: 38-16005 Rev. *B  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised May 2, 2003  
CYWUSB6942  
TABLE OF CONTENTS  
1.0 FEATURES ......................................................................................................................................1  
2.0 APPLICATIONS ...............................................................................................................................1  
3.0 GENERAL DESCRIPTION ...............................................................................................................4  
3.1 Functional Overview ...................................................................................................................4  
3.1.1 Efficient and Reliable Datagram Delivery ..........................................................................................4  
3.1.2 Direct Support for Wireless Peripherals ............................................................................................4  
3.1.3 Input/Output Interfaces ......................................................................................................................5  
3.1.4 Power Management ..........................................................................................................................5  
3.1.5 Wide Operating Range ......................................................................................................................5  
4.0 ARCHITECTURE OVERVIEW .........................................................................................................5  
4.1 Framer ........................................................................................................................................5  
4.2 GPIO/GPO/GPI Blocks. ..............................................................................................................5  
4.3 SPI Block ....................................................................................................................................5  
4.4 System RAM ...............................................................................................................................5  
4.5 Protocol/Application Engine ........................................................................................................5  
5.0 INTERFACE .....................................................................................................................................6  
5.1 The Radio Control Interface ........................................................................................................6  
5.2 The SPI Interface ........................................................................................................................7  
5.2.1 Overview ...........................................................................................................................................7  
5.2.2 SPI Signaling .....................................................................................................................................7  
5.3 Serial EPROM Interface ..............................................................................................................8  
5.3.1 Functional Description .......................................................................................................................8  
5.3.2 Serial EPROM Interface Signaling ....................................................................................................9  
5.4 Interface for Wakeup and Sleep .................................................................................................9  
6.0 CYWUSB6942 PIN DESCRIPTION .................................................................................................9  
7.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................12  
8.0 OPERATING CONDITIONS ...........................................................................................................13  
9.0 DC CHARACTERISTICS ...............................................................................................................13  
10.0 SWITCHING CHARACTERISTICS ..............................................................................................13  
11.0 SWITCHING WAVEFORMS  
....................................................................................................14  
12.0 AC TEST LOADS AND WAVEFORMS FOR DIGITAL PINS ......................................................16  
13.0 ORDERING INFORMATION ........................................................................................................16  
14.0 PACKAGE DIAGRAMS ...............................................................................................................17  
Document #: 38-16005 Rev. *B  
Page 2 of 18  
CYWUSB6942  
LIST OF FIGURES  
Figure 2-1. CYWUSB6942 Top-level Block Diagram ..............................................................................1  
Figure 3-1. CYWUSB6942 Device Family Usage Scenario .................................................................... 4  
Figure 4-1. CYWUSB6942 Framer Block Diagram.................................................................................. 6  
Figure 5-1. CYWUSB6942 Radio Control Interface Diagram .................................................................. 7  
Figure 5-2. SPI Timing............................................................................................................................. 8  
Figure 5-3. CYWUSB6942 Serial EPROM Interface Diagram................................................................. 8  
Figure 5-4. Serial EPROM Interface Timing ............................................................................................ 9  
Figure 6-1. CYWUSB6942 100-pin TQFP Top View............................................................................. 12  
Figure 11-1. SPI Waveforms ................................................................................................................. 14  
Figure 11-2. Serial EPROM Interface Waveforms................................................................................. 14  
Figure 11-3. Radio Serial Interface........................................................................................................ 15  
Figure 11-4. CYWUSB6942 Reset Timing ............................................................................................ 15  
Figure 12-1. AC Test Loads and Waveforms for Digital Pins ................................................................ 16  
Figure 14-1. CYWUSB6942 100-pin TQFP Package Diagram ............................................................. 17  
LIST OF TABLES  
Table 6-1. Pin Description Table ............................................................................................................9  
Table 9-1. DC Characteristics (Over the Operating Range) .........................................................................13  
Table 10-1. Switching Characteristics (Over the Operating Range) .............................................................13  
Document #: 38-16005 Rev. *B  
Page 3 of 18  
CYWUSB6942  
3.0  
3.1  
General Description  
Functional Overview  
WirelessUSB EX enables low-cost, low-power WirelessHID solutions using 2.4-GHz Industrial Scientific Medical (ISM) band  
and frequency-hopping spread-spectrum (FHSS) technology. The CYWUSB6942 supports wireless peripheral applications such  
as optical mice, keyboards, and game controllers by transferring data between the peripherals and the host over the air through  
the WirelessUSB EX protocol.  
The CYWUSB6942 WirelessUSB EX Baseband IC is part of a two-device chipset for implementing a WirelessUSB-based appli-  
cation. The CYWUSB6941 WirelessUSB Radio IC is also needed to complete the WirelessUSB EX chipset.  
When used with a Cypress enCoRe chip, the WirelessUSB EX chipset also acts as a USB bridge to allow wireless peripherals  
using the CYWUSB6942 devices to communicate with the host via a low-speed USB link. Data received by the WirelessUSB EX  
chipset from a peripheral device is transferred to the enCoRe chip and then sent upstream to the USB host device. Downstream  
data is transferred from the enCoRe to the WirelessUSB EX chipset and then sent to the peripheral over the air. Each  
WirelessUSB EX chipset acting as a USB bridge can support up to seven peripherals.  
For more information on the WirelessUSB EX system, protocol and internal operations, see our application note entitled  
WirelessUSB EX Theory of Operation.  
Host  
WirelessUSB EX host  
using the CYWUSB6941 &  
USB  
CYWUSB6942  
WirelessUSB EX keyboard  
using the CYWUSB6941 &  
CYWUSB6942  
WirelessUSB EX optical mouse  
using the CYWUSB6941 &  
CYWUSB6942  
Figure 3-1. CYWUSB6942 Device Family Usage Scenario  
Efficient and Reliable Datagram Delivery  
3.1.1  
The WirelessUSB EX chipset implements a highly efficient, bidirectional wireless protocol designed to reliably and quickly send  
and receive data packets between devices with a high throughput of 1-Mbps raw data rate. The WirelessUSB EX Baseband  
device contains a framer, which handles all bit-level operations, maximizing available processing bandwidth in the Protocol and  
Application Engines for embedded applications. It also ensures reliable and secure datagram delivery by applying algorithms  
such as CRC, encryption, data whitening, and Forward Error Correction (FEC).  
HID datagrams are delivered over the air using a low power 2.4-GHz FHSS radio that can coexist with other 2.4-GHz systems  
(e.g., Bluetooth , IEEE 802.11b, analog cordless phones).  
3.1.2  
Direct Support for Wireless Peripherals  
The CYWUSB6942 device provides direct support for an optical mouse, an 18 × 8 keyboard scan matrix, and a USB host bridge  
applications when used with the Cypress enCoRe chip. As a result, low cost solutions can be implemented with a minimal number  
of external components required.  
Document #: 38-16005 Rev. *B  
Page 4 of 18  
CYWUSB6942  
3.1.3  
Input/Output Interfaces  
The CYWUSB6942 offers up to six general purpose input/output (GPIO) pins, twenty-one GPO pins, seven GPI pins, and a Serial  
Peripheral Interface (SPI), allowing the implementation of a wide variety of wireless HID applications including mice, keyboards,  
game controllers, and USB bridges.  
3.1.4  
Power Management  
The CYWUSB6942 provides power management, including a low battery power detection and low-power mode.  
3.1.4.1 Low Battery Power Detection  
A DC-DC converter can be used to provide the required operating voltage to the system as well as a low battery warning signal  
via the PFO pin. When the voltage levels provided by the batteries are below a preset threshold, the PFO signal should be  
asserted, allowing the CYWUSB6942 to take appropriate action.  
3.1.4.2 Low-Power Standby/Sleep Mode  
The CYWUSB6942 provides support for a very low power mode (ISB < 1.0 µA typical). For details, please refer to Section 5.4.  
3.1.5  
Wide Operating Range  
The CYWUSB6942 device is offered with wide operating voltage (2.7 to 3.6V), commercial temperature range (0°C to +70°C),  
and small package (14 x 14 mm TQFP), providing the flexibility for the implementation of a wide variety of wireless HID applica-  
tions.  
4.0  
Architecture Overview  
From a top-level, the CYWUSB6942 device consists of the WirelessUSB EX Framer, the Protocol and Application Engines, and  
a Radio Interface that allows communication with the CYWUSB6941 external 2.4-GHz radio.  
4.1  
Framer  
The Framer (Figure 4-1) handles all bit-wise data packet operations. It retrieves transmit packet header information from the  
Protocol Engine, payload data from the System RAM, and processes them for transmission by the radio. Data received from the  
radio is processed into packets, and handed over to the Protocol Engine and System RAM. Functions include error correction,  
encryption/decryption, whitening/dewhitening, encoding/decoding, channel selection, correlation, synchronization, and data clock  
recovery. The Framer is controlled by the Protocol Engine, and directly DMAs data to and from the System RAM.  
4.2  
GPIO/GPO/GPI Blocks.  
The GPIO (Figure 2-1) block contains up to six independently configurable I/O pins. The General Purpose Output (GPO) block  
contains up to twenty-one output pins. The General Purpose Input (GPI) block contains up to seven input pins.  
4.3  
SPI Block  
The SPI Block (Figure 2-1) is a slave mode serial interface block. Data is not returned to a tri-state mode after SS is deasserted.  
4.4  
System RAM  
The 8-KB System RAM acts as the data interface between the Protocol Engine and the WirelessUSB EX Framer for transmitting  
and receiving HID datagrams.  
4.5  
Protocol/Application Engine  
The Protocol Engine is used to implement the link control protocol. It manages low level packet traffic, link set-up and breakdown,  
and transfers data between the HID and the WirelessUSB EX Packet Engine.  
The Application Engine executes application-specific functions for a variety of HIDs, such as mice, keyboards, and gamepads.  
Document #: 38-16005 Rev. *B  
Page 5 of 18  
CYWUSB6942  
Transmit  
Data DMA  
Controller  
TX  
HEC/CRC  
Encryptor  
Whitener  
Encoder  
FROM  
Packet  
Buffer  
Transmit  
Data  
to  
Radio  
Packet / Payload  
Header Storage /  
Decode  
Transmit Bitstream FSM  
Packet / Payload  
Header Storage /  
Decode  
Receive Bitstream FSM  
Receive  
Data  
from  
TO  
Packet  
Buffer  
Radio  
Receive  
Data DMA  
Controller  
Decrypter  
HEC/CRC  
Dewhitener  
Decoder  
Correlator  
RX  
Figure 4-1. CYWUSB6942 Framer Block Diagram  
5.0  
5.1  
INTERFACE  
The Radio Control Interface  
The CYWUSB6942 radio control interface is the communication interface between the WirelessUSB EX baseband and the  
CYWUSB6941 WirelessUSB EX Radio. It consists of a data interface and a control interface for transmitting and receiving data,  
and a serial interface for programming the internal registers of the CYWUSB6941.  
There are four subsections of the interface:  
• RF data  
• Control interface  
• Register control interface (serial)  
• Master clock.  
There are two data lines in the RF data interface and seven signals that are used in the RF control interface, four signals in the  
serial register control interface, and one system clock. All of the signals are unidirectional. Direction is oriented to/from the  
CYWUSB6942 baseband IC.  
Document #: 38-16005 Rev. *B  
Page 6 of 18  
CYWUSB6942  
Data Interface  
BTXD  
BRXD  
Control Interface  
BRCLK  
BTXEN  
BRXEN  
BPAEN  
WirelessUSB  
EX Baseband  
CYWUSB6942  
WirelessUSB  
EX Radio IC  
CYWUSB6941  
BSEN  
BXTLEN  
BnPWR  
Serial Interface  
BDCLK  
BnDEN  
BMOSI  
BMISO  
Master Clock  
BCLK13M  
Figure 5-1. CYWUSB6942 Radio Control Interface Diagram  
5.2  
The SPI Interface  
5.2.1  
Overview  
The SPI is a four-pin serial interface that the CYWUSB6942 uses to communicate with external devices. The SPI is a master/slave  
interface with the CYWUSB6942 always acting as a slave. The pins used are the SS (Slave Select), SCK (Serial Clock), MOSI  
(Master-Out/Slave-In), and MISO (Master-In/Slave-Out) pins.  
5.2.2  
SPI Signaling  
The SS, SCK, and MOSI signals are all driven by the master while the CYWUSB6942 drives only the MISO signal. To initiate a  
byte transfer, the master asserts the SS signal and provides the SCK signal as a clock for the interface. The MOSI data is driven  
out by the master on the rising edge of SCK and sampled by the CYWUSB6942 on the falling edge of SCK. The MISO data is  
driven out by the CYWUSB6942 on the rising edge of SCK and sampled by the master on the falling edge of SCK. One bit is  
transferred per clock cycle, and one byte is transferred in a total of eight clock cycles. Once the transfer is complete, the master  
can deassert the SS, SCK, and MOSI pins.  
Document #: 38-16005 Rev. *B  
Page 7 of 18  
CYWUSB6942  
SS  
SCK  
MOSI  
MISO  
[1]  
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1  
LSB  
LSB  
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1  
Figure 5-2. SPI Timing  
MSB BIT 6  
BIT 5 BIT 4  
BIT 3  
BIT 2 BIT 1  
LSB  
5.3  
Serial EPROM Interface  
5.3.1  
Functional Description  
When the CYWUSB6942 powers up, the firmware is loaded by the internal boot loader via a serial EPROM interface with the  
CYWUSB6942 being the master and the EPROM being the slave.  
This is a four-pin interface that includes the EECS (Chip Select), EESCK (Serial Clock), EEMOSI (EPROM Serial output), and  
EEMISO (EPROM Serial input) pins.  
VCC  
CYWUSB6942  
CYWUSB6941  
RA DIO  
Inter f ac e  
2.4GHz  
Radio  
Serial  
EPROM  
Interface  
SPI  
EPROM  
SS  
EECS  
SCK  
EESCK  
MOSI  
MISO  
EEMOSI  
EEMISO  
GND  
Figure 5-3. CYWUSB6942 Serial EPROM Interface Diagram  
Note:  
1. Data lines do not three-state.  
Document #: 38-16005 Rev. *B  
Page 8 of 18  
CYWUSB6942  
5.3.2  
Serial EPROM Interface Signaling  
The EECS, EESCK, and EEMOSI signals are all driven by the CYWUSB6942 acting as a master, while the EPROM (slave) drives  
only the EEMISO signal. To initiate a byte transfer, the CYWUSB6942 asserts the EECS signal and provides the EESCK signal  
as a clock for the interface. The EEMOSI data is driven out by the CYWUSB6942 on the falling edge of SCK (the MSB is available  
on the falling edge of EECS) and sampled by the EPROM on the rising edge of SCK. The EEMISO data is driven out by the  
EPROM on the falling edge of EESCK and sampled by the CYWUSB6942 on the rising edge of EESCK. One bit is transferred  
per clock cycle, and one byte is transferred in a total of eight clock cycles. Once the transfer is complete, the CYWUSB6942 will  
drive the EECS pin high.  
EECS  
EESCK  
EEMISO  
EEMOSI  
MSB  
MSB  
BIT 6  
BIT 6  
BIT 5  
BIT 5  
BIT 4  
BIT 4  
BIT 3  
BIT 3  
BIT 2  
BIT 2  
BIT 1  
BIT 1  
LSB  
LSB  
Figure 5-4. Serial EPROM Interface Timing  
Interface for Wakeup and Sleep  
5.4  
Power management is crucial to preserving battery life for WirelessHID applications, and the CYWUSB6942 provides the flexi-  
bility of power control at the hardware level, offering a low-power standby/sleep mode.  
To enable the low-power mode of this device, the external signal XTLEN must first be driven low. This will set up the low-power  
condition. Once the chip has set itself in a condition for low power, it will set the output signal BXTLEN to a low condition. This  
signals the chip is ready to have its clock stopped. The clock should then be stopped at a logic low.  
6.0  
CYWUSB6942 Pin Description  
Table 6-1. Pin Description Table  
Pin Name Type Default  
Control Interface  
Description  
32  
RESET  
Input  
Z
Active LOW Reset. Resets the entire chip. This pin is normally tied to VCC through a  
10K resistor, and to GND through a 1-µF capacitor.  
51  
33  
CLKOUT  
O/Z  
N/A CLKOUT needs to be connected to MODESEL.  
MODESEL Input  
Z
MODESEL must to be connected to either the input clock: BCLK13M or be driven by  
the base band’s output clock: CLKOUT.  
19  
35  
BCLK13M  
XTLEN  
Input  
Input  
Z
Z
System Clock. 13-MHz system clock.  
Crystal Oscillator Enable. Enable signal for the clock. When XTLEN is deasserted the  
device goes into sleep mode.  
Port A  
94  
PA0  
PA1  
PA2  
PA3  
PA4  
PA5  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
Z
Z
Z
Z
Z
Z
Port A [5:0] is a bidirectional I/O bus.  
93  
88  
87  
84  
83  
Document #: 38-16005 Rev. *B  
Page 9 of 18  
CYWUSB6942  
Table 6-1. Pin Description Table (continued)  
Pin  
Port B  
59  
Name  
Type Default  
Description  
PB0  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Port B [12:0]. This bus can be used to drive large pin-count applications (e.g., keyboard  
scan matrix).  
58  
PB1  
PB2  
PB3  
PB4  
PB5  
PB6  
PB7  
PB8  
PB9  
PB10  
PB11  
PB12  
57  
56  
55  
54  
47  
46  
45  
44  
43  
42  
41  
Port C  
65  
PC0  
PC1  
PC2  
PC3  
PC4  
Output  
Output  
Output  
Output  
Output  
0
0
0
0
0
Port C[4:0]. This bus can be used to drive large pin-count applications (e.g., keyboard  
scan matrix or control signal for optical mouse)  
66  
67  
81  
82  
General Purpose Inputs/Slave Peripheral Interface (four wires)  
90  
89  
GPI0/SS  
Input  
Input  
Z
Z
GPI0. General Purpose Input.  
(Slave Select) Sync Clock. Provides clock synchronization for the serial data transfer.  
GPI1. General Purpose Input.  
GPI1/SCK  
Serial Bit Clock. Driven by the Serial interface master device.  
91  
92  
MISO  
MOSI  
Output  
Input  
0
Z
MISO. MISO is for a slave device to transmit data to a Serial Interface master device.  
On this bus, this chip is the slave device.  
MOSI. MOSIis for aslave devicetoreceive datafrom the Serial Interfacemaster device.  
On this bus, this chip is the slave device.  
38  
36  
37  
31  
GPI2  
GPI3  
GPI4  
GPI5  
Input  
Input  
Input  
Input  
Z
Z
Z
Z
GPI2. General Purpose Input.  
GPI3. General Purpose Input.  
GPI4. General Purpose Input.  
GPI5. General Purpose Input.  
Serial EPROM Interface  
60  
61  
64  
EECS /  
PC5  
Output  
0
0
Chip Select. Chip select for EEPROM interface.  
PC5. Part of GPO block after reset boot process.  
EESCK /  
PC6  
Output  
Serial Clock. Serial clock for EEPROM interface.  
PC6. Part of GPO block after reset boot process.  
EEMOSI / Output  
PC7  
O
Serial Output. Serial output for EEPROM interface. On this bus, this chip is the master  
device and the EEPROM is the slave device.  
PC7. Part of GPO block after reset boot process.  
34  
EEMISO /  
GPI6  
Input  
Z
Serial Input. Serial input for EEPROM interface. On this bus, this chip is the master  
device and the EEPROM is the slave device.  
GPI6. Part of GPI block after reset boot process.  
Document #: 38-16005 Rev. *B  
Page 10 of 18  
CYWUSB6942  
Table 6-1. Pin Description Table (continued)  
Pin Name Type Default  
Radio Control Interface  
Description  
21  
18  
17  
15  
9
BTXD  
Output  
Input  
0
Z
Z
0
Z
0
0
Transmit Data. Transmit data output port.  
Receive Data. Demodulated and sliced digital receive data.  
BRXD  
BRCLK  
BPAEN  
BRXEN  
BTXEN  
BSEN  
Input  
Transmit Clock. 1 MHz clock associated with the transmit data.  
Output  
Output  
Output  
Output  
Power Amplifier Enable. Enables the PA in transmit mode. Active HIGH.  
Receive Circuitry Enable. This signal enables the receive circuitry. Active HIGH.  
Transmit Circuitry Enable. This signal enables the transmit circuitry. Active HIGH.  
Synthesizer Enable. This signal enables the hop synthesizer. Active HIGH.  
22  
20  
14  
24  
BnPWR  
BXTLEN  
Output RESET Power On Reset. This signal is active LOW.  
Output  
1
Crystal Oscillator Enable. This signal enables the crystal oscillator or the external  
13-MHz clock, if provided. Active HIGH.  
16  
Reserved  
NC  
N/A No connect  
Radio Serial Interface Pins  
12  
BMOSI  
Output  
0
Output Data. This is the serial data output pin. On this bus, this chip is the master  
device.  
11  
10  
13  
BMISO  
BDCLK  
BnDEN  
Input  
Output  
Output  
Z
Z
Z
Input Data. This is the serial data input pin. On this bus, this chip is the master device.  
Output Clock. This is the serial register clock.  
Enable. This signal enables the serial communication.  
Reserved Pins  
28  
23  
Reserved Must be tied to GND.  
Reserved  
NC  
N/A No connect  
VCC and GND pins  
8
29  
VCC  
GND  
NC  
Power  
N/A VCC pins. Power supply for digital logic.  
39  
52  
62  
85  
95  
25  
Ground  
N/A Ground pins.  
30  
40  
53  
63  
86  
96  
1-7  
26-27  
48-50  
68-80  
97-100  
N/A Not connected pins.  
Document #: 38-16005 Rev. *B  
Page 11 of 18  
CYWUSB6942  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76  
NC  
NC  
1
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
2
NC  
NC  
3
NC  
NC  
NC  
4
NC  
5
NC  
NC  
6
NC  
NC  
7
NC  
VCC  
8
NC  
BRXEN  
BDCLK  
BMISO  
BMOSI  
BnDEN  
BnPWR  
BPAEN  
BPKTCTL  
BRCLK  
BXRD  
BCLK13M  
BSEN  
BTXD  
BTXEN  
BRTM  
9
PC2  
PC1  
PC0  
EEMOSI  
GND  
VCC  
EESCK  
EECS  
PB0  
PB1  
PB2  
PB3  
PB4  
PB5  
GND  
VCC  
CLKOUT  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
CYWUSB6942  
BXTLEN  
GND  
24  
25  
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
Figure 6-1. CYWUSB6942 100-pin TQFP Top View  
7.0  
Absolute Maximum Ratings  
Storage Temperature .................................–65°C to +150°C  
Ambient Temperature with Power Applied..–55°C to +125°C  
Supply Voltage on VCC relative to VSS........... –0.3V to +3.9V  
DC Input Voltage .................................. –0.3V to VCC + 0.3V  
DC Voltage Applied to Outputs in High-Z State –0.3V to VCC + 0.3V  
Static Discharge voltage (Digital)[2].......................... > 2000V  
Latch-up current..................................................... + 200 mA  
Note:  
2. Rating measured using the Human Body Model (HBM).  
Document #: 38-16005 Rev. *B  
Page 12 of 18  
CYWUSB6942  
8.0  
Operating Conditions  
VCC (Supply Voltage)......................................... 2.7V to 3.6V  
TA (Ambient Temperature Under Bias) .............0°C to +70°C  
Ground Voltage..................................................................0V  
FCLK (BCLK13M)........................................13 MHz ± 20 ppm  
..........................................................duty cycle: 40% to 60%  
9.0  
DC Characteristics  
Table 9-1. DC Characteristics (Over the Operating Range)  
Parameter  
Description  
Supply Voltage  
Conditions  
Min.  
Typ.  
Max.  
3.6  
Unit  
V
VCC  
ICC  
ISB  
VIH  
VIL  
II  
2.7  
Operating Supply Current  
Low-power Mode Current  
Input High Voltage  
38  
50  
mA  
µA  
V
1.0  
10.0  
VCC  
0.8  
2.0  
–0.3  
Input Low Voltage  
V
Input Leakage Current  
Output Voltage High  
Output Voltage High  
Output Low Voltage  
Output Leakage Current  
Pin Capacitance  
0< VIN < VCC  
–1  
+1  
µA  
V
VOH1  
IOH = –100 µA  
VCC – 0.2  
2.4  
[3]  
VOH2  
IOH = –1.6 mA  
V
VOL  
IOZ  
IOL= 1.6 mA  
0.4  
+1  
8
V
0 <= VO <= VCC Output Disabled  
–1  
µA  
pF  
CPIN  
10.0  
Switching Characteristics  
Table 10-1. Switching Characteristics (Over the Operating Range) [4]  
Parameter Description  
SPI  
Min. Typ. Max. Unit  
tSCK  
tSCKH  
tSCKL  
tSSS  
tSSH  
tSSU  
tSHD  
tSDO  
SCK period  
590[5]  
435[5]  
155  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Minimum pulse width HIGH for SCK  
Minimum pulse width LOW for SCK  
Slave Select Set-up Time before first positive edge of SCK edge  
Slave Select Hold Time after last negative edge of SCK edge  
0
Slave Input Data Set-up Time, data stable (on MOSI) before negative edge of SCK  
Slave Input Data Hold Time, data stable (on MOSI) after negative edge of SCK  
Slave Data Output Time from positive edge of SCK to data valid (on MISO)  
10  
5
435  
Serial EPROM Interface  
tEESCK  
tEESCKH  
tEESCKL  
tEESSS  
tEESSH  
tEESSU  
SCK frequency  
1
MHz  
ns  
Minimum pulse width HIGH for EESCK  
535  
458  
455  
–2  
Minimum pulse width LOW for EESCK  
ns  
Slave Select Set-up Time before first EESCK edge  
Slave Select Hold Time after last EESCK edge  
ns  
ns  
Slave Input Data Set-up Time, data stable (on EEMOSI) before positive edge of  
EESCK  
12  
ns  
tEESHD  
Slave Input Data Hold Time, data stable (on EEMOSI) after positive edge of EESCK  
Slave Data Output Time from positive edge of SCK to data valid (on EEMISO)  
0
ns  
ns  
tEESDO  
10  
Notes:  
3. VOH2 applies to pins PC[4:0], EESI, EESCK, EECS_N, and X13OUT. All other output pins use VOH1  
.
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of 10-pF  
load capacitance to ground.  
5. For minimum tSCKH or tSCK requires setup time of master device to be zero ns (tSUMD). If the master device has a setup time greater than zero you must add  
the setup time to tSCKH and tSCK  
.
Document #: 38-16005 Rev. *B  
Page 13 of 18  
CYWUSB6942  
Table 10-1. Switching Characteristics (Over the Operating Range) (continued)[4]  
Parameter  
Description  
Min. Typ. Max. Unit  
Radio Serial Interface Pins  
tBDCLK  
Clock period  
302  
131  
156  
55  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tBDCLKH  
tBDCLKL  
Clock minimum pulse width HIGH  
Clock minimum pulse width LOW  
tBMISOSU  
tBMISOHD  
tBnDENSDO  
tBMOSISDO  
Input Data Setup Time, data stable on BMISO to positive edge of BDCLK  
Input Data Hold Time, data stable on BMISO from positive edge of BDCLK  
Data Output Time from negative edge of BDCLK to BnDEN Valid  
Data Output Time from negative edge of BDCLK to BMOSI Valid  
5
5
Power Management Timing  
tR1C1  
Minimum RESET length (BCLK13M valid during this time)  
100  
µs  
11.0  
Switching Waveforms  
SS  
tSSS  
tSSH  
tSCKL  
SCK  
tSCKH  
MOSI  
MSB  
LSB  
tSDO  
tSSU tSHD  
MSB  
LSB  
MISO  
Figure 11-1. SPI Waveforms  
EECS  
t
EESSS  
t
EESSH  
t
EESCKL  
EESCK  
t
EESCKH  
tEESSU  
tEESHD  
LSB  
MSB  
EEMISO  
EEMOSI  
t
ESSDO  
MSB  
LSB  
Figure 11-2. Serial EPROM Interface Waveforms  
Document #: 38-16005 Rev. *B  
Page 14 of 18  
CYWUSB6942  
tBDCLK  
tBDCLKL  
tBDCLKH  
BDCLK  
BnDEN  
tBnDENSDO  
BMISO  
BMOSI  
tBDMOSISDO  
tBDMISOHD  
tBDMISOSU  
Figure 11-3. Radio Serial Interface  
Vcc  
BCLK13M  
~tR1C1  
* tR1C1 > (Oscillator startup + 8 clock cycles)  
RESET  
Figure 11-4. CYWUSB6942 Reset Timing  
Document #: 38-16005 Rev. *B  
Page 15 of 18  
CYWUSB6942  
12.0  
AC Test Loads and Waveforms for Digital Pins  
AC Test Loads  
OUTPUT  
OUTPUT  
5 pF  
30 pF  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
Max  
Typical  
DC Test Load  
R1  
VCC  
OUTPUT  
R2  
THÉ  
Equivalent to:  
OUTPUT  
VENIN EQUIVALENT  
ALL INPUT PULSES  
RTH  
VCC  
VTH  
90%  
10%  
90%  
10%  
GND  
Parameter  
R1  
Unit  
Ω
Fall time: 1 V/ns  
Rise time: 1 V/ns  
1071  
937  
500  
1.4  
R2  
Ω
RTH  
Ω
VTH  
V
VCC  
3.00  
V
Figure 12-1. AC Test Loads and Waveforms for Digital Pins  
13.0  
Ordering Information  
Package  
Name  
Part Number  
CYWUSB6942-100AC  
Package Type  
Operating Range  
TQFP-A100  
100-pin Thin Plastic Quad Flat Pack (14 × 14 × 1.4 mm)  
Commercial  
Document #: 38-16005 Rev. *B  
Page 16 of 18  
CYWUSB6942  
14.0  
Package Diagrams  
100-pin Thin Plastic Quad Flat Pack (TQFP) A100  
51-85048-*B  
Figure 14-1. CYWUSB6942 100-pin TQFP Package Diagram  
For feedback or technical support regarding Cypress products please contact Cypress at www.cypress.com. This document is  
subject to change, and may be found to contain errors of omission or changes in parameters. The reader is encouraged to provide  
any information to Cypress Semiconductor that may be of use in improving this document.  
Bluetooth and the Bluetooth logos are trademarks owned by Bluetooth SIG. enCoRe and WirelessUSB are trademarks of Cypress  
Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-16005 Rev. *B  
Page 17 of 18  
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYWUSB6942  
Document History Page  
Document Title: CYWUSB6942 WirelessUSB™ EX Baseband IC  
Document Number: 38-16005  
Issue  
Date  
Orig. of  
Change  
REV.  
**  
ECN No.  
122945  
124456  
Description of Change  
12/11/02  
05/09/03  
LXA  
KKU  
New Data Sheet  
Removed application note material.  
*A  
Updated block diagrams, signal names, timing and characterization data.  
*B  
128045  
08/01/03  
KKU  
Updated from Preliminary to Final  
Updated package references in sections 13.0 and 1.0  
Document #: 38-16005 Rev. *B  
Page 18 of 18  
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