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CYWB0124AB

CYWB0125AB

West Bridge^®Antioch™

USB/Mass Storage Peripheral Controller

West Bridge^®Antioch™ USB/Mass Storage Peripheral Controller

Features

Applications

■ SLIM™ architecture, enabling simultaneous and independent

data paths between processor and USB, and between USB

and mass storage

■ Cellular phones

■ Portable media players

■ Personal digital assistants

■ Digital cameras

■ High speed USB at 480 Mbps

❐ USB-2.0 compliant

❐ Integrated USB 2.0 transceiver, smart serial interface engine

❐ 16 programmable endpoints

■ Portable video recorder

■ Mass storage device support

❐ MMC/MMC+/SD/CE-ATA

❐ NAND flash: × 8 or × 16, SLC

❐ Full NAND management (ECC, wear leveling)

■ Memory mapped interface to main processor

■ DMA slave support

■ Supports Microsoft^®media transfer protocol (MTP) with

optimized data throughput

■ Ultra low power, 1.8 V core operation

■ Low power modes

■ Small footprint, 6 × 6 mm VFBGA, and less than 4 × 4 mm

WLCSP

■ Selectable clock input frequencies

❐ 19.2 MHz, 24 MHz, 26 MHz, and 48 MHz

Logic Block Diagram

West Bridge Antioch

Control

Registers

8051

MCU

P

U

SLIM^TM

Mass Storage Interface

SD/MMC+/CE-ATA

NAND

S

Cypress Semiconductor Corporation

Document Number: 001-07978 Rev. *O

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 1, 2017

CYWB0124AB

CYWB0125AB

Contents

Functional Overview ........................................................3

SLIM™ Architecture ....................................................3

Turbo-MTP Support .....................................................3

8051 Microprocessor ...................................................3

Configuration and Status Registers .............................3

Processor Interface (P-port) ........................................3

USB Interface (U-Port) ................................................3

Mass Storage Support (S-Port) ...................................3

Clocking .......................................................................4

Power Domains ...........................................................5

Power Modes ..............................................................5

Antioch in WLCSP .......................................................6

Absolute Maximum Ratings ..........................................12

Operating Conditions .....................................................12

DC Characteristics .........................................................12

USB Transceiver .......................................................14

Capacitance ....................................................................14

AC Test Loads and Waveforms .....................................14

AC Characteristics .........................................................15

USB Transceiver .......................................................15

P-Port Interface .........................................................15

SD/MMC Parameters ................................................22

Reset and Standby Timing Parameters ....................23

Ordering Information ......................................................24

Ordering Code Definitions .........................................24

Package Diagrams ..........................................................25

Acronyms ........................................................................27

Document Conventions .................................................27

Units of Measure .......................................................27

Document History Page .................................................28

Sales, Solutions, and Legal Information ......................31

Worldwide Sales and Design Support .......................31

Products ....................................................................31

PSoC®Solutions .......................................................31

Cypress Developer Community .................................31

Technical Support .....................................................31

Document Number: 001-07978 Rev. *O

Page 2 of 31

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CYWB0125AB

Processor Interface (P-port)

Functional Overview

Communication with the external processor is realized through a

dedicated processor interface. This interface supports both

synchronous and asynchronous SRAM mapped memory

SLIM™ Architecture

The Simultaneous Link to Independent Multimedia (SLIM)

architecture allows three different interfaces (the P-port, the

S-port, and the U-port) to connect to one another independently.

accesses.

This

ensures

straightforward

electrical

communications with the processor that also has other devices

connected on a shared memory bus. Asynchronous accesses

reach a bandwidth of up to 66.7 MBps. Synchronous accesses

are performed at 33 MHz across 16 bits for up to 66.7 MBps

bandwidth.

With this architecture, using Antioch™ to connect a device to a

PC through an USB does not disturb the functions of the device.

It still accesses mass storage at the same time the PC is

synchronizing with the main processor.

The memory address is decoded to access any of the multiple

endpoint buffers inside Antioch. These endpoints serve as

buffers for data between each pair of ports, for example, between

the processor port and the USB port. The processor writes and

reads into these buffers through the memory interface.

The SLIM architecture enables new usage models, in which a

PC accesses a mass storage device independent of the main

processor, or enumerates access to both the mass storage and

the main processor at the same time.

In a handset, this typically enables the user to use the phone as

a thumb drive or download media files to the phone while still

having full functionality available on the phone. The same phone

even functions as a modem to connect the PC to the web.

Access to these buffers is controlled by using either a DMA

protocol or an interrupt to the main processor. These two modes

are configured by the external processor.

As a DMA slave, Antioch generates a DMA request signal to

signify to the main processor that it is ready to read from or write

to a specific buffer. The external processor monitors this signal

and polls Antioch for the specific buffers ready for read or write.

It then performs the appropriate read or write operations on the

buffer through the processor interface. This way, the external

processor only deals with the buffers to access a multitude of

storage devices connected to Antioch.

Turbo-MTP Support

Turbo-MTP is an implementation of Microsoft’s Media Transfer

Protocol (MTP) enabled by West Bridge^®Antioch™. In the

current generation of MTP-enabled mobile phones, all protocol

packets need to be handled by the main processor. West Bridge

Turbo-MTP switches these packet types and sends only control

packets to the processor, while data payloads are written directly

to mass storage. This brings the high performance of West

Bridge to MTP. For more information on Turbo-MTP, refer to the

application note AN48864 “Performance Optimization by West

Bridge Controllers with Turbo-MTP”.

In the Interrupt mode, Antioch communicates important buffer

status changes to the external processor using an interrupt

signal. The external processor then polls Antioch for the specific

buffers ready for read or write and performs the appropriate read

or write operations through the processor interface.

8051 Microprocessor

USB Interface (U-Port)

The 8051 microprocessor embedded in Antioch does basic

transaction management for all the transactions between the

P-port, the S-port, and the U-port. The 8051 does not reside in

the data path; it manages the path. The data path is optimized

for performance. The 8051 executes firmware that supports

NAND, SD, and MMC devices at the S-port. For the NAND

device, the 8051 firmware follows the Smart Media algorithm to

support:

In accordance with the USB 2.0 specification, Antioch operates

in Full Speed USB mode in addition to High Speed USB mode.

The USB interface consists of the USB transceiver. The USB

interface accesses and also is accessed by both the P-port and

the S-port.

The Antioch USB interface supports programmable

CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints.

■ Physical to Logical Management

■ ECC Correction

Mass Storage Support (S-Port)

The S-port is configured in two different modes, either

simultaneously supporting an SD/MMC+ port and a × 8 NAND

port or supporting a unique × 16 NAND access port. The

NANDCFG Ball is used to set the configuration of the S-port as

either 16-bit NAND or 8-bit NAND and SD/MMC. The 16-bit

interface is only used when there is no other mass storage

device connected to the S-port. Note that in the WLCSP option,

the S-port is not configurable; it only supports a single SD/MMC+

port with no NAND port.

■ Wear Leveling

■ NAND Flash Bad Block Handling

Configuration and Status Registers

The West Bridge Antioch device includes Configuration and

Status registers that are accessible as memory mapped registers

through the processor interface. The Configuration registers

allow the system to specify certain behavior from Antioch. For

example, it masks certain Status registers from raising an

interrupt. The Status registers convey the status of different

parameters of Antioch, such as the addresses of buffers for read

operations.

Antioch also includes two chip enables, NAND_CE# and

NAND_CE2#, that enable to access two different NANDs

alternately.

Document Number: 001-07978 Rev. *O

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NAND Port (S-Port)

Clocking

Antioch, as part of its mass storage management functions, fully

manages a NAND device. The embedded 8051 manages the

actual reading and writing of the NAND along with its required

protocols. It performs standard NAND management functions

such as ECC and wear leveling.

Antioch allows either to connect a crystal between the XTALIN

and XTALOUT balls or connect an external clock at the XTALIN

ball. The power supply level at the crystal supply XVDDQ

determines whether a crystal or a clock is provided. If XVDDQ is

detected as 1.8 V, Antioch assumes that a clock input is

provided. This clock input must be a 1.8 V square wave. To

connect a crystal, XVDDQ must be 3.3 V. Note that the clock

inputs at 3.3 V level are not supported.

SLC NAND devices are supported on all devices in the Antioch

family. The write performance for connecting to a single SLC

NAND is up to 9 MBps, while read performance is up to 13 MBps.

CYWB0124AB supports crystals only at 19.2, 24, and 26 MHz.

At 48 MHz, only clock inputs are supported. Clock inputs are

supported at all frequencies.

SD/MMC/CE-ATA Port (S-Port)

When Antioch is configured through NANDCFG to support

MMC/SD/CE-ATA, this interface supports:

Antioch has an on-chip oscillator circuit that uses an external

19.2/24/26 MHz (±150 ppm) crystal with the following

characteristics:

■ The MultiMediaCard System Specification, MMCA Technical

Committee, Version 4.1

■ Parallel resonant

■ SD Memory Card Specification - Part 1, Physical Layer

Specification, SD Group, Version 1.10, October 15, 2004, and

Version 2.0, November 9, 2005

■ Fundamental mode

■ 1 mW drive level

■ CE-ATA Digital Protocol, Rev 1.1, 28 September, 2005 and

CE-ATA Host Design Guidance, Rev 1.0, 29 September, 2005

■ 12 pF (5% tolerance) load capacitors ^[1]

West Bridge Antioch provides support for 1-bit and 4-bit SD

cards: 1-bit, 4-bit, and 8-bit MMC, and MMC+. For the SD,

MMC/MMC Plus card, this block supports one card for one

physical bus interface.

Figure 1. Capacitor

24 MHz

PLL

C1

C2

12 pF

Antioch supports SD commands including the multisector

program command that is handled by the API.

12 pF

Compatibility with specific CE-ATA HDD is subject to

confirmation with drive vendors.

12 pF capacitor values assumes a trace capacitance

of 3 pF per side on a four-layer FR4 PCA

Table 1. External Clock Requirements

Specification

Parameter

Description

Input Phase Noise at 100 Hz Offset

Unit

Min

–

Max

PN_100Hz

PN_1k

–75

–104

–120

–128

–130

70

dBc/Hz

%

Input Phase Noise at 1 kHz Offset

Input Phase Noise at 10 kHz Offset

Input Phase Noise at 100 kHz Offset

Input Phase Noise at 1 MHz Offset

Duty Cycle

–

PN_10k

PN_100k

PN_1M

–

30

–

Maximum Frequency Deviation

Overshoot

150

3

ppm

–

%

Undershoot

–

-3

%

Note

1. Specified as typical for 24 MHz frequency. Load capacitance varies with crystal vendor specifications and frequency used.

Document Number: 001-07978 Rev. *O

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This on-chip PLL multiplies the 19.2/24/26/48 MHz frequency up

to 480 MHz, as required by the transceiver/PHY. The internal

counters divide it down for use as the 8051 clock. The 8051 clock

frequency is 48 MHz. The XTALIN frequency is independent of

the clock/data rate of the 8051 microprocessor or any of the

device interfaces (including P-port and S-port). The internal PLL

applies the proper clock multiply option depending on the input

frequency.

Noise guideline for all supplies except AVDDQ is a maximum of

100 mV p-p. All I/O supplies of Antioch are ON when a system

is active, even if Antioch is not used. The core V_DDis also

deactivated at any time to preserve power, provided that there is

a minimum impedance of 1 k between the V_DDBall and ground.

All I/Os tri-state when the core is disabled.

Power Supply Sequence

The power supplies are independently sequenced without

damaging the part. All power supplies are up and stable before

the device operates. If all supplies are not stable, the remaining

domains are in low power (standby) mode.

For applications that use an external clock source to drive

XTALIN, the XTALOUT Ball is left floating. The external clock is

a square wave that conforms to high and low voltage levels

mentioned in Table 3 on page 12 and the rise and fall time

specifications in Figure 5 on page 14. The external clock source

also stops high or low and is not toggling to achieve the lowest

possible current consumption. The requirements for an external

clock source are shown in Capacitance on page 14.

Flexible I/Os

Each of Antioch’s ports operate between 1.8 V and 3.3 V with

adjustable slew rate for each port and adjustable drive strength

for each port for the I/Os. The slew rate and drive strength are

controlled by registers.

Power Domains

Antioch has multiple power domains that serve different

purposes within the chip.

Power Modes

In addition to the normal operating mode, Antioch contains

several low power modes when normal operation is not required.

*VDDQ. This refers to a group of five independent supply

domains for the digital I/Os. The nominal voltage level on these

supplies are 1.8 V, 2.5 V, or 3.3 V. Specifically, the four separate

I/O power domains are:

Normal Mode

In this mode, Antioch is fully functional. This is the mode in which

the data transfer functions described in this datasheet are

performed.

■ PVDDQ – P-port processor interface I/O

■ SNVDDQ – S-port NAND interface I/O

■ SSVDDQ – S-port SD interface I/O

■ GVDDQ – Other miscellaneous I/O

Suspend Mode

This mode is entered internally by 8051 (external processor only

initiates entry into this mode through Mailbox commands). This

mode is exited by the D+ bus going low, GPIO[0] going to a

predetermined state, or by asserting CE# LOW.

UVDDQ. This is the 3.3 V nominal supply for the USB I/O and

some analog circuits. It also supplies power to the USB

transceiver.

In Suspend mode of Antioch:

■ The clocks are shut off.

VDD33. This supply is required for the power sequence control

circuits. For more information, see Table 2 on page 7.

V

_DD. This is the supply voltage for the logic core. The nominal

■ All I/Os maintain their previous state.

■ Core power supply are retained.

supply voltage level is 1.8 V. This supplies the core logic circuits.

The same supply is also used for AVDDQ.

■ The states of the Configuration registers, endpoint buffers, and

the program RAM are maintained. All transactions are

completed before Antioch enters Suspend mode (state of

outstanding transactions are not preserved).

AVDDQ. This is the 1.8 V supply for PLL and USB serializer

analog components. The same supply is also used for V_DD

.

Maximum permitted noise on AVDDQ is 20 mV p-p.

XVDDQ. This is the clock I/O supply. 3.3 V for XTAL or 1.8 V for

an external clock.

■ The firmware resumes its operation from where it has

suspended, because the program counter is not reset.

Figure 2. Antioch Power Supply Domains

■ The only inputs that are sensed are RESET#, GPIO[0], D+, and

CE#. The last three are wakeup sources (each is individually

enabled or disabled).

VDD

UVDDQ

D+

D-

*VDDQ

■ Hard reset is performed by asserting the RESET# input and

Antioch performs initialization.

I/O

D-CORE

USB-IO

Document Number: 001-07978 Rev. *O

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CYWB0125AB

Standby Mode

requirement of a minimum impedance of 1 k between the V_DD

ball and ground remains unchanged.

Standby mode is a low power state. This is the lowest power

mode of Antioch while still maintaining external supply levels.

This mode is entered through the deassertion of the WAKEUP

input ball or through internal register settings. It is exited by

asserting the WAKEUP Ball if the mode is entered by

deasserting the WAKEUP Ball. Exiting Standby mode is also

accomplished by asserting CE# LOW or processor writes to

Internal registers.

In the WLCSP option, AVDDQ is internally tied to XVDDQ. As a

result, the clock input at XTALIN must be brought to a steady

LOW level before entry into Core Power Down mode.

Antioch in WLCSP

Antioch is available in a Wafer Level Chip Scale Package

(WLCSP) with 81 balls. The WLCSP differs from the VFBGA in

the following ways:

In this mode, the following characteristics apply:

■ The XTALIN input only accepts clock inputs and no crystals.

The XTALOUT ball and the XVDDQ power domain do not exist

in this package. The XVDDQ power domain is internally

combined with AVDDQ.

■ All Configuration register settings and program RAM contents

are preserved. However, data in the buffers or other parts of

the data path, if any, is not guaranteed in values. Therefore,

the external processor ensures that the required data is read

before Antioch is moved into this Standby mode.

❐ The program counter is reset upon waking up from Standby

mode.

❐ All outputs are tri-stated (except UVALID), and I/O is placed

in input only configuration. Values of I/Os in Standby mode

are listed in the Table 2 on page 7.

■ Since AVDDQ and as a result, XVDDQ, are OFF in the Core

Power Down mode, the clock input at XTALIN must be brought

to a steady LOW level before entry into Core Power Down

mode.

■ NAND functionality is not available. SNVDDQ does not exist

as a separate power domain. It is internally combined with

SSVDDQ.

❐ Core power supply is retained.

❐ Hard reset is performed by asserting the RESET# input, and

Antioch performs initialization.

■ The P-port CLK ball and the P-port synchronous mode

operation are not available. The P-port is operated only in

asynchronous mode.

❐ PLL is disabled.

Core Power Down Mode

The core power supply V_DDis powered down in this mode.

AVDDQ is tied to the same supply as V_DDand as a result, is also

powered down. The endpoint buffers, configuration registers,

and the program RAM do not maintain state. It is necessary to

reload the firmware upon exiting from this mode. It is required

that all VDDQ power supplies (except AVDDQ) are on and not

powered down in this mode. VDD33 must remain ON and the

■ GVDDQ is not a separate power domain in the WLCSP

package. It is internally combined with PVDDQ.

■ Availability of specific signals on the WLCSP option is detailed

in Table 2 on page 7.

Document Number: 001-07978 Rev. *O

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The Ball Assignment table for CYWB0124AB, CYWB0125AB follows.

Table 2. Ball Assignment ^{[2, 3, 4]}

Reset^[5]

VFBGA WLCSP

Ball Name

I/O

I

Ball Description

Clock for P-port

Standby

Power Domain

J2

G1

H3

H2

H1

J3

N/A

G8

J6

CLK

–

Z

–

Z

CE#

I

Chip Select for P-port. Active LOW

Bit 7 of Address Bus for P-port

Bit 6 of Address Bus for P-port

Bit 5 of Address Bus for P-port

Bit 4 of Address Bus for P-port

Bit 3 of Address Bus for P-port

Bit 2 of Address Bus for P-port

Bit 1 of Address Bus for P-port

Bit 0 of Address Bus for P-port

Bit 15 of Data Bus for P-port

Bit 14 of Data Bus for P-port

Bit 13 of Data Bus for P-port

Bit 12 of Data Bus for P-port

Bit 11 of Data Bus for P-port

Bit 10 of Data Bus for P-port

Bit 9 of Data Bus for P-port

Bit 8 of Data Bus for P-port

Bit 7 of Data Bus for P-port

Bit 6 of Data Bus for P-port

Bit 5 of Data Bus for P-port

Bit 4 of Data Bus for P-port

Bit 3 of Data Bus for P-port

Bit 2 of Data Bus for P-port

Bit 1 of Data Bus for P-port

Bit 0 of Data Bus for P-port

A[7]

I

J7

A[6]

I

J8

A[5]

I

H6

H7

J9

A[4]

I

J1

A[3]

I

K3

K2

K1

G2

G3

F1

F2

F3

E1

E2

E3

D1

D2

D3

C1

C2

C3

B1

B2

A1

A[2]

I

H8

H9

G9

G7

F8

F9

F7

E9

E8

E7

D9

D8

D7

C9

C8

C7

B9

B8

A9

A[1]

I

A[0]

I

DQ[15]

DQ[14]

DQ[13]

DQ[12]

DQ[11]

DQ[10]

DQ[9]

DQ[8]

DQ[7]

DQ[6]

DQ[5]

DQ[4]

DQ[3]

DQ[2]

DQ[1]

DQ[0]

ADV#

I/O

I

Z

PVDDQ

VGND

P Port

Z

–

Address Valid for P-port. Valid during

asynchronous mode. ADV# deassertion

causes to latch the address.

B3

A2

A3

A4

A8

B7

A7

C6

OE#

I

Output Enable. Controls the data bus output

drive. Ignored during write cycle. Active LOW.

–

Z

–

Z

WE#

INT#

DRQ#

I

Write Enable. Signals a read (HIGH) or write

(LOW) access cycle.

O

Interrupt Request. Assertion indicates that an

interrupt event has occurred. Active LOW.

DMA Request. Assertion indicates to

Processor that it is ready to read or write one

or more endpoints. It reflects register

CY_AN_MEM_P0_DRQ EPnDRQ assertions.

Active LOW or HIGH (programmable).

B4

C5

DACK#

I

DMA Acknowledgement. Assertion indicates

DMA acknowledgement from processor. Is

configured in ACK mode (asserted throughout

DMA transfer) or EOB mode (pulsed at end of

DMA transfer). Active LOW or HIGH

(programmable).

–

Notes

2. Unused inputs: Must be connected to HIGH/V or LOW/GND (negligible difference in current drawn) logic level, through a single 10 K pull-up resistor. The only

DD

exceptions are WAKEUP, NANDCFG and CLK. WAKEUP is tied HIGH for normal operation and NANDCFG is tied LOW for unused NAND with SD or tied HIGH for

16-bit NAND with no SD. CLK is tied LOW for asynchronous P-port operation.

3. Unused I/Os: For lowest leakage, unused I/Os must be connected to a HIGH logic level. It is recommended that connection to the power supply is through a single

10k ohm pull-up resistor for all unused I/Os.

4. No Antioch balls have internal pull-up or pull-down resistors. Input/output balls may require external pull-up or pull-down resistors depending on the application. The

pull-up resistors used to indicate speed capability on the USB are included in Antioch and need not be connected externally.

5. The Reset column indicates the state of signals during reset (RESET# asserted). The Standby column indicates signal state during Standby (low power operating

mode through WAKEUP deassertion) or core V deactivation.

DD

Document Number: 001-07978 Rev. *O

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Table 2. Ball Assignment ^{[2, 3, 4]}(continued)

Reset^[5]

VFBGA WLCSP

Ball Name

I/O

Ball Description

Standby

Power Domain

SD and

8-bit NAND

Configuration Configuration

16-bit NAND

G9

G10

F9

H2

H1

G3

G2

F2

E3

E2

E1

G1

SD_D[7]

SD_D[6]

SD_D[5]

SD_D[4]

SD_D[3]

SD_D[2]

SD_D[1]

SD_D[0]

SD_CLK

NAND_IO[15]

NAND_IO[14]

NAND_IO[13]

NAND_IO[12]

NAND_IO[11]

NAND_IO[10]

NAND_IO[9]

NAND_IO[8]

N/A

I/O

O

Serve as SD_D[7] for SD port or NAND_IO[15] for

NAND Upper I/O port depending on NANDCFG

selection. NAND configuration is not available in

WLCSP.

Z

Serve as SD_D[6] for SD port or NAND_IO[14] for

NAND Upper I/O port depending on NANDCFG

selection. NAND configuration is not available in

WLCSP.

Serve as SD_D[5] for SD port or NAND_IO[13] for

NAND Upper I/O port depending on NANDCFG

selection. NAND configuration is not available in

WLCSP.

F10

E9

Serve as SD_D[4] for SD port or NAND_IO[12] for

NAND Upper I/O port depending on NANDCFG

selection. NAND configuration is not available in

WLCSP.

Serve as SD_D[3] for SD port or NAND_IO[11] for

NAND Upper I/O port depending on NANDCFG

selection. NAND configuration is not available in

WLCSP.

E10

D9

Serve as SD_D[2] for SD port or NAND_IO[10] for

NAND Upper I/O port depending on NANDCFG

selection. NAND configuration is not available in

WLCSP.

Z

SSVDDQ

VGND

Serve as SD_D[1] for SD port or NAND_IO[9] for

NAND Upper I/O port depending on NANDCFG

selection. NAND configuration is not available in

WLCSP.

Z

D10

F8

Serve as SD_D[0] for SD port or NAND_IO[8] for

NAND Upper I/O port depending on NANDCFG

selection. NAND configuration is not available in

WLCSP.

Z

S Port

Clock output for the SD interface. Frequency is

changed and clock is disabled through firmware

control.

G8

H8

H3

G4

SD_CMD

SD_POW

N/A

I/O

O

SD Command/Response Ball.

Z

SD Power Control. This GPIO is used to control

SD/MMC card power FET if present. HIGH indicates

on, LOW indicates off.

H10

D1

SD_WP

N/A

I

SD Write Protection Detection. Connected to GPIO for

firmware detection. HIGH indicates that the device

connected to the SD port has write protect enabled.

–

Z

–

Z

K7

K8

J8

N/A

NAND_IO[7] NAND_IO[7]

NAND_IO[6] NAND_IO[6]

NAND_IO[5] NAND_IO[5]

NAND_IO[4] NAND_IO[4]

NAND_IO[3] NAND_IO[3]

NAND_IO[2] NAND_IO[2]

NAND_IO[1] NAND_IO[1]

NAND_IO[0] NAND_IO[0]

NAND_CLE NAND_CLE

I/O

O

NAND_IO[7] for NAND Upper I/O port

NAND_IO[6] for NAND Upper I/O port

NAND_IO[5] for NAND Upper I/O port

NAND_IO[4] for NAND Upper I/O port

NAND_IO[3] for NAND Upper I/O port

NAND_IO[2] for NAND Upper I/O port

NAND_IO[1] for NAND Upper I/O port

NAND_IO[0] for NAND Upper I/O port

K9

J9

H9

K10

J10

K6

[6]

Z

SNVDDQ

VGND

NAND Command Latch Enable

[6]

J6

J5

N/A

NAND_ALE NAND_ALE

NAND_CE# NAND_CE#

O

NAND Address Latch Enable

Z

[6]

NAND Chip Enable. Active LOW.

K4

H6

J7

N/A

NAND_RE# NAND_RE#

NAND_WE# NAND_WE#

NAND_WP# NAND_WP#

O

NAND Read Enable. Active LOW.

NAND Write Enable. Active LOW.

Z

[6]

NAND Write Protect. Active LOW.

J4

N/A

NAND_R/B# NAND_R/B#

I

NAND Ready/Busy. NAND output is Open Drain.

Active LOW.

-

K5

N/A

NAND_CE2# NAND_CE2#

O

NAND Chip Enable 2. Allows to access the second

Z

[6]

NAND device. Active LOW.

Note

6. The NAND_CE#, NAND_CE2#,NAND_WP#, NAND_CLE, and NAND_ALE pins are used as General Purpose Outputs if NAND functionality is not used.

Document Number: 001-07978 Rev. *O

Page 8 of 31

CYWB0124AB

CYWB0125AB

Table 2. Ball Assignment ^{[2, 3, 4]}(continued)

Reset^[5]

VFBGA WLCSP

Ball Name

I/O

Ball Description

Standby

Power Domain

A5

A6

A7

A4

A5

B4

D+

I/O/Z USB D+

I/O/Z USB D–

Z

UVDDQ

UVSSQ

D–

Z

U-port

UVALID

O

External USB Switch Control. Reflects value of

register CY_AN_MEM_PMU_UPDATE.UVALID.

Low

A8

B8

A2

N/A

C2

XTALIN

I

Input for either crystal or clock signal. XVDDQ is 3.3

V for crystal input; XVDDQ is 1.8 V for clock input.

–

Z

–

Z

XVDDQ

VGND

[7]

O

I

Output to connect to feedback input of crystal. Is left

floating when external clock at XTALIN.

XTALOUT

C10

B10

RESET#

Reset. Asserted to place Antioch into reset mode and

subsequent initialization. Active LOW.

–

Z

–

N/A

RESETOUT

O

Reset Out. Deasserted LOW when RESET# is

asserted LOW. Asserted HIGH after RESET# is

deasserted and initialization is complete. Reflects

value of RSTCMPT bit.

Low

Others

C9

D8

D3

D2

GPIO[1]

GPIO[0]

I/O

General purpose input/output.

Z

General purpose input/output.GPIO[0] is used for SD

Card Detect with firmware detection. LOW indicates

card is inserted.

[8]

C7

C5

C1

C3

I

Wake Up Signal. 1 = normal operation, 0 = low power

“sleep” mode. Is asserted for Antioch to initialize.

–

WAKEUP

XTALSLC[1]

XTALSLC[0]

NANDCFG

Clock Select. For CYWB0124AB, XTALSLC[1:0] is

decoded as: 00 = 19.2 MHz, 01 = 24 MHz, 10 = 48

MHz, 11 = 26 MHz.

GVDDQ

VGND

C4

C6

C4

i

Clock Select. For CYWB0124AB, XTALSLC[1:0] is

decoded as: 00 = 19.2 MHz, 01 = 24 MHz, 10 = 48

MHz, 11 = 26 MHz.

–

N/A

I

S-port Configuration. ‘0’ selects 8-bit NAND and

SD/MMC configuration. ‘1’ selects 16-bit NAND

configuration.

Config

E8

C8

D7

B1

D4

A1

TEST[2]

TEST[1]

TEST[0]

I

Test mode selection. Is tied to VGND for normal

operation (CMOS level inputs).

–

Test mode selection. Is tied to VGND for normal

operation (CMOS level inputs).

Test mode selection. Is tied to VGND for normal

operation (CMOS level inputs).

D4, H4

H5

E5, A6 PVDDQ

Power Power for P-port I/O. 1.8 V, 2.5 V, or 3.3 V nominal.

–

N/A

SNVDDQ

Power Power for NAND port I/O. 1.8 V, 2.5 V, or 3.3 V

nominal.

B5

H7

B5

UVDDQ

Power Power for USB I/O. 3.3 V nominal.

–

F1, F3, SSVDDQ

F4, G5,

Power Power for SD port, is connected to SNVDDQ if using

16-bit NAND. 1.8 V, 2.5 V, or 3.3 V nominal.

H4, H5,

J2, J3,

J4, J5

D6

B9

B7

N/A

B3

GVDDQ

AVDDQ

XVDDQ

Power Power for miscellaneous I/O. 1.8 V, 2.5 V, or 3.3 V

nominal.

–

Power Power for internal PLL and USB serializer. 1.8 V

nominal.

Power

N/A

Power Power for crystal or clock I/O. 1.8 V (clock) or 3.3 V

(crystal) nominal.

D5, G4,

G5, G6,

G7, F7

D6, F6,

G6, J1

V

Power Power for core. 1.8 V nominal.

DD

[9]

A10

B6

N/A

A3

Power Power sequence control supply. 3.3 V nominal.

Power Ground for all USB.

–

VDD33

UVSSQ

A9

B2

AVSSQ

Power Ground for PLL.

E4, E5,

E6, E7,

F4, F5,

F6

B6, D5, VGND

E4, E6,

F5

Power Ground for core.

Notes

7. XTALOUT is driven HIGH during Standby mode. XTALOUT operates the same during RESET# assertion and Normal mode: fixed HIGH when XVDDQ is 1.8 V (ext

clock) and actively toggles when XVDDQ is 3.3 V (crystal).

8. When RESET# is asserted, the device enters reset state and WAKEUP is ignored.

9. VDD33: In CYWB0124AB, the Ball is no-connect internally. It handles power sequence control in future West Bridge products. When migrating to Astoria, it is connected

to the highest supply to the device. If USB is used, for example, then VDD33 is connected to nominal 3.3 V (because 3.3 V is required for USB). VDD33 is always

supplied in Astoria.

Document Number: 001-07978 Rev. *O

Page 9 of 31

CYWB0124AB

CYWB0125AB

Figure 3. CYWB0124AB 100-ball VFBGA – Top View

Top View

1

2

3

4

5

6

7

8

9

10

A

B

C

D

E

F

ADV#

WE#

INT#

DRQ#

D+

D-

UVALID

XTALIN

AVSSQ

VDD33

RESETOUT

RESET#

SD_D[0]

SD_D[2]

SD_D[4]

SD_D[6]

SD_WP

A

B

C

D

E

F

DQ[1]

DQ[4]

DQ[7]

DQ[10]

DQ[13]

CE#

DQ[0]

DQ[3]

DQ[6]

DQ[9]

DQ[12]

DQ[15]

A[6]

OE#

DQ[2]

DQ[5]

DQ[8]

DQ[11]

DQ[14]

A[7]

DACK#

UVDDQ

UVSSQ

NANDCFG

GVDDQ

VGND

XVDDQ

WAKEUP

TEST[0]

VGND

XTALOUT

TEST[1]

GPIO[0]

AVDDQ

GPIO[1]

XTALSLC[0] XTALSLC[1]

PVDDQ

VGND

VDD

VGND

VDD

SD_D[1]

SD_D[3]

SD_D[5]

SD_D[7]

NAND_IO[2]

TEST[2]

SD_CLK

SD_CMD

SD_POW

VGND

VDD

G

H

J

VDD

G

H

J

A[5]

PVDDQ

SNVDDQ

NAND_WE#

NAND_ALE

SSVDDQ

A[3]

CLK

A[4]

NAND_R/B# NAND_CE#

NAND_WP# NAND_IO[5] NAND_IO[3] NAND_IO[0]

NAND_IO[7] NAND_IO[6] NAND_IO[4] NAND_IO[1]

K

A[0]

1

A[1]

2

A[2]

3

NAND_RE# NAND_CE2# NAND_CLE

K

4

5

6

7

8

9

10

POWER DOMAIN KEY

UVDDQ

GVDDQ

SSVDDQ

VGND

PVDDQ

SNVDDQ

Document Number: 001-07978 Rev. *O

Page 10 of 31

CYWB0124AB

CYWB0125AB

Figure 4. CYWB0124AB 81-ball WLCSP – Top View

2

3

4

5

6

7

8

9

1

TEST[0]

XTALIN

UVSSQ

D+

D-

PVDDQ

INT#

OE#

ADV#

A

B

C

D

E

F

A

TEST[2]

WAKEUP

SD_WP

SD_D[0]

SSVDDQ

SD_CLK

SD_D[6]

AVSSQ

RESET#

GPIO[0]

SD_D[1]

SD_D[3]

SD_D[4]

SD_D[7]

AVDDQ

UVALID

UVDDQ

DACK#

VGND

DRQ#

VDD

WE#

DQ[2]

DQ[5]

DQ[8]

DQ[11]

DQ[14]

A[3]

DQ[0]

DQ[3]

DQ[6]

DQ[9]

DQ[13]

CE#

DQ[1]

B

XTALSLC[1] XTALSLC[0]

DQ[4]

C

GPIO[1]

SD_D[2]

SSVDDQ

SD_D[5]

SD_CMD

TEST[1]

VGND

DQ[7]

D

PVDDQ

VGND

VDD

DQ[10]

E

SSVDDQ

SD_POW

SSVDDQ

DQ[12]

F

SSVDDQ

VDD

DQ[15]

G

H

J

G

A[4]

A[1]

A[0]

H

VDD

SSVDDQ

A[7]

A[6]

A[5]

A[2]

J

1

2

3

4

5

6

7

8

9

POWER DOMAIN KEY

UVDDQ

AVDDQ, VDD

SSVDDQ

VGND

PVDDQ

Document Number: 001-07978 Rev. *O

Page 11 of 31

CYWB0124AB

CYWB0125AB

Static discharge voltage (ESD)

from JESD22-A114 .................................................> 2000 V

Absolute Maximum Ratings

Operating range specifies temperature and voltage boundary

conditions for safe operation of the device. Operation outside

these boundaries may affect the performance and life of the

device. These user guidelines are not tested.

Latch-up current ....................................................> 200 mA

Maximum output short circuit current

for all I/O configurations. (V_OUT= 0 V)^[10].............. –100 mA

Storage temperature ................................ –65 °C to +150 °C

Operating Conditions

Ambient temperature

with power supplied (Industrial) ................. –40 °C to +85 °C

T_A(Ambient temperature under bias)

Industrial .................................................... –40 °C to +85 °C

Supply voltage to ground potential

V_DD, AVDDQ ................................................–0.5 V to +2.0 V

V_DD, AV_DDQsupply voltage .............................1.7 V to 1.9 V

UV_DDQsupply voltage .....................................3.0 V to 3.6 V

GVDDQ, PVDDQ, SSVDDQ, SNVDDQ,

UVDDQ and VDD33 and XVDDQ ...............–0.5 V to +4.0 V

PV_DDQ, GV_DDQ, SNV_DDQ, SSV_DDQ

supply voltage ..................................................1.7 V to 3.6 V

DC input voltage to any input ball ..................1.89 V to 3.6 V

XVDDQ (Crystal I/O) supply voltage ...............3.0 V to 3.6 V

XVDDQ (Ext. clock I/O) supply voltage ...........1.7 V to 1.9 V

(Depends on I/O supply voltage. Inputs are not over voltage

tolerant.)

DC voltage applied to outputs

in High Z State .................................. –0.5 V to VDDQ+0.5 V

DC Characteristics

Table 3. DC Specifications for All Voltage Supplies

Parameter

V_DD

Description

Core voltage supply

Analog voltage supply

Crystal voltage supply

Clock voltage supply

Processor interface I/O

Conditions

Min

1.7

3.0

1.7

Typ

1.8

Max

1.9

3.6

1.9

3.6

Unit

V

AVDDQ

XVDDQ

PVDDQ^[11]

GVDDQ^[11]

SNVDDQ^[11]

SSVDDQ^{[11, 12]}

UVDDQ^[13]

VDD33

1.8

V

3.3

V

1.8

V

1.8, 2.5, 3.3

V

Miscellaneous I/O voltage supply

S-port NAND I/O voltage supply

S-port SD I/O voltage supply

USB voltage supply

1.7

1.8, 2.5, 3.3

3.6

V

1.8, 2.5, 3.3

1.7

1.8, 2.5, 3.3

3.6

3.0

3.3

–

3.6

Power sequence control supply

Input HIGH voltage 1

3.0

3.6

[14]

All ports except USB,

2.0 V  V_CC 3.6 V

0.625 × V_CC

V_CC+ 0.3

V_IH1

[14]

Input HIGH voltage 2

All ports except USB,

1.7 V  V_CC< 2.0 V

V_CC– 0.4

–

V_CC+ 0.3

V_IH2

V_IL

Input LOW voltage

–0.3

–

0.25 × V_CC

V

V_OH

V_OL

I_IX

Output HIGH voltage

Output LOW voltage

Input leakage current

Output leakage current

I_OH(MAX) = –0.1 mA

0.9 × V_CC

–

I_OL(MIN) = 0.1 mA

–

–1

–

0.1 × V_CC

V

All I/O signals held at VDDQ

1

A

mA

I_OZ

1

I_CCCore

Operating current of core voltage Outputs tri-stated

supply (V_DD) and analog voltage

supply (AVDDQ)

VFBGA

WLCSP

110

115

–

Notes

10. Do not test more than one output at a time. Duration of the short circuit does not exceed 1 second. Tested initially, and after any redesign or process changes, may

affect these parameters.

11. Interfaces with a voltage range are adjustable with respect to the I/O voltage and thus support multiple I/O voltages.

12. The SSVDDQ I/O voltage is dynamically changed (for example, from high range to low range) as long as the supply voltage undershoot does not surpass the lower

minimum voltage limit. SSVDDQ levels for SD modes: 2.0 V–3.6 V, MMC modes: 1.7 V–3.6 V.

13. When U-port is in a disabled state, UVDDQ goes down to 2.4 V, provided UVDDQ is still the highest supply voltage level.

14. V = pertinent V

value.

CC

DDQ

Document Number: 001-07978 Rev. *O

Page 12 of 31

CYWB0124AB

CYWB0125AB

Table 3. DC Specifications for All Voltage Supplies (continued)

Parameter

Description

Conditions

XTALOUT floating

Min

–

Typ

–

Max

5

Unit

I_CCCrystal

Operating current of crystal

voltage supply (XVDDQ)^[15]

VFBGA

WLCSP

mA

–

N/A

25

I_CCUSB

I_SB1

Operating current of USB voltage Operating and terminated for high

supply (UVDDQ)^[15]

speed mode

–

mA

250^[17]

Total standby current of Antioch 1. *VDDQ = 3.3 V Nominal

when device is in suspend mode

–

2500

A

(3.0–3.6 V)

2. Outputs and Bidirs High or

Floating^[16]

3. XTALOUT Floating

4. D+ Floating (no current drawn

through internal 1.5 kohm

pull-up),

D– Grounded, UVALID Driven

LOW

5. Device in Suspend Mode

I_SB2

Total standby current of Antioch 1. *VDDQ = 3.3 V

25 °C

–

45

A

when device is in standby mode

Nominal (3.0–3.6 V)

2. Outputs and Bidirs

High or Floating^[16]

3. XTALOUT Floating

4. D+ Floating, D–

Grounded, UVALID

Driven LOW

85 °C

290

I_SB3

Total standby current of Antioch 1. Outputs and Bidirs

25 °C

85 °C

–

25

when device is in core power

down mode

High or Floating^[16]

2. XTALOUT Floating

3. D+ Floating, D–

Grounded, UVALID

Driven LOW

139

4. Core Powered Down

Notes

15. Active Current Conditions:

-UVDDQ: USB transmitting 50% of the time, receiving 50% of the time.

-PVDDQ/SNVDDQ/SSVDDQ/GVDDQ: Active Current Depends on I/O activity, bus load, and supply level.

-XVDDQ: Assume highest frequency clock (48 MHz) or crystal (26 MHz).

16. The Outputs/Bidirs that are forced low in Standby mode increases I/O supply standby current beyond specified value.

17. Isb1 typical value is not a maximum specification but a typical value. Isb1 maximum current value specified for 85 °C.

Document Number: 001-07978 Rev. *O

Page 13 of 31

CYWB0124AB

CYWB0125AB

USB Transceiver

USB 2.0 compliant in full speed and high speed modes.

Capacitance

Parameter

C_IN

Description

Conditions

Typ

Max

Unit

Input ball capacitance,

Except D+/D–

T_A= 25 °C, f = 1 MHz, V_CC= V_CCIO

–

9

pF

Input ball capacitance, D+/D–

Output ball capacitance

–

15

10

C_OUT

pF

AC Test Loads and Waveforms

Figure 5. AC Test Loads and Waveforms

Document Number: 001-07978 Rev. *O

Page 14 of 31

CYWB0124AB

CYWB0125AB

AC Characteristics

USB Transceiver

USB 2.0 compliant in full speed and high speed modes.

P-Port Interface

Asynchronous Mode Timing Parameters

Table 4. Asynchronous Mode Timing Parameters

Parameter

Description

Min

Max

Unit

Read Timing Parameters

tAA

Address to data valid

–

3

–

5

30

–

ns

tOH

Data output hold from address change

Chip enable to data valid

tEA

30

–

tAADV

tAVS

tAVH

ADV# to data valid access time

Address valid to ADV# HIGH

ADV# HIGH to address hold

2^[18]

5

–

tCVS

tVPH

CE# low setup time to ADV# HIGH

ADV# HIGH time

–

ns

15^[19]

tVP

ADV# pulse width LOW

OE# LOW to data valid

OE# LOW to Low Z

OE# HIGH to High Z

CE# LOW to Low Z

CE# HIGH to High Z

7.5

–

22.5

–

ns

tOE

tOLZ

tOHZ

tLZ

3

0

22.5

–

3

tHZ

–

22.5

Write Timing Parameters

tCW

CE# LOW to write end

30

0

–

ns

tAW

Address valid to write end

Address setup to write start

ADV# setup to write start

WE# pulse width

tAS

tADVS

tWP

0

22

10

5

tWPH

tCPH

tAVS

tAVH

WE# HIGH time

CE# HIGH time

Address valid to ADV# HIGH

ADV# HIGH to address hold

2^[18]

5

tCVS

tVPH

CE# LOW setup time to ADV# HIGH

ADV# HIGH time

–

ns

15^[19]

7.5

30

18

0

tVP

ADV# pulse width LOW

–

ns

tVS

ADV# LOW to end of write

Data setup to write end

tDW

tDH

–

Data hold from write end

WE# low to DQ High Z output

WE# high to DQ Low Z output

–

tWHZ

tWLZ

–

22.5

–

3

Notes

18. In applications where back-to-back accesses are not performed on different endpoint addresses, the minimum t

specification is relaxed to 0 ns.

AVH

19. In applications where access cycle time is at least 60 ns, t

is relaxed to 12 ns.

VPH

Document Number: 001-07978 Rev. *O

Page 15 of 31

CYWB0124AB

CYWB0125AB

Figure 6. Asynchronous Single Read Timing

Valid Address

tAA

A

tVPH

tAVS

tAVH

ADV#

CE#

tHZ

tVP

tAADV

tEA

tOE

OE#

tOHZ

WE#

DQ

tOLZ

High-Z

Valid Output

tLZ

Figure 7. Asynchronous Back-to-Back Read Timing

Valid Address

tAA

Valid Address

tOH

A

tVPH

tAVS

tAVH

ADV#

CE#

tHZ

tVP

tAADV

tEA

OE#

tOHZ

WE#

DQ

High-Z

Valid Output

tLZ

Document Number: 001-07978 Rev. *O

Page 16 of 31

CYWB0124AB

CYWB0125AB

Figure 8. Asynchronous Back-to-Back Write Timing

Valid Address

A

tAVS

tVP

tAVH

tVPH

ADV#

CE#

tVS

tCW

OE#

WE#

tAW

tWPH

tWP

tOW

tAS

tADVS

tDH

tDW

High-Z

Valid Input

DQ_IN

tWHZ

tLZ

DQ_OUT

Figure 9. Asynchronous Read to Write Timing

A

Valid Address

tAA

tAVS

tAVH

ADV#

tVPH

tAVS

tAVH

tVP

tVS

tAADV

CE#

tEA

tOE

OE#

WE#

tOHZ

tAW

tWP

tOW

tDH

tDW

tAS

High-Z

Valid Input

DQ_IN

tOLZ

tWHZ

High-Z

DQ_OUT

Valid Output

tLZ

Document Number: 001-07978 Rev. *O

Page 17 of 31

CYWB0124AB

CYWB0125AB

Figure 10. Asynchronous Write to Read Timing

Valid Address

tAVS

tVP

Valid Address

A

tAA

tAVH

tAVS

tAVH

ADV#

CE#

tVP

tVS

tAADV

tOE

OE#

WE#

tAW

tWP

tDH

tDW

tAS

Valid Input

DQ_IN

tOLZ

tWHZ

DQ_OUT

Valid Output

Synchronous Mode Timing Parameters

Table 5. Synchronous Mode Timing Parameters

Parameter

FREQ

Description

Interface Clock Frequency

Clock Period

Conditions

Min

–

Max

33

–

Unit

MHz

ns

tCLK

tCLKH

tCLKL

tS

30

12

7.5

1.5

–

Clock HIGH Time

–

ns

Clock LOW Time

–

ns

CE#/WE#/ADDR/DQ Setup Time

CE#/WE#/ADDR/DQ Hold Time

Clock to Valid Data

–

ns

tH

–

ns

tCO

18

–

ns

tOH

Clock to Data Hold Time

OE# HIGH to Data High Z

OE# LOW to Data Low Z

OE# LOW to Data Valid

WE# Low to DQ High Z Output

WE# High to DQ Low Z Output

2

ns

tHZ

–

22.5

–

ns

tLZ

3

ns

tOE

–

22.5

–

ns

tWHZ

tWLZ

tCKHZ

–

ns

3

ns

Clock to Data High Z (Figure 14 on page 20) Measured from the rising edge of the

–

18

ns

second clock after the deassertion of

CE#islatchedbytherisingedgeofthe

clock.

tCKLZ

Clock to Data Low Z (Figure 16 on page 21)

3

–

ns

Document Number: 001-07978 Rev. *O

Page 18 of 31

CYWB0124AB

CYWB0125AB

Figure 11. Synchronous Write Timing

tCLKH

tCLKL

tCLK

CLK

CE#

tH

tS

A[7:0]

An+1

An+2

An

An+3

WE#

OE#

DQ[15:0]

(input)

Dn+1

Dn+2

Dn

Dn+3

DQ[15:0] High-Z

(output)

Note:

- Assumes previous cycle had CE# deselected

- OE# is don’t care during write operations

Figure 12. Synchronous Read Timing

tCLKH

tCLKL

tCLK

CLK

CE#

tH

tS

A[7:0]

An+1

An+2

An+4

An

An+3

WE#

OE#

High-Z

DQ[15:0]

(input)

tLZ

tHZ

tOH

Dn

tCO

DQ[15:0]

(output)

Dn+1

tOE

Note:

- Assumes previous cycle had CE# deselected

Document Number: 001-07978 Rev. *O

Page 19 of 31

CYWB0124AB

CYWB0125AB

Figure 13. Synchronous Read (OE# Fixed LOW) Timing

CLK

CE#

tH

tS

A[7:0]

Ax+1

Ax+2

Ax

WE#

OE#

tCKHZ

Dx+1

tOH

Dx-1

tCO

DQ[15:0]

(output)

Dx-2

Dx

Note:

- Assumes previous several cycles were Read

Figure 14. Synchronous Read to Write (OE# Controlled) Timing

tCLKH

tCLKL

tCLK

CLK

CE#

tH

tS

A[7:0]

Ax+1

An

Ax

An+1

Dn+1

An+2

WE#

OE#

tH

tS

Dn

High-Z

DQ[15:0]

(input)

Dn+2

tOH

Dx-1

tCO

tHZ

DQ[15:0]

(output)

Dx-2

Dx

Note:

- Assumes previous several cycles were Read

- (Ax) and (Ax+1) cycles are turnaround. (Ax+1) operation does not cross pipeline.

Document Number: 001-07978 Rev. *O

Page 20 of 31

CYWB0124AB

CYWB0125AB

Figure 15. Synchronous Read to Write (OE# Fixed LOW) Timing

tCLKH

tCLKL

tCLK

CLK

CE#

tH

tS

A[7:0]

Ax+1

Ax+2

Ax

An

An+1

Dn+1

WE#

OE#

tWHZ

tH

tS

High-Z

Dn

DQ[15:0]

(input)

tCO

tOH

Dx-1

DQ[15:0]

(output)

Dx

Dx-2

tCO

Note:

- Assumes previous several cycles were Read

- In this scenario, OE# is held LOW

- (Ax) and (Ax+1) cycles are turnaround. (Ax+1) operation does not cross pipeline.

- No operation is performed during the Ax+2 cycle (true turnaround operation)

Figure 16. Synchronous Write to Read Timing

tCLKH

tCLKL

tCLK

CLK

tH

tS

CE#

A[7:0]

An+1

Dn+1

An+2

An+4

An

Dn

An+3

WE#

OE#

tWLZ

tS

DQ[15:0]

(input)

tOH

tCO

High-Z

DQ[15:0]

(output)

Dn+2

tCKLZ

Note:

- Assumes previous cycle has CE# deselected

- In this scenario, OE# is held LOW

Document Number: 001-07978 Rev. *O

Page 21 of 31

CYWB0124AB

CYWB0125AB

SD/MMC Parameters

Figure 17. SD/MMC Timing Waveform - All Modes

tSDCLKH

tSDCLK

SD_CLK

tSDCLKL

tSDOS

tSDOH

tSDCKLZ

tSDCKHZ

SD_CMD/

SD_D0-D3

Output

SD_CMD/

SD_D0-D3

Input

tSDIH

tSDIS

Table 6. Common Timing Parameters for SD and MMC – During Identification Mode

Parameter

SDFREQ

tSDCLK

Description

SD_CLK interface clock frequency

Clock period

Min

–

Max

400

–

Unit

kHz

s

2.5

1.0

tSDCLKH

tSDCLKL

Clock high time

–

s

Clock low time

–

s

Table 7. Common Timing Parameters for SD and MMC – During Data Transfer Mode

Parameter

SDFREQ

tSDCLK

Description

SD_CLK interface clock frequency

Clock period

Min

5

Max

48

200

60

3

Unit

MHz

ns

20.8

40

–

tSDCLKOD

tSCLKR

Clock duty cycle

%

Clock rise time

ns

tSCLKF

Clock fall time

–

3

ns

Table 8. Timing Parameters for SD – All Modes

Parameter Description

tSDIS Input setup time

Min

4

Max

–

Unit

ns

tSDIH

Input hold time

2.5

7

–

ns

tSDOS

Output setup time

Output hold time

Clock to data high Z

Clock to data low Z

–

ns

tSDOH

6

–

ns

tSDCKHZ

tSDCKLZ

–

18

–

ns

3

ns

Table 9. Timing Parameters for MMC – All Modes

Parameter Description

tSDIS Input setup time

Min

4

Max

–

Unit

ns

tSDIH

Input hold time

4

–

ns

tSDOS

Output setup time

Output hold time

Clock to data High Z

Clock to data Low Z

6

–

ns

tSDOH

6

–

ns

tSDCKHZ

tSDCKLZ

–

18

–

ns

3

ns

Document Number: 001-07978 Rev. *O

Page 22 of 31

CYWB0124AB

CYWB0125AB

Reset and Standby Timing Parameters

Figure 18. Reset and Standby Timing Diagram

Core

Power-Down

VDD

(core)

VDDQ

(I/O)

XTALIN up & stable

before WAKEUP

asserted

XTALIN

tWPW

tWU

tWH

Standby

Mode

tRR

WAKEUP

RESET#

Mandatory

Reset Pulse

Mandatory

Reset Pulse

tRH

Hard Reset

Firmware Init

Complete

Firmware Init

Complete

Firmware Init

Complete

High-Z

tRPW

RESETOUT

UVALID

USB Switch

Disabled

USB Switch

Enabled

tSLP

CY_AN_MEM_PMU_UPDATE.UVALID

bit is set to ‘0’

CY_AN_MEM_PMU_UPDATE.UVALID

bit is set to ‘0’

CY_AN_MEM_PMU_UPDATE.UVALID

bit is set to ‘1’

Table 10. Reset and Standby Timing Parameters

Parameter Description

tSLP

Conditions

Min

–

Max

1

Unit

ms

Sleep time

tWU

WAKEUP time from standby mode

Clock on XTALIN

1

–

Crystal on XTALIN-XTALOUT

5

–

tWH

WAKEUP high time

WAKEUP pulse width

RESET# high time

RESET# pulse width

5

–

tWPW

tRH

5

–

5

–

tRPW

Clock on XTALIN

1

–

Crystal on XTALIN-XTALOUT

5

–

tRR

RESET# recovery time

1

–

Document Number: 001-07978 Rev. *O

Page 23 of 31

CYWB0124AB

CYWB0125AB

Ordering Information

Table 11 lists the key package features and ordering codes. The table contains only the parts that are currently available. If you do

not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at

www.cypress.com and refer to the product summary page at http://www.cypress.com/products.

Table 11. Key Features and Ordering Information

Ordering Code

CYWB0124AB-BVXI

CYWB0124ABX-FDXI

CYWB0125ABX-FDXI

Turbo-MTP Enabled

Package Type

Available Clock Input Frequencies (MHz)

19.2, 24, 26, 48

No

100-ball VFBGA – Pb-free

81-ball WLCSP – Pb-free

19.2, 24, 26, 48

Yes

19.2, 24, 26, 48

Ordering Code Definitions

CY WB 012 4, 5 AB X BV, FD X

I

Temperature: Industrial

Pb-free

BV = VFBGA, FD = WLCSP

BGA, CSP

A generation

Turbo MTP is enabled

4 = No, 5 = Yes

Antioch Bridge

Family: West Bridge

Company ID: CY = Cypress

Document Number: 001-07978 Rev. *O

Page 24 of 31

CYWB0124AB

CYWB0125AB

Package Diagrams

Figure 19. 100-ball VFBGA (6 × 6 × 1.0 mm) Package Outline, 51-85209

E1

2X

0.10 C

(datum B)

A1 CORNER

E

B

A

D

10

9

8

7 6 5 4 3 2 1

7

A

A1 CORNER

6

B

C

D

E

F

G

H

SD

D1

(datum A)

J

K

eD

6

2X

0.10 C

eE

SE

TOP VIEW

BOTTOM VIEW

DETAIL A

0.10 C

A

A1

0.08 C

C

100XØb

5

SIDE VIEW

Ø0.15 M C A B

Ø0.05 M C

DETAIL A

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONS

NOM.

SYMBOL

2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

MIN.

MAX.

1.00

-

A

A1

D

-

4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX

SIZE MD X ME.

0.16

6.00 BSC

4.50 BSC

10

E

D1

E1

MD

ME

N

5.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE

PARALLEL TO DATUM C.

6.

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND

DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

10

100

0.30

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW

"SD" OR "SE" = 0.

b

0.25

0.35

eD

eE

SD

SE

0.50 BSC

0.25 BSC

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" = eD/2 AND "SE" = eE/2.

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK

METALIZED MARK, INDENTATION OR OTHER MEANS.

7.

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER

BALLS.

9. JEDEC SPECIFICATION NO. REF. : MO-195C.

51-85209 *F

Document Number: 001-07978 Rev. *O

Page 25 of 31

CYWB0124AB

CYWB0125AB

Figure 20. 81-ball WLCSP (3.8 × 3.8 × 0.55 mm) Package Outline, 001-13820

001-13820 *G

Document Number: 001-07978 Rev. *O

Page 26 of 31

CYWB0124AB

CYWB0125AB

Acronyms

Document Conventions

Table 12. Acronyms Used in this Document

Units of Measure

Acronym

DC

Description

Table 13. Units of Measure

Direct Current

Symbol

Unit of Measure

DMA

ESD

Direct Memory Access

Electrostatic Discharge

Error Correction Codes

Hard Disk Drive

A

ampere

dBc

kHz

MBPs

MHz

µA

decibels relative to the carrier

kilohertz

ECC

megabyte per second

megahertz

HDD

MTP

Media Transfer Protocol

Multimedia Card

microampere

microsecond

millisecond

MMC

PLL

µs

Phase-Locked Loop

ms

SLIM

SLC

Simultaneous Link to Independent Media

Single Level Cell

ns

nanosecond

parts per million

picofarad

ppm

pF

USB

Universal Serial Bus

WLCSP

CE-ATA

Wafer Level Chip Scale Package

V

volt

Consumer Electronics - Advanced Technology

Attachment

mA

milliampere

Document Number: 001-07978 Rev. *O

Page 27 of 31

CYWB0124AB

CYWB0125AB

Document History Page

Document Title: CYWB0124AB/CYWB0125AB, West Bridge^®Antioch™ USB/Mass Storage Peripheral Controller

Document Number: 001-07978

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

460480

539922

ODC

VSO

See ECN New release.

*A

See ECN Removed all CYWB0224AB (this is Astoria P/N)

Removed CYWB0224AB Additional Features

Removed MLC NAND support wordings

Removed CE-ATA specification

Added 26 MHz for the clock support

Removed the paragraph of CYWB0224AB

Removed Note 1

Corrected Note 7 is the same as PDD

Added Astoria as a future product in Note 9

Added reference figures in tCKHZ and tCKLZ

Added condition description to tCKHZ

Added figure 11

Updated figure 14

Removed CYWB0224AB-BVXI, removed the columns of CE-ATA and MLC

NAND Support

*B

*C

567593

841760

VSO

RUY

See ECN Minor Change: Post part CYWB0124AB on external website under NDA.

See ECN Page-1, Changes to the Mass Storage Support with addition of CE-ATA

Updated the Revision numbers of SD Card Specifications

Added CE-ATA Specifications

Clarified footnote 5 that unused inputs are tied through 10k pull up resistors

and that CLK is LOW in asynchronous P-port operation

Footnote 6, 100k resistor is changed to 10k

Footnote 7, a sentence on resistors for speed capability on USB is added

SDIO is changed to SD in Pin Assignment Table

In Clocking, changed crystal requirement from 50 to 100 ppm.

Clarified Core Power Down mode that AVDDQ is also powered down.

Split tAS into tAS and tADVS and tWPH into tWPH and tCPH in Table 5

Updated Figure 5 to depict tOH

Updated Figure 6 to depict tADVS and corrected tCW

Updated Figure 1 to remove “Access Control”

Added external clock requirements and Table 1

Added section on Flexible I/Os

Specified values in Absolute Maximum Ratings (changed from TBS)

In Table 3, updated V_IHvalue for supplies other than UVDDQ, and added

pertinent notes 15 and 16. Appended to note 12 that maximum current values

are measured at 85°C. Added maximum current values for I_{SB1, SB2}and I_SB3

I

In Table 5, the following changes are made: tOH, tOLZ, tLZ, and tOW changed

from 5 to 3 ns; tVP changed from 5 to 7.5 ns; tOE, tOHZ, tHZ, and tWHZ

changed from 20 to 22.5 ns. Added notes [17] and [18]

In Table 6, tHZ and tOE changed form 18 to 22.5 ns.

Document Number: 001-07978 Rev. *O

Page 28 of 31

CYWB0124AB

CYWB0125AB

Document History Page (continued)

Document Title: CYWB0124AB/CYWB0125AB, West Bridge^®Antioch™ USB/Mass Storage Peripheral Controller

Document Number: 001-07978

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*D

1067820

RUY

See ECN Added Table 10

Added “SSVDDQ levels for SD modes: 2.0V - 3.6V, MMC modes:1.7V - 3.6V.”

to note 11 in Table 5

Added notation of tSDCKHZ and tSDCKLZ to Figure 15

Added undershoot and overshoot parameters and removed the Supply Voltage

Noise requirement in Table 1 External Clock Requirements

Added representation of tWHZ to Figure 13 and tWLZ to Figure 14

Added tWHZ and tWLZ to Table 5

Changed name of parameter tOW to tWLZ in Table 6

Added “and less than 4x4 mm WLCSP” to Features

Added Figure 19

Added WLCSP ordering information

Added functionality of Antioch in WLCSP

Added Figure 3

Added two columns to Table 1 showing the Balls are available in the WLCSP

and VFBGA packages

Added “Note that in the WLCSP option, the S-port is not configurable; it only

supports a single SD/MMC+ port with no NAND port.” to Mass Storage Support

section

Added “Availability of specific signals on the WLCSP option is detailed in Pin

Assignments.” to Antioch in WLCSP.

Added “Maximum permitted noise on AVDDQ is 20 mV p-p.” and “Noise

guideline for all supplies except AVDDQ is maximum 100 mV p-p.” to Antioch

Power Domains section

Changed maximum value of Isb3 in Table 3 from 170 uA to 139 uA. Changed

“Typical” values for Isb2 and Isb3 to correct definition of “Maximum” value at

25°C. Isb1 has typical value at 25°C. Removed “These values are based upon

simulation and are subject to change pending closure of full device character-

ization.” from note 10

Added figure 16 and Table 11

Changed reference from “pin” to “Ball” in Table 2 and throughout the data sheet.

Corrected the ball description of SD_WP in Table 2 to say that SD_WP being

HIGH, not LOW indicates that the card is write protected

Added the requirement that XTALIN is LOW before entry into Core Power

Down mode in Core Power Down mode and Antioch in WLCSP sections

Re-ordered paragraphs in Clocking section

Added “The external clock is a square wave that conforms to high and low

voltage levels mentioned in Table 3 and the rise and fall time specifications” in

Figure 17

Clarified Standby mode section to reflect that WAKEUP assertion releases

Antioch from standby mode only when the mode is entered by de-asserting

WAKEUP

*E

*F

1116363

1408263

RUY

See ECN Changed part number for the WLCSP part from CYWB0124AB-FDXI to

CYWB0124ABX-FDXI in Ordering Information table

Updated the information from *B version of specification 001-13820 in the

package diagram of WLCSP

Removed mention of erroneous change in Isb1 parameter in *D version from

Document History Table

AESA

See ECN Changed the DC Characteristics to differentiate between Icc Crystal for Antioch

VFBGA and WLCSP

Added a footnote to NAND_CE#, NAND_CE2#, NAND_WP#, NAND_CLE,

and NAND_ALE pins in the pin assignment table.

Document Number: 001-07978 Rev. *O

Page 29 of 31

CYWB0124AB

CYWB0125AB

Document History Page (continued)

Document Title: CYWB0124AB/CYWB0125AB, West Bridge^®Antioch™ USB/Mass Storage Peripheral Controller

Document Number: 001-07978

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*G

1489983 OSG / AESA See ECN In DC Characteristics Table, changed Icc Crystal and Icc Core to differentiate

between values for VFBGA and WLCSP

In DC Characteristics Table, clarified the ISB1 measurement conditions.

*H

2572476 OSG / AESA 09/25/2008 Updated Phase Noise specifications for input clock - Table 1

Updated ppm specification to 150 ppm for input clock and crystal - Table 1

Added Turbo-MTP Support introduction to Functional Overview

Added Turbo-MTP part numbers to Ordering Information

Added part number CYWB0125AB

Changed data sheet title to “CYWB0124AB/CYWB0125AB West Bridge®

Antioch™ USB/Mass Storage Peripheral Controller”

Updated to new template.

*I

2949425

ODC

10/22/10

Included table of contents.

Added ordering code definitions.

Added Acronym table and units of measure.

Updated package diagrams.

Updated to new template.

*J

3201726

AESA

03/21/11

Removed Pruned part CYWB0125AB-BVXI from ordering information.

Updated Figure 19 on page 25

*K

*L

3553527

3847849

AASI

HBM

03/16/2012 Post to external web.

12/20/2012 Updated Package Diagrams:

spec 001-13820 – Changed revision from *E to *F.

*M

*N

4197479

5566511

HBM

11/20/2013 Updated to new template.

Completing Sunset Review.

12/26/2016 Updated Package Diagrams:

spec 51-85209 – Changed revision from *D to *F.

spec 001-13820 – Changed revision from *F to *G.

Updated to new template.

Completing Sunset Review.

*O

5981602 AESATMP9 12/01/2017 Updated logo and copyright.

Document Number: 001-07978 Rev. *O

Page 30 of 31

CYWB0124AB

CYWB0125AB

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/pmic

cypress.com/touch

cypress.com/usb

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 001-07978 Rev. *O

Revised December 1, 2017

Page 31 of 31

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