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CYZ2509ZC

型号：

CYZ2509ZC

品牌：

CYPRESS[ CYPRESS ]

页数：

6 页

PDF大小：

73 K

下载PDF手册
CYZ2509  
Nine-output Zero Delay Buffer  
• OE pins for separate output enable control  
• 24-pin TSSOP package  
Features  
• Zero delay 9-output buffer with internal loop filter  
• High-frequency operation (150 MHz)  
• Low jitter: < ± 75 pS  
• Low skew < 200 pS  
• Extended temperature range: 0°C to 85°C  
• Spread-Spectrum-compatible  
• Integrated series damping resistors specifically  
designed for registered SDRAM DIMM applications–  
JEDEC JC40-compliant  
• Externally controllable output delay  
• 45–55% output duty cycle  
Description  
The CYZ2509 is a 3.3V zero delay buffer designed to distribute  
high-speed clocks in PC, workstation, datacom, telecom and  
other high-performance applications. It is ideal for use in  
SDRAM memory applications, and conforms to the JEDEC  
JC40 specification supporting SDRAM DIMM applications.  
The CYZ2509 has two banks of outputs with independent  
output enable controls. Input-to-output skew can be adjusted  
by varying load/delay on feedback path.  
Pin Configuration  
Block Diagram  
FBOUT  
1Y0  
VSSA  
VDD  
2Y0  
2Y1  
2Y2  
VSS  
VSS  
2Y3  
2Y4  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
REF  
VDDA  
VDD  
1Y0  
1Y1  
VSS  
1Y1  
1Y2  
1Y3  
OEA  
FBIN  
REF  
PLL  
1
MUX  
0
VSS  
2Y0  
1Y2  
1Y3  
VDD  
OEA  
FBIN  
VDDA  
SEL  
9
2Y1  
2Y2  
2Y3  
2Y4  
VDD  
OEB  
FBOUT  
10  
11  
12  
OEB  
Table 1. Function Table  
INPUT PINS  
OUTPUT PINS  
2Y(0:4)  
LOW  
OEA  
LOW  
LOW  
HIGH  
HIGH  
OEB  
LOW  
HIGH  
LOW  
HIGH  
1Y(0:3)  
LOW  
LOW  
REF  
FBOUT  
REF  
REF  
REF  
LOW  
REF  
REF  
REF  
REF  
Note:  
1. See Table 4 for additional logic configurations. REF is fixed frequency input.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-07391 Rev. **  
Revised June 6, 2002  
CYZ2509  
Pin Description  
Pin  
Name  
REF  
I/O  
I
Description  
24  
12  
13  
Input reference pin.  
Output feedback pin, no OE controls.  
FBOUT  
O
This pin is to be connected to the FBOUT pin. A timing delay may be inserted  
to change the device’s actual skew.  
FBIN  
I
14  
OEA  
OEB  
VDD  
I
I
Output Enable for Bank A clocks (high active). See Block Diagram.  
Output Enable for Bank A (high active). See Block Diagram.  
3.3V supply for core logic, inputs and outputs.  
11  
22, 10, 15, 22  
23  
PWR  
Power for internal analog circuitry. This supply should have separate decou-  
pling. For test purposes, when VDDA’s are strapped to ground the internal  
phase-locked loop (PLL) ( is bypassed and REF is buffered directly to device  
outputs (see Table 4)  
VDDA  
PWR  
21, 20, 17, 16  
3, 4, 5, 8, 9  
6, 7, 18, 19  
1
1Y(0:3)  
2Y(0:4)  
VSS  
O
Low skew clock outputs. Outputs enabled by OEA in high state.  
Low skew clock outputs. Outputs enabled by OEB in high state.  
Ground pins for core logic and I/Os.  
O
PWR  
VSSA  
PWR  
Ground pin for analog circuitry.  
Table 2. Absolute Maximum Ratings[2]  
Parameter  
Description  
Supply Voltage Range  
Input Voltage Range  
Commercial  
–0.5 to +4.6  
Unit  
V
VDD, VDDA  
VI[3]  
–0.5 to VDD + 0.5  
V
VoltageRange AppliedtoAny Outputinthe  
HIGH or LOW State  
[3]  
VO  
–0.5 to VDD + 0.5  
V
I
IK (V I < 0)  
Input Clamp Current  
–50  
mA  
mA  
Terminal Voltage with Respect to VSS  
(inputs VIH2.5, VIL2.5)  
IOK (VO < 0 or VO > VDD  
±50  
IO (VO = 0 to VDD  
VDD or VSS  
TA = 50°C (in still air)[4]  
)
Continuous Output Current  
Continuous Current  
±50  
±100  
mA  
mA  
W
Maximum Power Dissipation  
Storage Temperature Range  
0.7  
TSTG  
–65°C to +150°C  
°C  
Table 3. Capacitance[5]  
Parameter  
Description  
Input Capacitance Vj = VDD or VSS  
Output Capacitance VO = m VDD or VSS  
Load Capacitance  
Min.  
Typ.  
5
Max.  
Unit  
pF  
CIN  
CO  
CL  
6
pF  
30  
pF  
Table 4. Test Mode Table (VDDA = 0V)  
INPUTS  
OUTPUTS  
OEA  
LOW  
LOW  
LOW  
HIGH  
OEB  
LOW  
HIGH  
LOW  
LOW  
HIGH  
REF  
LOW  
HIGH  
HIGH  
HIGH  
HIGH  
1Y(0:3)  
2Y(0:4)  
LOW  
FBOUT  
LOW  
LOW  
LOW  
HIGH  
HIGH  
LOW  
HIGH  
HIGH  
HIGH  
HIGH  
HIGH  
LOW  
LOW  
HIGH  
HIGH  
Notes:  
2. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stresses rating only and functional  
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to  
absolute-maximum-rated conditions for extended periods may affect device reliability.  
3. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
4. The maximum package power dissipation is calculated using a junction temperature or 150°C and board trace length of 750 mils.  
5. Unused inputs must be held high or low to prevent them from floating.  
Document #: 38-07391 Rev. **  
Page 2 of 6  
CYZ2509  
Table 5. DC Parameters (VDD = VDDA = 3.0V to 3.6V, TAMB = 0°C to +85°C)[6]  
Parameter  
VIH  
Description  
HIGH Level Input Voltage  
LOW Level Input Voltage  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
V
2.0  
VIL  
0.8  
V
Min. to Max  
VDD = 3V  
I
OH = –100 mA  
VDD–0.2  
2.1  
VOH  
HIGH Level Output Voltage  
LOW Level Output Voltage  
HIGH Level Output current  
LOW Level Output Current  
IOH = –12 mA  
IOH = –6 mA  
V
V
VDD = 3V  
2.4  
Min. to Max  
VDD = 3V  
I
OL =100 mA  
0.2  
0.8  
VOL  
IOH  
IOL  
IOL = 12 mA  
IOL= 6 mA  
VDD = 3V  
0.55  
VDD = 3.135V  
VO = 1V  
–32  
VDD = 3.3V  
VO = 1.65V  
VO = 3.135V  
VO = 1.95V  
VO = 1.65V  
VO = 0.4V  
–36  
mA  
mA  
V
DD = 3.465V  
DD = 3.135V  
–12  
V
34  
VDD = 3.3V  
VDD = 3.465V  
VDD = 3V  
40  
14  
–1.2  
±5  
VIK  
II  
Clamp Voltage  
IIN = –18 mAV  
VI = VDD or VSS  
V
Input Leakage Current Per Pin  
VDD = 3.6V  
mA  
IO = 0V  
VIN = VDD or VSS  
IDD  
Supply Current  
VDD = 3.6V  
10  
mA  
mA  
Additional Quiescent Supply  
Current  
IO = 0  
input at VDD–0.6V  
DIDD  
VDD = 3.6V  
500  
Table 6. AC Electrical Characteristics (TAMB = 0°C to +85°C)[6]  
V
DD 3.3V ± 0.165V VDD = 3.3V ± –0.3V  
Parameter  
From Input/Condition  
To Output  
Unit  
Min. Typ. Max. Min. Typ. Max.  
Fout  
Operating Frequency (Output)  
REF = 66 to 100 MHz  
25  
–50  
45  
185  
50  
25  
–50  
45  
185 MHz  
tPHASE Error[11]  
Duty Cycle  
tsk(o)[7]  
FBIN  
50  
55  
pS  
%
55  
Any Clock Out (100 MHz)  
Any Clock Out  
150 pS  
Any Clock Out or  
FBOUT  
S
l75l  
1.9  
2.5  
l75l  
pS  
Jitter (cycle-to-cycle) REF = 100 MHz  
Any Clock Out or  
FBOUT  
1.3  
1.7  
0.8  
1.2  
2.1  
nS  
[12,13]  
tR  
Any Clock Out or  
FBOUT  
2.7  
nS  
[12,13]  
tF  
TSTABIL  
Stabilization Time[10]  
1
mS  
Notes:  
6. All typical values are measured at TAMB = 25°C.  
7. The tSK(0) specification is only valid for equal loading of all outputs (30 pF/500Ω).  
8. The specifications for parameters in this table are applicable only after any appropriate stabilization time as elapsed.  
9. Ref Duty Cycle must be 50% ±5%.  
10. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency,  
fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew and jitter parameters given  
in the switching characteristics table are not applicable.  
11. Uses the averaging feature of the scope to remove the jitter component.  
12. The test load is 30 pF/500Ω.  
13. tR/tF are measured at 0.4V to 2.0V.  
Document #: 38-07391 Rev. **  
Page 3 of 6  
CYZ2509  
Parameter Measurement Information  
3 V  
0 V  
Input  
50% VDD  
2 V  
From Output  
Under Test  
tpd  
VOH  
VOL  
2 V  
500 Ohm  
30 pF  
Output  
50% VDD  
0.4 V  
0.4 V  
tr  
tf  
Load Circuit for Outputs  
Voltage Waveforms Propagation Delay Times  
Figure 1. Load Circuit and Voltage Waveforms[14,15,16]  
CLKIN  
FBIN  
tphase error  
FBOUT  
Any Y  
tsk(o)  
Any Y  
Any Y  
tsk(o)  
Figure 2. Phase Error and Skew Calculations  
Ordering Information  
Part Number  
Package Type  
24-pin TSSOP  
24-pin TSSOP–Tape and Reel  
Production Flow  
CYZ2509ZC  
Commercial, 0°C to +85°C  
Commercial, 0°C to +85°C  
CYZ2509ZCT  
Notes:  
14. CL includes probe and jig capacitance.  
15. All input pulses are supplied by generators having the following characteristics: Input Frequency ≤ 100 MHz, Zo = 50Ω, tr ≤ 1.2 ns, tf < 1.2ns.  
16. The outputs are measured one at a time with one transition per measurement.  
Document #: 38-07391 Rev. **  
Page 4 of 6  
CYZ2509  
Package Drawing and Dimension  
24-lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24  
51-85119  
All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-07391 Rev. **  
Page 5 of 6  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYZ2509  
Document Title: CYZ2509 Nine-output Zero Delay Buffer  
Document Number: 38-07391  
Orig. of  
Rev.  
ECN No. Issue Date  
113451 06/07/02  
Change  
Description of Change  
**  
ITH  
New Data Sheet  
Document #: 38-07391 Rev. **  
Page 6 of 6  
厂商 型号 描述 页数 下载

CYPRESS

 		CYZ2509ZCT [ Clock Driver, PDSO24 ] 6 页

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