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OXU200-LQAG

型号：

OXU200-LQAG

品牌：

PLX[ PLX TECHNOLOGY ]

页数：

16 页

PDF大小：

632 K

下载PDF手册
Data Sheet  
OXU200  
USB High-Speed Peripheral Controller  
Features  
„
„
„
High‐speed USB peripheral controller  
Compatible with the Universal Serial Bus Specification, Revision 2.0  
Single 3.3 V power supply, flexible I/O voltage of 1.65 V to 3.6 V  
(LVCMOS/TTL) to interface to a wide range of CPUs and DSPs  
„
„
16‐bit memory mapped interface can gluelessly interface to most  
popular microprocessors and DSPs  
8 Kbytes of on‐chip SRAM buffer, optimized for performance and  
cost  
„
„
DMA slave channel lowers CPU utilization  
Allows up to 8 bi‐directional endpoints for support of  
multi‐function systems  
„
Transfer‐oriented control model handles all USB signaling and  
packetization, minimizes CPU loading  
„
„
„
Low power operation, suitable for mobile applications  
Ultra‐low‐power sleep mode and power‐saving suspend state  
Integrated PLL supports 12 MHz external crystal or crystal  
oscillator  
„
Small package and footprint saves board space  
†
12×12 mm LQFP, 100‐pin, RoHS compliant  
6×6 mm BGA, 64‐ball, RoHS compliant  
†
„
„
Fast microprocessor access cycle and multi‐buffering support for  
all four types of USB transfers  
Operating temperature range: ‐40° to 85° C  
DS-0051 Mar 07  
External—Free Release  
1
OXU200 Data Sheet  
Oxford Semiconductor, Inc.  
Device  
Overview  
The Oxford Semiconductor OXU200 is a low‐cost, single‐port USB  
high‐speed peripheral controller. It is designed for high performance and  
enables embedded systems to perform high‐speed USB data transfers for  
peripheral connectivity when connected to a USB host.  
The low‐power, high‐performance design and small package size make  
the OXU200 ideal for adding high‐speed USB into a broad range of  
mobile consumer electronics, including cell phones, portable GPS  
devices, and PDAs.  
The OXU200 has a 16‐bit SRAM‐like memory‐mapped interface and  
flexible I/O voltage that can connect gluelessly to most popular CPUs  
and DSPs. The 8 Kbytes of on‐chip SRAM buffer is cost and performance  
optimized to reduce system interrupts and minimize processor  
overhead.  
Software solutions for the OXU200 include USB device drivers and the  
Oxford Semiconductor USBLinkTM product suite. USBLink Peripheral  
has been ported to a wide variety of real time operating systems  
including VxWorks®, ThreadX®, and Nucleus®.  
In addition, Oxford Semiconductor also makes available low‐level  
controller drivers for other native USB stacks such as those included with  
Windows® CE 5.0 and Linux® 2.6.x.  
Figure 1 shows the OXU200 architectural diagram.  
Figure 1 OXU200 Architectural Diagram  
Clock/  
OSC1  
Osc Pads  
and Clk  
OSC2  
Div  
System Configuration  
& Control Registers  
ACK  
REQ  
DMA  
Interface  
USB Peripheral  
Controller Registers  
DP  
DM  
/RESET  
USB  
Peripheral  
Controller  
HS USB  
XCVR  
/CS  
/WR  
/RD  
INT  
VBUS  
µP  
Interface  
8 Kbyte  
Memory  
A[10:1]  
D[15:0]  
2
External—Free Release  
DS-0051 Mar 07  
Oxford Semiconductor, Inc.  
OXU200 Data Sheet  
Development  
Support  
The OXU200 product suite includes the USB controller as well as the  
protocol stacks and the driver software that enable a wide variety of USB  
applications. This unique ability to deliver a total hardware and software  
solution sets Oxford Semiconductor apart from other semiconductor  
companies and benefits customers by:  
„
„
„
Shortening time to market  
Reducing risk  
Offering a single source for hardware and software, thereby  
reducing the number of suppliers the customer has to deal with  
Oxford Semiconductor is a Microsoft® Windows® Embedded Partner  
and has developed peripheral controller drivers for Windows CE 5.0.  
Similar software support is also available for Linux® 2.6.x.  
For customers using a real time operating system (RTOS) such as  
VxWorks®, ThreadX®, Nucleus®, OSE, LynxOS® and AMXTM among  
others, Oxford Semiconductor offers its USBLink peripheral software  
solution.  
The USBLink Product Suite is a modularized approach to providing USB  
connectivity for a wide variety of embedded products. Due to its flexible  
architecture and broad based support for USB host, peripheral and OTG  
applications, Oxford Semiconductor can tailor the USBLink software  
deliverables to meet each customer’s USB requirements.  
The USBLink solutions are configurable and can support systems with:  
„
„
„
„
Big or little endian processors  
DMA or non‐DMA USB controllers  
A wide variety of USB controllers, including the OXU200  
A broad range of operating systems  
Oxford Semiconductor has over eight years of experience developing  
embedded USB technology. Its USBLink software has been ported to  
over twenty different operating systems and a wide variety of embedded  
architectures. USBLink is shipping in many millions of units.  
Sample  
Applications  
„
„
„
„
Cell phones  
Personal Digital Assistants (PDA)  
Portable media players  
Portable GPS systems  
DS-0051 Mar 07  
External—Free Release  
3
OXU200 Data Sheet  
Oxford Semiconductor, Inc.  
Electrical  
Characteristics  
Table 1 to Table 6 detail the required operating conditions for the device  
and the DC and AC electrical characteristics.  
Table 1 Absolute Maximum Device Ratings  
Symbol  
DD3.3  
DD1.8  
DDW  
Parameter  
3.3 V power supply  
Condition  
Min  
Max  
Unit  
V
V
V
V
T
-0.3  
4.0  
V
1.8 V power supply  
-0.3  
-0.3  
-0.3  
-40  
2.16  
4.0  
V
V
Wide-range I/O power supply  
DC input voltage  
4.0  
V
I
Storage temperature  
+150  
°C  
S
Note:  
Permanent device damage may occur if absolute maximum ratings are exceeded. Func‐  
tional operation should be restricted to the normal operating conditions specified in the  
following section. Exposure to absolute maximum rating conditions for extended periods  
may affect device reliability.  
Table 2 Recommended Operating Conditions  
Symbol Parameter  
3.3 V power supply  
Condition  
Min  
Max  
Unit  
V
V
V
V
V
T
2.97  
3.63  
V
DD3.3  
1.8 V power supply  
1.62  
1.62  
0
1.98  
3.63  
3.6  
V
V
DD1.8  
DDW  
I3.3  
Wide-range I/O power supply  
DC input voltage of 3.3 V pins  
DC input voltage of wide-range pins  
Operating temperature  
V
0
1.1*V  
V
IW  
DDW  
-40  
+85  
°C  
O
Table 3 DC Characteristics, High-Speed USB I/O Signals: D and D Only  
P
M
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
V
High-speed differential input  
sensitivity  
|V  
V |  
I(D ) -- I(D )  
300  
mV  
P
M
HSDIFF  
V
V
High-speed data signaling  
common mode range  
-50  
500  
100  
mV  
HSCM  
HSSQ  
High-speed squelch detection  
threshold  
Squelch detected  
mV  
mV  
mV  
No squelch detected  
150  
-10  
V
V
V
V
High-speed idle output voltage  
(differential)  
10  
10  
HSIO  
High-speed low-level output  
voltage (differential)  
-10  
mV  
mV  
mV  
HSOL  
HSOH  
CHIRPK  
High-speed high-level output  
voltage (differential)  
-360  
-900  
400  
-500  
Chirp-K output voltage  
(differential)  
4
External—Free Release  
DS-0051 Mar 07  
Oxford Semiconductor, Inc.  
OXU200 Data Sheet  
Table 4 DC Characteristics, Logic Signals  
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
V
Low-level output voltage  
0.4  
V
OL  
V
V
V
High-level output voltage  
Low-level input voltage  
High-level input voltage  
V
V
V
V
V
V
= 3.3 V  
= 1.8 V  
= 3.3 V  
= 1.8 V  
= 3.3 V  
= 1.8 V  
2.4  
V
V
OH  
DDW  
DDW  
DDW  
DDW  
DDW  
DDW  
0.75*VDDW  
0.8  
V
IL  
0.3*V  
V
DDW  
2.0  
V
IH  
0.7*V  
V
DDW  
C
C
C
I
Input capacitance  
2.2 (typical)  
2.2 (typical)  
2.2 (typical)  
pF  
pF  
pF  
µA  
IN  
Output capacitance  
Bi-directional capacitance  
Input leakage current  
OUT  
BI  
No pull up or pull down  
-10  
10  
IN  
Note:  
The capacitances listed above do not include pad capacitance and package capacitance.  
One can estimate pin capacitance by adding pad capacitance of about 0.5 pF and the  
package capacitance, which is about 0.86 pF max for LQFP.  
Table 5 DC Characteristics, Regulator  
Symbol  
rout  
Parameter  
Output voltage  
Condition  
Min  
1.8 (typical)  
150  
Max  
Unit  
V
Driving current <= 100 mA  
V
I
Driving current  
V
= 3.3 V  
DD3.3A  
mA  
rdrive  
Output voltage = 1.8 V  
t
Start-up time when enabled  
V
V
= 3.3 V  
25 (typical)  
µs  
rst  
DD3.3A  
= 1.62 V (90%)  
REGOUT  
Note:  
The VDD3.3A pin that corresponds to the regulator supply is QFP pin 81.  
Table 6 AC Characteristics, High-Speed D and D Driver Characteristics  
P
M
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
t
High-speed differential rise time  
500  
ps  
HSR  
HSF  
t
High-speed differential fall time  
Driver output impedance  
500  
ps  
R
Equivalent resistance used as internal  
chip  
40.5  
49.5  
Ω
DRV  
DS-0051 Mar 07  
External—Free Release  
5
OXU200 Data Sheet  
Oxford Semiconductor, Inc.  
Power  
Table 7 gives typical power consumption figures for the OXU200.  
Consumption  
Table 7 OXU200 Power Consumption  
Min  
Max  
75  
Unit  
mA  
mA  
µA  
µA  
Peripheral operational current, High Speed  
Peripheral operational current, Full Speed  
Peripheral suspend state current  
Power save state current  
50  
400 (typical)  
150 (typical)  
The above measurements are at typical process corner and room  
temperature and do not account for process and temperature variations.  
Peripheral operational current is measured with a 5 m cable with  
maximum switching and BULK OUT transfer at 400 Mbps with 92.6%  
bus utilization during one microframe. The actual average current in  
customer applications will be lower.  
6
External—Free Release  
DS-0051 Mar 07  
Oxford Semiconductor, Inc.  
OXU200 Data Sheet  
Pin Layout  
The OXU200 is supplied as a 100‐pin LQFP package and as a 64‐ball BGA  
package. Figure 2 shows the pin layout of the 100‐pin OXU200‐LQAG  
package.  
Figure 2 OXU200 100-Pin LQFP Package (Top View)  
73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51  
75 74  
NC  
NC  
76  
77  
78  
79  
80  
81  
82  
50  
49  
48  
OSC1  
OSC2  
VDD3.3A  
VDD3.3  
47 VSSA  
46 RREF  
NC  
V
REGOUT  
VDD3.3A  
45  
44 DP  
DM  
VSSA  
VSS  
VDD3.3A  
43  
42  
41  
40  
39  
83  
84  
VSSA  
VSS  
VDD1.8  
VDDW  
85  
VDD1.8  
/CS  
/RESET 86  
TEST  
GPIO 88  
87  
38 NC  
DRQ  
ACK  
89  
90  
37  
36  
35  
34  
NC  
NC  
A10  
NC  
OXU200-LQAG  
91  
92  
RSVD0  
NC  
33 A9  
RSVD2 93  
32  
31  
A8  
RSVD1  
94  
95  
VDDW  
VDDW  
D0  
30  
29  
28  
A7  
A6  
A5  
96  
97  
98  
D1  
D2  
27  
26  
D3  
VSS  
99  
VDD1.8  
100  
VDDW  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
24 25  
Table 8 lists the LQFP pin allocations.  
DS-0051 Mar 07  
External—Free Release  
7
OXU200 Data Sheet  
Oxford Semiconductor, Inc.  
Table 8 OXU200 100-Pin LQFP Pin Allocations (Sheet 1 of 2)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
Processor Interface (33 pins)  
2, 3, 4, 5, 8, 9, 10, 16  
11, 13, 14, 15, 16,  
96, 97, 98, 99  
MSBCT  
D - D  
16-bit data bus. Pull-up/pull-down can be controlled  
through register 0x034, bits 2:1. Default is none  
0
15  
22, 23, 24, 25, 28, 10  
29, 30 32, 33, 35  
MSID  
MSIU  
MSIU  
MSIU  
MOCT  
A - A  
Address bus for direct address space of 2 Kbytes.  
Default is pull-down  
1
10  
20  
21  
39  
19  
1
1
1
1
/WR  
/RD  
/CS  
/INT  
Write strobe. Pull-up can be disabled through register  
0x034, bit 13. Default is pull-up  
Read strobe. Pull-up can be disabled through register  
0x034, bit 13. Default is pull-up  
Chip select. Pull-up can be disabled through register  
0x034, bit 13. Default is pull-up  
Interrupt to the MCU.This pin can be software  
configured as a driven output or open drain. Open  
drain is the default  
86  
89  
90  
1
1
1
MSIU  
MOCT  
MSI  
/RESET  
DRQ  
Hardware reset. Pull-up is always enabled  
DMA request output  
ACK  
DMA acknowledge. Pull-up/pull-down can be  
controlled through register 0x03A, bits 1:0. Default is  
none  
General Purpose I/O (1 pin)  
88  
Power & Ground (34 pins)  
1
BC  
GPIO  
General purpose I/O  
1, 12, 27, 41, 51,  
65, 75, 83  
8
V
Digital/wide-range ground  
Analog ground  
SS  
42, 47, 69, 74, 82  
5
8
V
V
SSA  
6, 18, 40, 53, 57,  
66, 84, 100  
1.8 V core power. V  
supplies  
must be used for the  
REGOUT  
DD1.8  
43, 48, 70, 73, 81  
56, 78  
5
2
6
V
V
V
Analog +3.3 V power  
Digital +3.3 V power  
DD3.3A  
DD3.3  
DDW  
7, 17, 26, 31, 85,  
95  
Wide-range I/O +1.8 V to +3.3 V. If using +1.8 V,  
may be used for these supplies  
V
REGOUT  
USB Interface (4 pins)  
44, 45  
46  
2
1
B
B
D , D  
Data lines for USB peripheral port  
P
M
R
Connect external reference resistor (12 KΩ +/- 1%) to  
REF  
V
SSA  
72  
1
5I  
V
V
input used by the voltage comparators of the  
BUS  
BUS  
peripheral port for connection  
8
External—Free Release  
DS-0051 Mar 07  
Oxford Semiconductor, Inc.  
OXU200 Data Sheet  
Table 8 OXU200 100-Pin LQFP Pin Allocations (Sheet 2 of 2)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
Clock Interface (2 pins)  
50  
1
I
OSC  
OSC  
Input. A 12 MHz passive crystal should be connected  
across the two pins (OSC and OSC ). Optionally, a  
1
1
2
12 MHz oscillator can be connected to OSC while  
1
keeping OSC unconnected  
2
49  
1
O
Output  
2
Internal Voltage Regulator (1 pin)  
80  
1
O
V
Internal voltage regulator output of 1.8 V. This output  
REGOUT  
must be connected to the V  
supply of the chip  
DD1.8  
(and may be connected to V  
1.8 V)  
if wide-range IO is at  
DDW  
Test (2 pins)  
87  
1
1
ID  
I
TEST  
Factory test mode. This pin should be grounded or  
left floating (has an internal pull-down) for normal  
operation. Pull-down is always enabled  
64  
XMODE  
This pin must be grounded for normal operation  
Miscellaneous (23 pins)  
91, 94, 93  
3
-
-
RSVD , RSVD , RSVD  
2
Reserved. These pins must be grounded  
0
1
34, 36, 37, 38, 52, 20  
54, 55, 58, 59, 60,  
61, 62, 63, 67, 68,  
71, 76, 77, 79, 92  
NC  
No connection. These pins should be left floating  
Note to Table 8:  
1
Type key: format is [(L)(W_)X(Y)(_Z(A))] where the following conventions apply:  
L—Logic Level  
W—Tolerance  
X—Type  
Input  
Y—Pull  
Pull up  
Z—Drive  
T—Tristate  
Tristate  
Normal  
(2)  
(3)  
Multi-voltage:  
3.3 V CMOS  
2.5 V CMOS  
1.8 V CMOS  
5
5 V  
I
U
D
T
M
C
3.3 V  
O
Output  
Pull down  
S
Schmitt Trigger  
B
Bidirectional  
None  
2
3
Program to 3.3, 2.5, or 1.8 V by setting the VIO voltage level.  
Program to 2 mA, 4 mA, 6 mA, 8 mA, 10 mA, 12 mA, 14, mA, or 16 mA via the I/O Configura‐  
tion Register (0x034).  
DS-0051 Mar 07  
External—Free Release  
9
OXU200 Data Sheet  
Oxford Semiconductor, Inc.  
Figure 3 shows the ball layout of the 64‐ball OXU200‐TBAG package.  
Figure 3 OXU200 64-ball BGA Package (Top View)  
NC  
VSS  
VBUS  
XMODE  
VSS  
NC  
RREF  
/CS  
OSC1  
VSSA  
DP  
OSC2  
VDD3.3A  
DM  
VREGOUT  
/RESET  
TEST  
8
7
6
5
4
3
2
1
VSSA  
VDD3.3  
VDD3.3  
GPIO  
DRQ  
RSVD0  
RSVD2  
D1  
VDDW  
VDD1.8  
A9  
A6  
RSVD1  
D3  
VSSA  
NC  
A7  
ACK  
NC  
D0  
D12  
A3  
D13  
D14  
D15  
VDD3.3A  
VSS  
A10  
D6  
D7  
D10  
/RD  
/WR  
A8  
D2  
D5  
D9  
A1  
A5  
D4  
VDD1.8  
D8  
D11  
VDDW  
/INT  
A2  
A4  
A
B
C
D
E
F
G
H
Table 9 lists the BGA ball allocations.  
10  
External—Free Release  
DS-0051 Mar 07  
Oxford Semiconductor, Inc.  
OXU200 Data Sheet  
Table 9 OXU200 64-Ball BGA Ball Allocations (Sheet 1 of 2)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
Processor Interface (33 pins)  
A3, B3, A2, C4, A1,  
B2, C3, C2, C1, D2,  
D3, D1, D5, E4, E3,  
E2  
16  
MSBCT  
D - D  
16-bit data bus. Pull-up/pull-down can be controlled through  
register 0x034, bits 2:1. Default is none  
0
15  
G2, G1, E5, H1, H2, 10  
F4, G3, H3, F5, H4  
MSID  
MSIU  
MSIU  
MSIU  
MOCT  
A - A  
Address bus for direct address space of 2 Kbytes. Default is  
pull-down  
1
10  
F2  
F3  
F6  
F1  
1
1
1
1
/WR  
/RD  
/CS  
/INT  
Write strobe. Pull-up can be disabled through register 0x034,  
bit 13. Default is pull-up  
Read strobe. Pull-up can be disabled through register 0x034,  
bit 13. Default is pull-up  
Chip select. Pull-up can be disabled through register 0x034,  
bit 13. Default is pull-up  
Interrupt to the MCU.This pin can be software configured as a  
driven output or open drain. Open drain is the default  
B8  
B6  
A5  
1
1
1
MSIU  
MOCT  
MSI  
/RESET  
DRQ  
Hardware reset. Pull-up is always enabled  
DMA request output to support one channel  
ACK  
DMA acknowledge. Pull-up/pull-down can be controlled  
through register 0x03A, bits 1:0. Default is none  
General Purpose I/O (1 pin)  
A6  
Power & Ground (14 pins)  
1
B
GPIO  
General purpose I/O  
D4, D7, E7  
A7, G5, G7  
B1, E6  
3
3
2
2
2
2
V
V
V
V
V
V
Digital ground  
Analog ground  
SS  
SSA  
1.8 V core power. V  
must be used for the supplies  
DD1.8  
DD3.3A  
DD3.3  
DDW  
REGOUT  
H5, H7  
Analog +3.3 V power  
Digital +3.3 V power  
C6, C7  
D6, E1  
Wide-range I/O +1.8 V to +3.3 V. If using +1.8 V, V  
may be used for the supplies  
REGOUT  
USB Interface (4 pins)  
G6, H6  
2
1
1
B
5I  
B
D , D  
Data lines for USB peripheral port  
P
M
C8  
F7  
V
V
input is used to detect connection to a host  
BUS  
BUS  
R
Connect external reference resistor (12 KΩ + 1%) to V  
SSA  
REF  
DS-0051 Mar 07  
External—Free Release  
11  
OXU200 Data Sheet  
Oxford Semiconductor, Inc.  
Table 9 OXU200 64-Ball BGA Ball Allocations (Sheet 2 of 2)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
Clock Interface (2 pins)  
G8  
1
I
OSC  
OSC  
Input. A 12 MHz passive crystal should be connected across  
the two pins (OSC and OSC ). Optionally, a 12 MHz oscillator  
1
2
1
2
can be connected to OSC while keeping OSC unconnected  
1
2
H8  
1
O
Output  
Internal Voltage Regulator (1 pin)  
A8  
1
O
V
Internal voltage regulator output of 1.8 V. This output must be  
connected to the V supply of the chip (and may be  
REGOUT  
DD1.8  
connected to V  
if wide-range IO is at 1.8 V)  
DDW  
Test (2 pins)  
B7  
1
1
ID  
I
TEST  
Factory test mode. This pin should be grounded or left floating  
(has an internal pull-down) for normal operation. Pull-down is  
always enabled  
D8  
XMODE  
This pin must be grounded for normal operation  
Miscellaneous (7 pins)  
B5, C5, B4  
3
4
-
-
RSVD , RSVD , Reserved. These pins must be grounded  
0
1
RSVD  
2
A4, E8, F8, G4  
NC  
No connect. These pins should be left floating  
Note to Table 9:  
1
Type key: format is [(L)(W_)X(Y)(_Z(T))] where the following conventions apply:  
L—Logic Level  
W—Tolerance  
X—Type  
Input  
Y—Pull  
Pull up  
Z—Drive  
T—Tristate  
Tristate  
Normal  
(2)  
(3)  
Multi-voltage:  
3.3 V CMOS  
2.5 V CMOS  
1.8 V CMOS  
5
5 V  
I
U
D
T
M
C
3.3 V  
O
Output  
Pull down  
S
Schmitt Trigger  
B
Bidirectional  
None  
2
3
Program to 3.3, 2.5, or 1.8 V by setting the VIO voltage level.  
Program to 2 mA, 4 mA, 6 mA, 8 mA, 10 mA, 12 mA, 14, mA, or 16 mA via the I/O Configuration  
Register (0x034).  
12  
External—Free Release  
DS-0051 Mar 07  
Oxford Semiconductor, Inc.  
OXU200 Data Sheet  
Package  
Layout  
Figure 4 shows the package layout for the 100‐pin LQFP package.  
Figure 4 100-Pin LQFP  
DS-0051 Mar 07  
External—Free Release  
13  
OXU200 Data Sheet  
Oxford Semiconductor, Inc.  
Figure 5 shows the package layout for the 64‐ball BGA.  
Figure 5 64-Ball TFBGA Package  
14  
External—Free Release  
DS-0051 Mar 07  
Oxford Semiconductor, Inc.  
OXU200 Data Sheet  
Ordering  
Information  
The following conventions are used to identify Oxford Semiconductor  
products.  
OXU200 - LQAG  
Green (RoHS compliant)  
Revision  
Package Type: LQ 100-Pin LQFP  
Part Number  
OXU200 - TBAG  
Green (RoHS compliant)  
Revision  
Package Type: TB 64-Ball TF-BGA  
Part Number  
Contacting  
Oxford Semi-  
conductor  
See the Oxford Semiconductor website (http://www.oxsemi.com) for  
further detail about Oxford Semiconductor devices, or email  
sales@oxsemi.com.  
Revision  
Table 10 documents the revisions of this guide.  
Information  
Table 10 Revision Information  
Revision  
Dec 06  
Modification  
First publication  
Jan 07  
Added BGA chip layout, BGA pin allocations, and BGA package  
information  
Feb 07  
Mar 07  
Miscellaneous editorial changes  
Added the Certified USB logo to the title page  
DS-0051 Mar 07  
External—Free Release  
15  
OXU200 Data Sheet  
Oxford Semiconductor, Inc.  
USBLink is a trademark of Oxford Semiconductor, Inc.  
VxWorks is a registered trademark of Wind River Systems.  
ThreadX is a registered trademark of Express Logic, Inc.  
Nucleus is a registered trademark of Mentor Graphics Corporation.  
Windows is a trademark of Microsoft, Inc., registered in the US and other countries.  
LynxOS is a registered trademark of LynuxWorks, Inc.  
AMX is a trademark of KADAK Products LTD.  
Linux is a registered trademark of Linus Torvalds.  
All other trademarks are the property of their respective owners.  
© Oxford Semiconductor, Inc. 2007  
The content of this document is furnished for informational use only, is subject to change without notice, and should not be  
construed as a commitment by Oxford Semiconductor, Inc. Oxford Semiconductor, Inc. assumes no responsibility or liability for  
any errors or inaccuracies that may appear in this document.  
16  
External—Free Release  
DS-0051 Mar 07  
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