IXF6401BEC7,PDF,IXF6401BEC7 PDF资料,Datasheet,下载IXF6401BEC7技术资料

IXF6401 Broadband Access Processor

64 Bit, 66 MHz

Datasheet

Product Features

I General Performance

I Upper-Layer Assist

—Integrated Asynchronous Transfer Mode

(ATM) Optical Carrier (OC)-12c

Segmentation and Reassembly (SAR)

—Full-duplex, line-rate operation for even

64-byte, small packets

—LEC ID, ELAN ID, LLC/SNAP,

MPOA, and IP encapsulations

—LAN, MPOA, MPLS, and IP protocol

assist

—Programmable header encapsulation or

tagging

—64-bit architecture

—Hardware encapsulation and tagging

—Hardware packet formatting

—Full source code for device drivers

—Packet and VC tagging supported

—Concurrent cell-or-packet counter

reporting per VC for ease in tracking

statistics

—Nine transmit and receive report-ring

size configurations

—Sixteen offset configurations per receive

VC per packet and/or per buffer

—0 to 255 bytes offset configurations per

VC per packet in transmit direction on

byte boundary

I Buffer Management

—Full scatter/gather Direct Memory

Access (DMA)

—Extensive transmit and receive buffering

—Two-dimensional link-list packet

queuing

—64 K internal transmit packet descriptor

and packet buffer pools; 36 K receive

buffer pool

I Traffic Shaping and Policing

—Multiple buffer sizes and buffer pools

—Up to 64 K VCs supported

—Two and four-bank, structured SDRAM

supported

—Traffic-shaping resources for up to 4 K

CBR rates and at least 64 K VBR rates

—Flow-through and pipelined SSRAM

supported

—Granularity for rates down to 1 Kbps

—Time-wheel shaper for ABR/UBR, with

guaranteed frame rate

I Interfaces

—OC-12c or Quad OC-3c

—Glueless, 64-bit SSRAM and SDRAM

I/F

—PCI 2.1 compliant, 33- or 66-MHz, 32-

or 64-bit operation

—Dual Generic Cell Rate Algorithm

(GCRA) policing per receive VC

—Weighted-fair queuing and dynamic-

priority arbitration

I Process Technology

—UTOPIA 1, 2, 3

—ATM or POS

—3.3 V ± 5% tolerant I/Os

—0.35 µm CMOS design

—352-pin EBGA package

—Power consumption 6 W @ 66 MHz

Order Number: 273469-001

April 2001

I Features

—AAL Types 0, 1, 3/4, and 5 supported

I Local Area Network Emulation (LANE)

Hardware Assist

—LANE V1 and V2 packet-header

generation

—LEC ID, ELAN ID, and/or LLC/SNAP

encapsulation

—Separate LANE control buffer pool with

4 K bitmap

—LANE flush protocol assist

—TM 4.0 compliant

—UBR, CBR, VBR, and ABR flow

control supported

—64-byte, virtual-channel (VC)

descriptors

—Scalable to OC-48

—ATM and Packet-over-SONET (POS)

—Programmable packet holding mode

—“Wait for Flush” reply message

UTOPIA 1, 2, and 3 supported

—PCI 2.1 compliant

The power of the IXF6401 Broadband Access Processor is its flexibility, scalability, and

efficiency, and its integration of the different network traffic types. The processor’s architecture

simplifies and speeds OEM development by providing industry-standard interfaces for a 64-bit,

66-MHz PCI bus or 64-bit Synchronous Static Random Access Memory (SSRAM) /

Synchronous Dynamic RAM (SDRAM) local-memory bus. Other standard interfaces include

Universal Test and Operations Interface (UTOPIA) levels 1, 2, and 3; Asynchronous Transfer

Mode (ATM); and Packet-over-SONET (Synchronous Optical Network) interfaces for direct

coupling of a broad range of layer-1 physical interfaces.

The IXF6401 processor’s 64-bit, 66-MHz local-memory bus acts in concert with the 64-bit, 66-

MHz PCI bus to provide up to 8 Gbps of bus bandwidth. An onboard DMA “engine” controls

access to and from the PCI and local-memory buses and can run in master or slave mode.

The IXF6401 processor achieves its speed by using extensive, dedicated, and hardware-based

state machines. OEMs can use APIs that run on top of the processor’s device driver to achieve

value-added, differentiated services.

Information in this document is provided in connection with Intel^®products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. The IXF6401 Broadband Access Processor may

contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata

are available on request.

The IXF6401 Broadband Access Processor may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel’s web site at http://www.intel.com.

*Other names and brands may be claimed as the property of others.

Datasheet

IXF6401 Broadband Access Processor

Contents

1.0

Architectural Overview............................................................................ 7

1.1

1.2

1.3

1.4

Hardware Packet Processing................................................................................8

ATM Processing....................................................................................................8

Traffic Shaping and Policing................................................................................10

Basic Operation...................................................................................................10

2.0

3.0

Pinout Information................................................................................. 13

2.1

2.2

IXF6401 Broadband Access Processor Ball Pinout ............................................13

Pin and Signal-Name Cross References.............................................................14

Bus-Interface Information ..................................................................... 23

3.1

3.2

PCI Interface .......................................................................................................23

Local-Memory Interface.......................................................................................24

3.2.1 General Features ...................................................................................24

3.2.2 Arbitration...............................................................................................24

3.2.3 Local Memory Configuration ..................................................................25

3.2.3.1 SDRAM Configuration ...............................................................25

3.2.3.2 SSRAM Configuration ...............................................................26

UTOPIA Interface................................................................................................28

3.3.1 UTOPIA I................................................................................................28

3.3.2 UTOPIA II...............................................................................................29

3.3.3 UTOPIA III..............................................................................................29

3.3.4 UTOPIA Modes ......................................................................................30

3.3.5 POS Mode..............................................................................................30

3.3

4.0

Package Information.............................................................................. 31

4.1

4.2

Mechanical Specifications...................................................................................31

Thermal Specifications........................................................................................31

4.2.1 Die Temperature ....................................................................................32

4.2.2 Package Temperatures..........................................................................32

4.2.3 Thermal Solutions ..................................................................................33

4.2.3.1 System Requirements for Thermal Efficiency ...........................35

4.2.3.2 Recommendations for Thermal Solutions .................................36

4.2.4 Thermal-Solution Vendors......................................................................37

Ordering Information ...........................................................................................38

4.3

5.0

Electrical Specifications........................................................................ 39

5.1

5.2

5.3

5.4

Absolute Maximum Ratings.................................................................................39

Operating Conditions...........................................................................................39

DC Specifications................................................................................................39

Timing Specifications ..........................................................................................43

5.4.1 Clock Timing...........................................................................................43

5.4.2 Clock Specifications ...............................................................................43

5.4.3 PCI Timing Parameters..........................................................................44

5.4.4 UTOPIA Timing Parameters...................................................................46

5.4.5 Local Memory Bus Timing......................................................................47

Datasheet

3

IXF6401 Broadband Access Processor

Figures

1

IXF6401 Broadband Access Processor in ATM/POS Application.........................7

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

Architectural Block Diagram.................................................................................. 8

ATM Functionality ................................................................................................. 9

IXF6401 Broadband Access Processor Using an IXP1200 ................................11

IXF6401 Processor Ball Configuration ................................................................13

Local-Memory Arbitration Timing ........................................................................25

352-Pin Ball Grid Array .......................................................................................31

EBGA Heat Sink Volume Restrictions.................................................................34

EBGA Extruded Heat Sink Measurements .........................................................35

Recommended and Discouraged Via Connections (Top View) ..........................36

Recommended Printed-Circuit-Board Stack Up (Cross-Sectional View) ............36

IXF6401 Broadband Access Processor Markings...............................................38

Tval (min) and Slew Rate....................................................................................42

3.3 V Clock Waveform ........................................................................................43

Output Timing Measurement Conditions.............................................................45

Input Timing Measurement Conditions ...............................................................45

Tval (max) Rising Edge.......................................................................................46

Tval (max) Falling Edge ......................................................................................46

Local Memory Bus Timing Specifications ...........................................................48

Recommended Local Memory Clock Circuitry ....................................................48

4

Datasheet

IXF6401 Broadband Access Processor

Tables

1

2

3

4

5

6

7

Control Structure Memory Requirement..............................................................12

PCI Bus Signals ..................................................................................................14

Local Memory Bus Signals..................................................................................15

UTOPIA/POS Bus Signals ..................................................................................15

JTAG Signals ......................................................................................................16

Miscellaneous Signals.........................................................................................16

Signal Descriptions..............................................................................................17

Supported Clock Speeds and Bus Widths ..........................................................23

PCI Commands and Cycles ................................................................................23

Sample SDRAM Configuration: Bank 0...............................................................25

Sample SDRAM Configuration: Bank 1...............................................................26

Sample SSRAM Configuration: Banks 0 and 1...................................................27

Sample SSRAM Configuration: Banks 2 and 3...................................................27

UTOPIA-I Bit Settings..........................................................................................29

UTOPIA-II Bit Settings.........................................................................................29

UTOPIA-III Bit Settings........................................................................................29

UTOPIA Modes ...................................................................................................30

Mechanical Dimensions ......................................................................................31

EBGA Thermal Absolute Maximum Rating .........................................................32

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

T

as a Function of Ambient Temperature and Airflow: Without Heat Sink ....33

as a Function of Ambient Temperature and Airflow: Using a Heat Sink ....33

case

Thermal-Solution Vendor List..............................................................................37

IXF6401 Broadband Access Processor Date and Part-Number Codes..............38

Absolute Maximum Ratings.................................................................................39

Operating Conditions...........................................................................................39

DC Characteristics (Single-PHY,155 Mbps, 622 Mbps)......................................40

DC Characteristics for (Multi-PHY, 622 Mbps)....................................................40

DC Characteristics for UTOPIA Level 3 Baseline Text .......................................41

DC Characteristics for PCI ..................................................................................41

DC Characteristics for LM ...................................................................................42

Power Dissipation Requirements for Thermal Design.........................................42

33-MHz/66-MHz Timing Parameters...................................................................43

33-MHz and 66-MHz Timing Parameters............................................................44

Transmit Timing...................................................................................................46

Receive Timing....................................................................................................47

Local Memory Bus Timing Parameters ...............................................................47

Datasheet

5

IXF6401 Broadband Access Processor

Revision History

Date

Revision

Description

4/9/01

001

This is the first publication of this document.

6

Datasheet

IXF6401 Broadband Access Processor

1.0

Architectural Overview

The IXF6401 Broadband Access Processor provides a flexible and powerful solution for products

designed for broadband Synchronous Optical Network (SONET) networks.

Figure 1 shows how the IXF6401 processor could be incorporated into an Asynchronous Transfer

Mode (ATM)/Packets over SONET (POS) solution. Figure 2 is a block diagram of the processor’s

architecture.

Figure 1. IXF6401 Broadband Access Processor in ATM/POS Application

PCI Bus - 64-bits@66 MHz

Single OC3c POS

Quad OC3c ATM

Single OC12C ATM/POS

SSRAM

SDRAM

Intel_®

FRAMER

IXF6012

IXF6401

UTOPIA 1,2,3/POS

32-bits@50 MHz

Local Memory Bus

64-bits@66 MHz

PHY

(0.35µ, 3.3 V)

A8709-01

Datasheet

7

IXF6401 Broadband Access Processor

Figure 2. Architectural Block Diagram

Reassembly

or

Rx-packet

Enqueue

Engine

Rx-DMA

CMD Queue

Receive DMA

Receive Report

Generator

Rx-UTOPIA

ATM/POS

Interface

8,16 or 32 bit

PCI

Master

64-bit

Rx-FIFO1

2 Kbyte

Rx-DMA

Data Queue

66 MHz

PCI

Slave

Tx

Packet

Link

Pointer

Manager

Tx

Time

Wheel

Tx

Rx

Buffer

Pools

Tx

Traffic

Shaper

PCI 2 LM

LM 2 PCI

CPU DMA

Packet

Enqueue

Engine

Scheduler

Manager

LM

Slave

LM

Master

64-bit

66 MHz

SSRAM

SDRAM

Interface

Segmentation

or

Tx-UTOPIA

ATM/POS

Interface

8,16 or

Tx-DMA

CMD Queue

Transmit DMA

Transmit Report

Generator

Tx-

CRC32

Gen-

Packet

Dequeue

Engine

Tx-

FIFO1

1 Kbyte

erator

Tx-DMA

32 bit

Data Queue

A8419-01

1.1

Hardware Packet Processing

The IXF6401 processor performs all relevant layer-2 functions and provides extensive hardware

assistance to your CPU, FPGA, or ASIC-based, higher-layer processing engine. ATM

segmentation and reassembly (SAR), traffic-shaping, packet-tagging, encapsulation, buffer

management, and data transfers between the PCI and local-memory bus via on-chip direct memory

access (DMA) are handled by the IXF6401 processor. This frees your higher-layer engine to focus

on application layers such as bridging, routing, encryption, network operating system,

management, and security.

The processor supports several encapsulation methods that accelerate packet processing at layers 2

and 3 and can automate packet-header generation using the LEC ID, ELAN ID, MAC address, or

any required bit field. The IXF6401 processor performs LLC/SNAP encapsulation and handles

Multiprotocol Over ATM (MPOA), Local Area Network Emulation (LANE), Multiprotocol Label

Switching (MPLS), and Internet Protocol (IP) protocols and any custom packet-tagging scheme.

1.2

ATM Processing

In addition to the high-performance features for higher-layer processing, the IXF6401 processor

still comprises a full suite of ATM processing functions.

8

Datasheet

IXF6401 Broadband Access Processor

It supports ATM AAL 0, 1, 3/4, and 5 and can deliver true Unspecified Bit Rate (UBR), Constant

Bit Rate (CBR), Variable Bit Rate (VBR), and Available Bit Rate (ABR) processing for up to 64 K

virtual channels (VCs). The design features full, 64-byte VC descriptors and is multiport, SONET

capable.

Figure 3. ATM Functionality

Applications

ILMI

Signaling

MPOA

LANE

Hardware Assist

Hardware State

Not Supported

RFC 1483

RFC 1577

AAL 0, 1, 3/4, 5

ATM Layer

Physical

A8420-01

In the ATM mode, the IXF6401 processor provides all of the necessary termination functions

currently established by the ATM Forum and Internet Engineering Task Force (IETF):

• ATM Forum User-Network Interface (UNI) 3.1 ATM Adaptation Layer and ATM Layer

Specifications

• ATM Forum Traffic Management Specifications, Rev. 4.0

• RFC 1483 (Multiprotocol Encapsulation over ATM Adaptation Layer 5 [AAL 5])

• RFC 1626 (Default IP MTU for Use over ATM AAL 5)

• RFC 1577 (Classical IP and ARP over ATM)

• ATM Forum LANE Specification, Version 1.0

• ATM Forum LANE Version 2.0 - LUNI Baseline Document, Draft 5, February 1997

The IXF6401 processor maximizes both chip-level and system-level throughput. The IXF6401

processor supports 128 VC descriptors in its on-chip cache to virtually eliminate latency for

specific VCs (for example, nominated CBR VCs). Adding external, high-speed Synchronous Static

Random Access Memory (SSRAM) to the engine’s local bus increases total capacity to 64 K VCs.

The IXF6401 processor has a sophisticated buffer-management scheme. All buffer pointer

structures (64 K for transmit and 36 K for receive) are internal to the engine, greatly reducing the

number of read/write operations performed during lookup, segmentation, and reassembly. Multiple

buffer sizes and non-contiguous cell-splitting are fully supported in the hardware.

The IXF6401 processor can build a two-dimensional link list to link packets on a per-VC basis and

buffers on a per-packet basis for transmit-packet queuing. This link list not only contains per-

packet address and size, but also may contain per-packet encapsulation.

Datasheet

9

IXF6401 Broadband Access Processor

1.3

Traffic Shaping and Policing

The IXF6401 processor provides granular and efficient traffic shaping, making it an ideal fit for

Digital Subscriber Line Access Multiplexer (DSLAM), Voice-over-IP (VoIP), and class-of-service

sensitive applications. It includes 16 on-chip traffic shapers for CBR/VBR, with a TM-4.0-

compliant ABR scheduler with guaranteed “MCR not Zero” hardware support and onboard RM-

cell processing.

Within a shaped virtual path (VP), each VC can be independently shaped to rates as low as 1-Kbps

increments, giving you extensive control over traffic on a per-VC basis. The IXF6401 processor’s

dual, leaky-bucket, and virtual-scheduling algorithms can be implemented on a per-VC or per-VP

basis.

The processor has no embedded Reduced Instruction Set Computing (RISC) processor in the path

of any per-cell or per-packet transaction that would slow device operation or system throughput.

This massive hardware assist offloads the CPU, saving valuable cycles for other critical tasks such

as bridging, routing, policy execution, encryption, and security.

1.4

Basic Operation

The IXF6401 processor is simple to use. To send a packet to the SONET infrastructure, software

issues a 16-byte Add-Packet command that includes tagging and offset options, packet length,

other per-packet variables, and a VC descriptor number. The descriptor specifies the target cell

header VPI/VCI and traffic-shaping parameters. This may be followed by a series of 8-byte Add-

Buffer commands, telling the engine where the payload resides (in local SDRAM or across the PCI

bus). This is done in case the packet uses multiple buffers.

From this point, the IXF6401 processor takes control. The packet is linked per VC for CBR, VBR,

and ABR connections or the packet is linked on the UBR chain. Once the packet is linked, it is

transmitted at the specified rate, per VC descriptor, with the required encapsulation.

The process of associating a packet with a VC descriptor is an application-level function. For

example, if your application is routing, IP-route matches will direct packets destined to a remote

subnet to a Virtual Path Identifier (VPI) / Virtual Channel Identifier (VCI) defined in a local or

centralized table. In LAN emulation or bridging, a similar process occurs, based on the Media

Access Control (MAC) / Local Exchange Carrier Identification (LEC ID) address.

This association function is performed outside the IXF6401 processor, typically by a network

processor, such as the IXP1200 processor, or a combination of standard CPUs, FPGAs, or ASICs,

in either classic centralized or distributed architectures. Figure 4 shows how the IXF6401 processor

would be used with the IXP1200 network processor.

10

Datasheet

IXF6401 Broadband Access Processor

Figure 4. IXF6401 Broadband Access Processor Using an IXP1200

Optical

Xcvr

PHY

GigE

MAC

SSRAM

Flash

Receive

Buffer

SSRAM

SDRAM

SSRAM

Transmit

Buffer

Pool

UTOPIA SONET

Framer

Receive

Intel_®

IXF6401

Processor

Intel_®

IXF6012

Processor

PCI Bus

IXP1200

16

P2IX

Optical

Xcvr

Processor

IX Bus

Transmit

0.35 micron

3.3 V

PCI Bus

ATM/POS

Intel

PCI

Bridge

LM Bus

64-Bit Optional

66/100MHz

21154

SSRAM

A8710-01

The IXF6401 processor can perform any desired combination of operations on individual packets

and reliably deliver wire-speed Optical Carrier (OC) 12c performance, even for 64-byte packets.

Designs must issue the requisite Add-Packet commands, at whatever rates are required, to achieve

target performance levels.

Full support for newly developed ABR service category and multiprotocols, such as TCP/IP over

ATM, also are supported. On-chip memory enables cached VC descriptors to be registered and

allows extensive cell buffering, which further enhances performance for single-chip OC-12c rate

operation.

To handle changes to networking standards, the IXF6401 processor obtains configuration

information from the PCI address space or from a tightly coupled, local network processor. With its

extensive hardware assist, the IXF6401 processor is able to support multiprotocol data rates of 622

Mbps, full-duplex. That is possible because the higher-layer processor is not in the critical path of

any per-cell transaction.

In PCI-host systems, the IXF6401 processor further increases overall end-system performance and

manageability by off-loading, from the end-system’s main processor, the ATM service-specific

software functions, IP over ATM, and network statistical and management functions. This allows

the load to be distributed to each local processor, which greatly reduces system-bus bandwidth.

An intelligent DMA interface provides a high-speed transfer mechanism between the processor’s

local memory and PCI address space. The architecture also provides SSRAM and SDRAM

support. In very high-performance applications, part of the memory can be allocated to SSRAM.

Up to 128 Mbytes of addressable memory can be used for packet buffering. The packet-buffer

memory can be at the PCI bus or the local-memory bus.

Datasheet

11

IXF6401 Broadband Access Processor

:

Table 1. Control Structure Memory Requirement

Max Size

Total

Byte Length Total Memory

Description

Where Kept^†

Each

Required

Rc VC descriptor memory for 8 K VC

Tx VC descriptor memory for 8 K VC

2¹³

64

512 Kbytes

LM only

Maximum Tx packet buffer descriptor for

64 K pointers

2¹⁶

16

1 Mbyte

LM only

Maximum Rc report ring for 16 K entry

Maximum Tx report ring for 16 K entry

Maximum OEM cell ring for 1 K entry

Maximum RM cell ring for 1 K entry

2¹⁴

2¹⁰

8

128 Kbytes

64 Kbytes

LM or PCI

64

†

LM – Local memory consists of either all SDRAM, all SSRAM, or the combination of those two.

12

Datasheet

IXF6401 Broadband Access Processor

2.0

Pinout Information

2.1

IXF6401 Broadband Access Processor Ball Pinout

Figure 5. IXF6401 Processor Ball Configuration

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA AB AC AD AE AF

TXCLAV TXCLAV

BTXDATA BTXDATA BTXDATA BTXDATA BRCDATA BRCDATA

BRCDATA RCCLAV RCADDR

[0] [2] [1]

DIS_

ALL#

PCI_AD

[27]

PCI_AD

[24]

1

2

3

4

GND

TXEN#

RCCLK GND

GND

RCEN#

TCK

TDO

GND

VCC

GND

1

2

3

4

NC

[3]

[0]TPA

[14]

[10]

[6]

[3]

[15]

[12]

BTXDATA BRCDATA BRCDATA BRCDATA BRCDATA BRCDATA RCCLAV RCADDR RCADDR

PCI_AD

[25]

TXCLAV TXADDR BTXDATA BTXDATA BTXDATA BTXDATA

[1]

GND

VCC

GND

TMS

TDI

TRST#

GND

VCC

NC

[1]

[13]

[9]

[7]

[4]

[1]

[3]

[2]

[0]

[15]

[11]

[7]

[4]

LM_IRL

[0]

TXCLAV TXADDR

[2]

BTXDATA BTXDATA BTXDATA BTXDATA BRCDATA BRCDATA BRCDATA BRCDATA BRCDATA RCSOC/ RCCLAV

PCI_

INT#

PCI_

RST#

PCI_

REQ#

PCI_AD PCI_AD PCI_AD

PCI_AD

[23]

VCC

TXPRTY

[1]

[12]

[8]

[5]

[2]

[14]

[10]

[8]

[5]

[2]

RSOP

[0]/RPA

[30]

[28]

[26]

PCI_

IDSEL#

LM_SA

[2]

LM_IRL

[1]

TXADDR

[2]

BTXDATA BTXDATA

BTXDATA BRCDATA

[0] [11]

BRCDATA BRCDATA

RCCLAV

[1]

PCI_

GNT#

PCI_AD PCI_AD

PCI_AD

[22]

TXSOC

/TSOP

PCI_CBE

#[3]

EXT_CLK VCC

LM_

VCC

TXCLK

VCC

RCPRTY

VCC PCI_CLK

VCC

[13]

[9]

[6]

[3]

[31]

[29]

LM_SA

[3]

PCI_AD PCI_AD

[21] [20]

PCI_AD PCI_AD

[19]

5

6

TEOP

5

NC

ROMCS#

[18]

PCI_

LM_A

[2]

LM_SA

[4]

RMOD

[1]

LM_IRL

[2]

PCI_AD PCI_AD PCI_CBE

FRAME#

6

[17]

[16]

#[2]

PCI_

IRDY#

PCI_

TRDY#

PCI_

STOP#

TMOD

[1]

LM_SA

[6]

RMOD

[0]

LM_SA

[5]

PCI_DEV

SEL#

7

PCI_

PERR#

PCI_

SERR#

PCI_

PARITY

LM_A

[4]

TMOD

[0]

LM_A

[3]

PCI_CBE

#[1]

8

REOP

VCC

PCI_AD PCI_AD PCI_AD

[15] [14] [13]

LM_A

[7]

LM_A

[6]

LM_A

[5]

9

VCC

LM_A

[10]

LM_A

[9]

LM_A

[8]

PCI_AD PCI_AD

[12] [11]

PCI_AD PCI_AD

[10] [9]

10

LM_CS#

PKT_

BUSY

CPUDMA LM_A

LM_A

[11]

PCI_AD PCI_CBE PCI_AD PCI_AD

[8] #[0] [7] [6]

11

12

13

11

12

13

_BUSY

[12]

LM_A

[16]

LM_A

[15]

LM_A

[14]

LM_A

[13]

PCI_AD PCI_AD

IXF6401

EBGA352

[5]

[4]

[3]

[2]

LM_A

[17]

PCI_AD PCI_AD

[1] [0]

GND

LM_CLK

RERR

VCC

GND

VCC

LM_A

[19]

LM_A

[18]

PCI_

ACK64#

PCI_REQ PCI_CBE

14

15

16

17

18

19

20

21

GND

14

15

16

17

18

19

20

21

64#

#[7]

LM_A

[23]

LM_A

[22]

LM_A

[21]

LM_A

[20]

PCI_CBE PCI_CBE PCI_CBE PCI_AD

#[6] #[5] #[4] [63]

Bottom View

LM_A

[25]

LM_A

[24]

PCI_AD PCI_AD PCI_AD PCI_AD

[62] [61] [60] [59]

LM_RD# LM_WR#

PCI_AD PCI_AD PCI_AD PCI_AD

LM_D

[1]

LM_D

[0]

SSRAM LM_WE#

CS#[0]

[58]

[57]

[56]

[55]

[0]

LM_D

[4]

LM_D

[3]

LM_D

[2]

PCI_AD PCI_AD PCI_AD

[54] [53] [52]

VCC

LM_WE#

[1]

LM_D

[7]

LM_D

[6]

LM_D

[5]

PCI_AD PCI_AD PCI_AD PCI_AD

[51] [50] [49] [48]

LM_D

[10]

LM_D

[9]

LM_D

[8]

SSRAM

CS#[1]

PCI_AD PCI_AD

[47] [46]

PCI_AD PCI_AD

[45]

[44]

PCI_AD PCI_AD PCI_AD

[43] [42] [41]

LM_D

[13]

SSRAM

CS#[2]

LM_D

[12]

LM_D

[11]

NC

LM_WE#

[2]

LM_D

[15]

LM_D

[14]

PCI_AD PCI_AD PCI_AD PCI_AD

22

23

24

22

23

24

NC

[40]

[39]

[38]

[37]

LM_

VCC

LM_D

[57]

LM_D

[61]

LM_

BWAIT#

PCI_AD PCI_AD

LM_D

[17]

LM_D

[16]

LM_D

[22]

LM_WE

#[3]

LM_D

[26]

LM_D

[30]

LM_D

[33]

LM_D

[37]

LM_RAS

#[1]

LM_D

[41]

LM_D LM_CAS

LM_D

[50]

RVAL

VCC

NC

VCC

NC

RAS#[3]

[36]

[35]

[46]

#[2]

LM_

BACK#

PCI_AD

[34]

LM_D

[18]

LM_D

[23]

LM_D

[27]

LM_D

[31]

LM_CAS

#[0]

LM_D

[34]

LM_D

[38]

LM_CAS

#[1]

LM_D

[42]

LM_D

[44]

LM_D

[47]

SDRAM

CS#[2]

LM_D

[51]

LM_D

[54]

LM_CAS

#[3]

LM_D

[58]

LM_D

[62]

VCC

GND

VCC

GND

B

VCC

GND

NC

PCI_

PARITY

64

SDRAM

CS#[3]

LM_D

[59]

LM_D

[63]

LM_

BREQ#

LM_D

[20]

SSRAM

CS#[3]

LM_D

[28]

LM_WE

#[4]

SDRAM

CS#[0]

LM_D

[35]

LM_D

[39]

SDRAM

CS#[1]

LM_D

[43]

LM_D

[45]

LM_WE

#[6]

LM_D

[48]

LM_D

[52]

LM_D

[55]

25

26

GND

A

25

26

NC

VCC

GND

OLM_

CLK

LM_D

[19]

LM_D

[21]

LM_D

[24]

LM_D

[25]

LM_D

[29]

LM_RAS

#[0]

LM_D

[32]

LM_D

[36]

LM_WE

#[5]

LM_D

[40]

LM_RAS

#[2]

LM_D

[49]

LM_D

[53]

LM_WE

#[7]

LM_D

[56]

LM_D

[60]

LM_

BREL#

PCI_AD PCI_AD

[32] [33]

GND

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA AB AC AD AE AF

Notes:

VCC

Clock Input Pin

Ground Pin

CLK

NC

Power Pin [+3V]

GND

No Connect

A8275-01

Datasheet

13

IXF6401 Broadband Access Processor

2.2

Pin and Signal-Name Cross References

This section contains the tables listed below.

• Table 1, “PCI Bus Signals” on page 14 — Alphabetical list of PCI bus signals, by signal name,

that shows pin locations

• Table 2, “Local Memory Bus Signals” on page 15 — Alphabetical list of local-memory bus

signals, by signal name, that shows pin locations

• Table 3, “UTOPIA/POS Bus Signals” on page 15 — Alphabetical list of UTOPIA/POS bus

signals, by signal name, that shows pin locations

• Table 4, “JTAG Signals” on page 16 — Alphabetical list of JTAG signals, by signal name, that

shows pin locations

• Table 5, “Miscellaneous Signals” on page 16 — List of general-use signals, pins used for

power and ground, and pins reserved for ground or power, respectively, including their pin

locations

• Table 6, “Signal Descriptions” on page 17 — Alphabetical list of signal names that provides

descriptions

The “pin locations” given in the following tables refer to the grid location of the pin, as shown in

Figure 5, “IXF6401 Processor Ball Configuration” on page 13.

Table 1. PCI Bus Signals (Sheet 1 of 2)

Signal Name

Pin Locations

PCI_ACK64#

PCI_AD[63:0]

AC14

AF15, AC16, AD16, AE16, AF16, AC17, AD17, AE17, AF17, AD18, AE18, AF18,

AC19, AD19, AE19, AF19, AC20, AD20, AE20, AF20, AC21, AD21, AE21, AC22,

AD22, AE22, AF22, AE23, AF23, AF24, AD26, AC26, AA4, AA3, AB4, AB3, AB1,

AC3, AC2, AD1, AF3, AF4, AC5, AD5, AE5, AF5, AC6, AD6, AD9, AE9, AF9, AC10,

AD10, AE10, AF10, AC11, AE11, AF11, AC12, AD12, AE12, AF12, AD13, AE13

PCI_CBE#[7:0]

PCI_CLK

AE14, AC15, AD15, AE15, AD4, AE6, AF8, AD11

W4

PCI_DEVSEL#

PCI_FRAME#

PCI_GNT#

AE7

AF6

Y4

PCI_IDSEL#

PCI_INT#

AE4

V3

PCI_IRDY#

PCI_PARITY

PCI_PARITY64

PCI_PERR#

PCI_REQ#

AC7

AE8

AC25

AC8

Y3

PCI_REQ64#

PCI_RST#

AD14

W3

PCI_SERR#

PCI_STOP#

AD8

AF7

14

Datasheet

IXF6401 Broadband Access Processor

Table 1. PCI Bus Signals (Sheet 2 of 2)

Signal Name

Pin Locations

PCI_TRDY#

AD7

Table 2. Local Memory Bus Signals

Signal Name

Pin Locations

C16, D16, A15, B15, C15, D15, B14, C14, B13, A12, B12, C12, D12, C11, D11, A10,

B10, D10, A9, B9, C9, A8, C8, A6^†

LM_A[25:2]

LM_D[63:0]

AA25, AA24, AA23, Y26, Y25, Y24, Y23, W26, V25, V24, U26, U25, U24, U23, T26,

T25, R24, R23, P25, P24, N25, N24, N23, M26, L25, L24, L23, K26, K25, K24, K23,

J26, H24, H23, G26, G25, G24, G23, F26, E26, E24, E23, D26, D25, C26, A24, B23,

C23, C22, D22, A21, C21, D21, A20, B20, C20, B19, C19, D19, A18, B18, C18, A17,

B17

LM_BACK#

LM_BREL#

LM_BREQ#

LM_BWAIT#

LM_CAS#[3:0]

LM_CLK

AB24

AA26

AB25

AB23

W24, T23, M24, J24

C13

LM_CS#

C10

LM_IRL[2:0]

LM_RAS#[3:0]

LM_RD#

D6, B4, A3

W23, R26, M23, H26

A16

LM_ROMCS#

LM_SA[6:3]

LM_SA[2]

C5

B7, D7, B6, A5

A4^††

LM_WE#[7:0]

LM_WR#

V26, R25, L26, H25, F23, A22, A19, D17

B16

OLM_CLK

AB26

SDRAMCS#[3:0]

SSRAMCS#[3:0]

W25, T24, M25, J25

F25, B21, D20, C17

†

LM_A[2] (or Pin A6) is not used and must be pulled low.

†† LM_SA[2] is not used. Keep this signal no connect.

Table 3. UTOPIA/POS Bus Signals (Sheet 1 of 2)

Signal Name

Pin Locations

RCDATA[15:0]

TXDATA[15:0]

RCADDR[2:0]

RCCLAV [0]/RPA

RCCLAV[3:1]

K1, L3, L2, L1, M4, M3, M2, N3, N2, P4, P3, P2, R4, R3, R2, R1

F2, F1, G4, G3, G2, G1, H4, H3, H2, H1, J3, J2, J1, K3, K2, L4

U2, U1, V2

U3

T2, T1, U4

Datasheet

15

IXF6401 Broadband Access Processor

Table 3. UTOPIA/POS Bus Signals (Sheet 2 of 2)

Signal Name

Pin Locations

RCCLK

RCEN#

M1

V1

RCPRTY

RCSOC/RSOP

REOP

T4

T3

D8

RERR

D13

RMOD[0]

RMOD[1]

RVAL

C7

C6

A23

TEOP

D5

TMOD[0]

TMOD[1]

TXADDR[2:0]

TXCLAV[0]TPA

TXCLAV[3:1]

TXCLK

B8

A7

E4, E3, E2

D1

C1, D3, D2

K4

E1

F3

F4

TXEN#

TXPRTY

TXSOC/TSOP

Table 4. JTAG Signals

Signal Name

Pin Locations

TCK

TDI

Y1

Y2

TDO

AA1

W2

AA2

TMS

TRST#

Table 5. Miscellaneous Signals (Sheet 1 of 2)

Signal Name

Pin Locations

General-Use Signals

CPUDMA_BUSY

DIS_ALL#

B11

W1

C4

EXT_CLK

PKT_BUSY

A11

16

Datasheet

IXF6401 Broadband Access Processor

Table 5. Miscellaneous Signals (Sheet 2 of 2)

Signal Name

Pin Locations

Power Pins

B2, B25, C3, C24, D4, D9, D14, D18, D23, J4, J23, N4, P23, V4, V23, AC4, AC9,

AC13, AC18, AC23, AD3, AD24, AE2, AE25

VCC

Ground Pins

A1, A2, A13, A14, A25, A26, B1, B3, B24, B26, C2, C25, N1, N26, P1, P26, AD2,

AD25, AE1, AE3, AE24, AE26, AF1, AF2, AF13, AF14, AF25, AF26

GND

NC

No-Connect Pins

B5, B22, D24, E25, F24, AB2, AC1, AC24, AD23, AF21

Table 6. Signal Descriptions (Sheet 1 of 6)

Input (I)

Signal Name

Description

Output (O)

CPUDMA_BUSY

DIS_ALL#

O

I

DMA Queue Full.

Disable All. This signal disables all output and three-state signals. For normal operation, this

signal should be high.

EXT_CLK

GND

I

External Clock. This clock can be used as an external clock source for the traffic shaper.

Ground.

Local Bus Address. Using the 16-MByte Micron device as an example (MT48LC1M16A1),

the SDRAM row address is selected by LM_A[13:3]. The SDRAM column address is

represented by LM_A[10:3] because this device has 11 row addresses and eight column

addresses. During SSRAM operation, a new address is presented on every clock, if

SSRAMCS# is asserted. When the external master is performing a slave transaction, it must

hold the address until LM_BWAIT# is deasserted.

LM_A[25:3]

LM_A[2]

I/O

LM_A[2] (or Pin A6) is not used and must be pulled low.

Local Bus Acknowledge. This is the grant signal to the IXF6401 processor bus request. It

should remain asserted throughout the transaction. To optimize the performance of the chip,

external logic can assert this signal all the time. If an external master is present, however,

external logic needs to deassert this signal only when the external master requires the bus

by asserting LM_BREL# and LM_BREQ# is deasserted by the IXF6401 processor. After

LM_BACK# is deasserted, it must remain deasserted until the external master has

completed the transaction.

LM_BACK#

LM_BREL#

LM_BREQ#

I

Local Bus Release. The external master asserts this signal to indicate that it intends to use

the local bus. It deasserts this signal once it detects that LM_BREQ# is deasserted. To

improve performance, the external master should not assert this signal until there is a

transaction waiting to be performed.

I

Local Bus Request. When asserted, this signal indicates that the IXF6401 processor wants

to access the local bus. Once it is asserted, it remains asserted until the external master

asserts LM_BREL#. If the IXF6401 processor is idle when LM_BREL# is asserted, the

IXF6401 processor deasserts LM_BREQ# in the next clock cycle. If the IXF6401 processor

is not idle when LM_BREL# is asserted, the processor deasserts LM_BREQ# two cycles

after it finishes the current transaction. The IXF6401 processor deasserts this signal for only

one cycle.

O

Local Bus External Master Wait. During slave access, after the external master asserts

LM_CS#, the IXF6401 processor asserts this signal when it is not ready for a data

transaction. The IXF6401 processor removes LM_BWAIT# when it is ready for transaction.

During slave read access, the data on the local bus is valid the cycle AFTER LM_BWAIT# is

deasserted. The external master must hold the data until one cycle after this signal is

deasserted, during a slave-write transaction.

LM_BWAIT#

O

Datasheet

17

IXF6401 Broadband Access Processor

Table 6. Signal Descriptions (Sheet 2 of 6)

Input (I)

Signal Name

Description

Output (O)

Local Bus SDRAM Column Address Strobe Command. When this signal and SDRAMCS#

are both asserted while LM_RAS# is deasserted, the column address is selected. The

signals remain asserted until the transaction has completed. These signals also are

asserted for one cycle during either refresh or mode set. The signals should be connected

directly to CAS# of a SDRAM. They are input and shaped during slave external master

access of the local SDRAM.

LM_CAS#[3:0]

I/O

Local Bus Clock. This is the master clock for the local memory bus and the IXF6401

processor.

LM_CLK

LM_CS#

I

Local Memory Chip Select. When asserted, the host processor wants to access the

processor’s internal memory and registers.

Local Bus Data. Output during master write or slave read. Input when master read or slave

write. When writing to SSRAM or SDRAM, data is valid on every clock, provided any of the

memory chip enables are asserted. During SSRAM read access, data is valid one cycle

after SSRAMCS# is asserted. Therefore, the first cycle after SSRAMCS# is deasserted,

data is still valid. When reading from SDRAM, depending on the CAS latency value, data

could be valid three clock cycles after SDRAMCS# is asserted. As a result, data could still

be valid for three cycles after SDRAMCS# has been removed. Data is invalid in all other

cycles when the IXF6401 processor is in master mode. During slave write, the external

device must put the valid data on the data bus in the same cycle that it asserts LM_CS#,

and the value of the data must be held for one cycle after LM_BWAIT# is deasserted. During

slave read, data is valid one cycle after LM_BWAIT# is deasserted, and it is held until

LM_CS# is deasserted by the external device.

LM_D[63:0]

I/O

Local Bus Interrupt. LM_IRL[0] is asserted when any bit in the Error Interrupt register is set.

LM_IRL[1] is set when any bit in the Status Interrupt register is asserted. LM_IRL[2] is set

when any bit in the Status[2:0] register is set.

LM_IRL[2:0]

O

Local Bus SDRAM Row Address Strobe Command. When this signal and SDRAMCS# are

asserted, the row address is selected.

LM_RAS#[3:0]

I/O

Local Bus Read. Asserted when the current transaction performed by the IXF6401

processor is a read instruction to SSRAM. It has the same timing as SSRAMCS#. Please

notice that this signal is not used when a master read from SDRAM is performed. This signal

is asserted by the external master during a slave read transaction, and external logic should

hold the signal until the IXF6401 processor deasserts lM_WAIT#.

LM_RD#

I/O

O

Local Bus Expansion ROM Chip Select. If ROM is present, this signal will be asserted

during the booting process. PCI Master Access Expansion ROM. Only 16-bit EEPROM is

supported by the IXF6401 processor and it should be connected to LM_A[18:3] and

LM_D[63:48].

LM_ROMCS#

Local Bus Spare Memory Address. When LM_A[6:3] is used for SDRAM. The LM_SA[6:3]

should be used for SSRAM or vice-versa. This signal has the same timing as LM_A. Instead

of becoming input during a slave access, however, these pins will be tristated.

LM_SA[6:3]

LM_SA[2]

O

LM_SA[2] is not used. Keep this signal no connect.

18

Datasheet

IXF6401 Broadband Access Processor

Table 6. Signal Descriptions (Sheet 3 of 6)

Input (I)

Signal Name

Description

Output (O)

Local Bus Write Enable. Output during master read/write and input during slave read/write.

LM_WE#[7] controls LM_D[63:56].

LM_WE#[6] controls LM_D[55:48].

LM_WE#[5] controls LM_D[47:40].

LM_WE#[4] controls LM_D[39:32].

LM_WE#[3] controls LM_D[31:24].

LM_WE#[7:0]

I/O

LM_WE#[2] controls LM_D[23:16].

LM_WE#[1] controls LM_D[15:8].

LM_WE#[0] controls LM_D[7:0].

LM_WE#[2 i] and LM_WE#[2 i+1] should be connected to DQML and DQMU of the SDRAM,

respectively, where i is 0 to 3. When connected to SSRAM, LM_WE#[i] should be connected

to BWi#. LM_WE# has the same timing as local memory chip select when the IXF6401

processor is performing a master write.

Local Bus Write. Asserted when the IXF6401 processor accesses SDRAM. It has the same

timing as SDRAMCS#. This signal is not asserted during a master write to SSRAM. During

slave access, the external master asserts LM_WR# to indicate a write access. The external

logic should hold the signal until the IXF6401 processor deasserts lM_WAIT#.

LM_WR#

I/O

NC

—

No connect.

OLM_CLK

O

Local Memory Clock Output.

PCI Bus Acknowledge 64-bit. When asserted, this signal indicates the target is willing to

transfer data using 64 bits.

PCI_ACK64#

PCI_AD[63:0]

I/O

PCI Bus Multiplexed 64-bit Address/Data. During a data phase, the upper 32 bits are

meaningful when both PCI_REQ64# and PCI_ACK# are asserted. During the address

phase, only the lower 32 bits are used.

PCI Bus Command and Byte Enable. During an address phase, PCI_CBE# represents a

PCI-bus command. During a data phase, it represents a byte enable.

PCI_CBE#[7:0]

PCI_CLK

I/O

I

PCI Bus Clock. Up to 66 MHz.

PCI Bus Device Select. When driven, this signal indicates that the driving device has

decoded its address as the target of the current access.

PCI_DEVSEL#

I/O

PCI Bus Cycle Frame. This signal is driven by the bus master to indicate the start and end of

a transaction.

PCI_FRAME#

PCI_GNT#

PCI_IDSEL#

PCI_INT#

I/O

I

PCI Bus Grant for the IXF6401 processor.

PCI Bus Initialization Device Select. This signal is used as a chip select during configuration

read and write transactions.

I

O

I/O

PCI Bus Interrupt Signal. This signal should be connected to INTA# of the PCI connector.

PCI Bus Initiator Ready. When asserted, the bus master is ready to complete the current

data phase.

PCI_IRDY#

PCI_PARITY

I/O

PCI Bus Parity Bit. Sets even parity across PCI_AD[31:0] and PCI_C/BE#[3:0].

PCI_PARITY64

PCI Bus Parity Double Word. Sets even parity across PCI_AD[63:32] and PCI_C/BE#[7:4].

PCI Bus Parity Error. This bit is only used for reporting data parity errors during all PCI

transactions, except for a Special Cycle.

PCI_PERR#

PCI_REQ#

I/O

O

PCI Bus Request. The IXF6401 processor asserts this signal when it is trying to access the

PCI bus.

PCI_REQ64#

PCI_RST#

I/O

I

PCI Bus Request 64-bit Transfer. When asserted, this signal indicates a 64-bit transaction.

PCI Bus Reset. This is the master reset signal for the IXF6401 processor.

Datasheet

19

IXF6401 Broadband Access Processor

Table 6. Signal Descriptions (Sheet 4 of 6)

Input (I)

Signal Name

Description

Output (O)

PCI Bus System Error. This signal is used to report address parity errors, data parity on the

Special Cycle command, or any other system error where the result will be catastrophic.

PCI_SERR# is an open drain signal.

PCI_SERR#

O

PCI Bus Stop. The PCI target asserts this signal to request the bus master to stop the

current transaction.

PCI_STOP#

PCI_TRDY#

I/O

PCI Bus Target Ready. This signal is driven by the target to indicate its ability to complete

current data phase.

Packet Processor Busy. The purpose of this pin is to help external hardware to keep track of

whether the IXF6401 processor’s four-entry Transmit_ADD_PKT_QUEUE and two-entry

ADD_BUFFER_QUEUE are available to accept another command.

PKT_BUSY

O

UTOPIA Bus Receive MPHY Address. When address polling is enabled, these signals are

the Receive MPHY address. When polling is disabled, these signals are used as

RxEn#[3:1].

RCADDR[2:0]

ATM: RCCLAV-UTOPIA Bus Receive Cell Available. When asserted, MPHY is ready to

transfer a complete cell.

RCCLAV [0]/RPA

I

POS: Receive Packet Available. When high, indicates the POS framer has at least one

packet.

UTOPIA Bus Receive Cell Available. When asserted, MPHY is ready to transfer a complete

cell.

RCCLAV[3:1]

RCCLK

I

UTOPIA Bus Receive Clock. This is the UTOPIA-bus receive clock.

UTOPIA/POS Receive Data. This bus carries valid ATM cell or POS packet data, when

RCEN# is asserted.

RCDATA[15:0]

I/O

In 16-bit or 8-bit mode, RCDATA is input only for receive data.

In 32-bit mode with receive only, RCDATA will represent receive data [15:0] and TXDATA

will represent receive data [31:16].

UTOPIA Bus Receive Enable. When asserted, indicates that the IXF6401 processor is

ready to accept an ATM cell in the following cycles.

RCEN#

O

I

UTOPIA/POS Receive Data Parity. RCPRTY serves as the odd parity over RCDATA on

8/16-bit mode or RCDATA and TXDATA on 32-bit mode.

RCPRTY

ATM: RCSOC-UTOPIA Bus Receive Start of Cell. This signal indicates the current data on

RCDATA is the beginning of a new ATM cell.

RCSOC/RSOP

I

POS: RSOP-Receive Start Of Packet. When high, indicates the beginning of the packet with

RCEN# asserted.

Receive End Of Packet. REOP is valid only when RCEN# is asserted. In ATM mode, this pin

must be pulled down.

REOP

RERR

I

Receive Error. Indicates the packet is not valid due to error(s). In ATM mode, this pin must

be pulled down.

Receive module indicates the valid bytes.

In the data bus when REOP is asserted.

00 — DATA [31:0] valid

RMOD[1]

RMOD[0]

I

01 — DATA [31:8] valid

10 — DATA [31:16] valid

11 — DATA [31:24] valid

In ATM mode, these pins must be pulled low.

Receive Data Valid. When high, all receive controls and data are valid. In ATM mode, this

pin must be pulled up.

RVAL

I

20

Datasheet

IXF6401 Broadband Access Processor

Table 6. Signal Descriptions (Sheet 5 of 6)

Input (I)

Signal Name

Description

Output (O)

Local Bus SDRAM Chip Select. When asserted, the IXF6401 processor wants to access

SDRAM. These signals are asserted two cycles after LM_BACK# is asserted, if there is a

transaction pending. They remain asserted until the burst transaction has completed. When

these signals are deasserted at the end of the read cycle, it does not mean the data is

invalid from then on. These signals are for flow-through only. See “LM_D[63:0]” on page 15

for more information.

SDRAMCS#[3:0]

SSRAMCS#[3:0]

I/O

Local Bus SSRAM Chip Select. When asserted, the IXF6401 processor wants to access

SSRAM. These signals should be connected to CS# of the SSRAMs. Since the processor

generates its own burst addresses, ADSP# should be pulled up to high and ADSC# and

ADV# should be pulled down to GND. These signals are asserted two cycles after

LM_BACK is asserted if there is a transaction pending. They remain asserted until the burst

transaction has completed. When these signals are deasserted at the end of the read cycle,

it does not mean the data is invalid from then on. See “LM_D[63:0]” on page 15 for more

information.

TCK

TDI

I

JTAG Input Clock.

JTAG Data Input.

JTAG Data Output.

TDO

O

Transmit End Of Packet. TEOP is valid only when TXEN# is asserted. In ATM mode, this pin

is no connect.

TEOP

O

Transmit Module. Indicates the valid bytes in the data bus when TEOP is asserted.

00 — DATA [31:0] valid

TMOD[1]

TMOD[0]

O

01 — DATA [31:8] valid

10 — DATA [31:16] valid

11 — DATA [31:24] valid

In ATM mode, these pins are no connect.

TMS

I

JTAG Test Mode Select. Controls the state of the TAP controller in the device.

JTAG Test Reset. This will reset the TAP controller.

TRST#

UTOPIA Bus Transmit MPHY Address. When address polling is enabled, these signals are

the MPHY address. When address polling is disabled, these signals are used as

TXEN#[3:1].

TXADDR[2:0]

O

ATM: UTOPIA Bus Transmit Cell Available. When asserted, this signal indicates that MPHY

is ready to accept the transfer of a complete cell.

TXCLAV[0]TPA

I

POS: Transmit Packet Available (TPA). When high, indicates the POS framer is ready to

take data. When low, indicates the POS framer transmit fifo is full or near full and the

IXF6401 processor needs to stop transmitting data.

UTOPIA Bus Transmit Cell Available. When asserted, this signal indicates that MPHY is

ready to accept the transfer of a complete cell.

TXCLAV[3:1]

TXCLK

I

UTOPIA Bus Transmit Clock. This signal is the UTOPIA bus transmit clock.

UTOPIA/POS transmit data. This bus carries valid ATM cell or POS packet data when

TXEN# is asserted.

TXDATA[15:0]

I/O

In 16-bit or 8-bit mode, TXDATA is output only for transmit data.

In 32-bit mode with transmit only, TXDATA will represent transmit data [15:0] and RCDATA

will represent transmit data [31:16].

Datasheet

21

IXF6401 Broadband Access Processor

Table 6. Signal Descriptions (Sheet 6 of 6)

Input (I)

Signal Name

Description

Output (O)

Transmit Enable.

ATM- When asserted, this signal indicates that the current cycle contains a valid packet

data.

TXEN#

O

UTOPIA Bus Transmit Enable. When asserted, this signal indicates that the current cycle

contains a valid ATM cell.

UTOPIA/POS Transmit Data Parity. TXPRTY serves as the odd parity bit over TXDATA, on

8/16-bit mode, or RCDATA and TXDATA, on 32-bit mode. When FPE (Force Parity Error) is

set in the UTOPIA Control register, the IXF6401 processor asserts even parity on this pin.

TXPRTY

ATM: TXSOC- UTOPIA Bus Transmit Start of Cell. When asserted, this signal indicates that

the current data on TXDATA is the beginning of a new ATM cell.

TXSOC/TSOP

VCC

O

I

POS: TSOP-Transmit start of packet. When high, indicates the beginning of the packet

when TXEN# is asserted.

Power, 3.3 V.

22

Datasheet

IXF6401 Broadband Access Processor

3.0

Bus-Interface Information

This section provides overview information about the IXF6401 Broadband Access Processor’s

following bus interfaces:

• PCI Interface — See page 23.

• Local-Memory Interface — See page 24.

• UTOPIA Interface — See page 28.

3.1

PCI Interface

The IXF6401 processor’s default clock speed and bus width are 66 MHz and 64-bit. The

processor’s addressing is always 32-bit. Table 7 lists the other supported clock speeds and bus

widths.

Table 7. Supported Clock Speeds and Bus Widths

Clock Speed

Bus Width

33 MHz

66 MHz

32-bit^†

64-bit

32-bit^†

64-bit

†

To use the 32-bit mode, set System Control

Register bit (W_B[25]) to 1.

The configuration cycle/mechanism supported by the processor is: Configuration Mechanism #1,

Type 0.

PCI command and cycles to which the processor responds are shown in Table 8.

Table 8. PCI Commands and Cycles

PCI_CBE# [3:0] Bits

Command

PCI Specification

0110

0111

1010

1011

Memory Read

Memory Write

PCI 2.1, page 36

PCI 2.1, page 37

Configuration Read

Configuration Write

PCI 2.1, pages 84 - 86

Datasheet

23

IXF6401 Broadband Access Processor

The PCI interface has the following special features:

• Burst length and order — In Master mode, 64 bytes at a time.

• Retry, Disconnect, and Target-Abort — All are supported. (See the PCI 2.1 specification,

pages 43 - 47.)

Note: Combining, merging, and collapsing are not supported.

Slave and Master operation are supported by the IXF6401 processor. For master operation:

• You need to include an arbitration protocol that uses PCI_CLK, PCI_REQ#, PCI_GNT#,

PCI_FRAME#, and PCI_AD[63:0]. (See the PCI 2.1 specification, page 57.)

• Fast back-to-back transaction — The just-cited signals are used in conjunction with

PCI_IRDY# and PCI_TRDY#. (For a timing diagram, see the PCI 2.1 specification, page 61.)

3.2

Local-Memory Interface

3.2.1

General Features

The local-memory interface for the processor always operates in the 64-bit mode at 66 MHz. There

is no parity check.

The processor can address up to 256 MBytes of memory space — split between SSRAM (128

Mbytes) and SDRAM (128 Mbytes). Flow through and pipelined SSRAM can be used. The

IXF6401 processor always will perform as SDRAM auto-refresh.

Memory access transaction used:

• Size — Bursts can be one-byte, two-byte, four-byte, eight-byte, and linear eight-byte bursts up

to 64 bytes per access.

• SDRAM refresh — The IXF6401 processor always provides the address, but it does not have

an internal counter to auto-increment the address.

For detailed SSRAM and SDRAM timing information, see the manufacturer’s specifications.

3.2.2

Arbitration

The IXF6401 processor does not have a local-memory-bus, on-chip arbiter or a PCI-bus arbiter.

The local-memory-bus arbitration is shown in Figure 6.

The PCI arbitration is performed according to PCI specifications.

24

Datasheet

IXF6401 Broadband Access Processor

Figure 6. Local-Memory Arbitration Timing

LM_CLK

IXF6401 drives

LM_BREQ#

Arbiter drives

LM_BACK#

Arbiter drives

LM_BREL#

IXF6401 owns the LM bus

LM bus ownership turn around cycle

Other device owns the LM bus

A8730-01

NOTES:

1. For the processor or host to gain the local bus, the device first must assert either LM_BREQ# or LM_BREL#.

2. The device must wait for LM_BACK# to be asserted and then can start bus operations.

3. The bus request must remain active for the duration of the operation.

4. The bus request should return to inactive at the end of the operation. If the device’s grant is removed, it must

remain inactive for at least two clock cycles.

5. After detecting the desertion of the bus request of a current bus owner, the external arbitrator will rearbitrate

the bus.

6. The bus is granted to the next candidate on a first-come, first-served, round-robin basis.

7. To share the bus bandwidth, limit bursts to less than 64 bytes per transaction.

8. To access the IXF6401 processor’s internal registers and on-chip RAM/CAM from the local memory bus, the

local-memory-bus CPU asserts the LM_CS# pin after it gains ownership of the bus.

9. For more details on bus timing, see “Local Memory Bus Timing” on page 47.

10.For an illustration of the recommended local-memory clock circuitry, see Table 35 on page 47.

3.2.3

Local Memory Configuration

For information on configuring the local memory, refer to documentation on BIU Master Control

Register 1, in the IXF6401 Broadband Access Processor Developer’s Manual (273453).

3.2.3.1

SDRAM Configuration

For READ and WRITE SDRAM timing, refer to the memory manufacturer’s specification(s). The

following tables show the configuration settings for the Micron MT48LC8M16A2 SDRAM

module.

Table 9. Sample SDRAM Configuration: Bank 0 (Sheet 1 of 2)

IXF6401 Broadband Access Processor Pins

8 Mbits x 16 x 4 Chips

SDRAM Pins

CLK

CKE

CS#

LM_CLK^†

VCC

LM_CLK^†

VCC

LM_CLK^†

VCC

SDRAMCS0#

†

LM_CLK refers to the “delayed” LM_CLK signal. See Figure 20 on page 48.

Datasheet

25

IXF6401 Broadband Access Processor

Table 9. Sample SDRAM Configuration: Bank 0 (Sheet 2 of 2)

IXF6401 Broadband Access Processor Pins

8 Mbits x 16 x 4 Chips

SDRAM Pins

RAS#

CAS#

WE#

LM_RAS0#

LM_CAS0#

LM_WR#

LM_RAS0#

LM_CAS0#

LM_WR#

LM_RAS0#

LM_CAS0#

LM_WR#

LM_CAS0#

LM_WR#

DQML

DQMH

BA0

LM_WE0#

LM_WE1#

LM_A15

LM_WE2#

LM_WE3#

LM_A15

LM_WE4#

LM_WE5#

LM_A15

LM_WE6#

LM_WE7#

LM_A15

BA1

LM_A16

A[0:11]

DQ[0:15]

LM_A[3:14]

LM_D[0:15]

LM_A[3:14]

LM_D[16:31]

LM_A[3:14]

LM_D[32:47]

LM_A[3:14]

LM_D[48:63]

†

LM_CLK refers to the “delayed” LM_CLK signal. See Figure 20 on page 48.

Table 10. Sample SDRAM Configuration: Bank 1

IXF6401 Broadband Access Processor Pins

8 Mbits x 16 x 4 Chips

SDRAM Pins

CLK

CKE

LM_CLK^†

VCC

LM_CLK^†

VCC

LM_CLK^†

VCC

CS#

SDRAMCS1#

LM_RAS1#

LM_CAS1#

LM_WR#

SDRAMCS1#

LM_RAS1#

LM_CAS1#

LM_WR#

SDRAMCS1#

LM_RAS1#

LM_CAS1#

LM_WR#

SDRAMCS1#

LM_RAS1#

LM_CAS1#

LM_WR#

RAS#

CAS#

WE#

DQML

DQMH

BA0

LM_WE0#

LM_WE1#

LM_A15

LM_WE2#

LM_WE3#

LM_A15

LM_WE4#

LM_WE5#

LM_A15

LM_WE6#

LM_WE7#

LM_A15

BA1

LM_A16

A[0:11]

DQ[0:15]

LM_A[3:14]

LM_D[0:15]

LM_A[3:14]

LM_D[16:31]

LM_A[3:14]

LM_D[32:47]

LM_A[3:14]

LM_D[48:63]

†

LM_CLK refers to the “delayed” LM_CLK signal. See Figure 20 on page 48.

3.2.3.2

SSRAM Configuration

For READ and WRITE SSRAM timing, refer to the memory manufacturer’s specification(s). The

following tables show the configuration settings for the Micron SSRAM MT58L128L32F and

Flow-through Syncburst SRAM.

Note: Buffering may be required due to SSRAM load. Refer to the manufacturer’s load specification.

26

Datasheet

IXF6401 Broadband Access Processor

Table 11. Sample SSRAM Configuration: Banks 0 and 1

IXF6401 Broadband Access Processor Pins

SSRAM Pins

Bank 0 (128 Kbits x 32 x 2 Chips)

Bank 1 (128 Kbits x 32 x 2 Chips)

SA0

SA1

LM_SA3

LM_SA4

LM_SA[6:5]

LM_A[19:7]

GND

LM_SA3

LM_SA4

LM_SA[6:5]

LM_A[19:7]

GND

LM_SA3

LM_SA4

LM_SA[6:5]

LM_A[19:7]

GND

LM_SA3

LM_SA4

LM_SA[6:5]

LM_A[19:7]

GND

SA[3:2]

SA[16:4]

Mode

CLK

LM_CLK^†

ADV#

ADSC#

ADSP#

BWd#

BWc#

BWb#

BWa#

BWE#

GW#

GND

Pull-down

Pull-Up

Pull-down

Pull-Up

Pull-down

Pull-Up

Pull-down

Pull-Up

LM_WE3#

LM_WE2#

LM_WE1#

LM_WE0#

GND

LM_WE7#

LM_WE6#

LM_WE5#

LM_WE4#

GND

LM_WE3#

LM_WE2#

LM_WE1#

LM_WE0#

GND

LM_WE7#

LM_WE6#

LM_WE5#

LM_WE4#

GND

Pull-Up

CE#

SSRAMCS0#

GND

SSRAMCS0#

GND

SSRAMCS1#

GND

SSRAMCS1#

GND

CE2#

CE2

Pull-Up

OE#

LM_RD#

LM_D[0:31]

LM_RD#

LM_D[32:63]

LM_RD#

LM_D[0:31]

LM_RD#

LM_D[32:63]

DQa, b, c , d

†

LM_CLK refers to the “delayed” LM_CLK signal. See Figure 20 on page 48.

Table 12. Sample SSRAM Configuration: Banks 2 and 3 (Sheet 1 of 2)

IXF6401 Broadband Access Processor Pins

SSRAM Pins

Bank 2 (128 Kbits x 32 x 2 Chips)

Bank 3 (128 Kbits x 32 x 2 Chips)

SA0

SA1

LM_SA3

LM_SA4

LM_SA[6:5]

LM_A[19:7]

GND

LM_SA3

LM_SA4

LM_SA[6:5]

LM_A[19:7]

GND

LM_SA3

LM_SA4

LM_SA[6:5]

LM_A[19:7]

GND

LM_SA3

LM_SA4

LM_SA[6:5]

LM_A[19:7]

GND

SA[3:2]

SA[16:4]

Mode

CLK

LM_CLK^†

ADV#

ADSC#

GND

Pull-down

†

LM_CLK refers to the “delayed” LM_CLK signal. See Figure 20 on page 48.

Datasheet

27

IXF6401 Broadband Access Processor

Table 12. Sample SSRAM Configuration: Banks 2 and 3 (Sheet 2 of 2)

IXF6401 Broadband Access Processor Pins

SSRAM Pins

Bank 2 (128 Kbits x 32 x 2 Chips)

Bank 3 (128 Kbits x 32 x 2 Chips)

ADSP#

BWd#

BWc#

BWb#

BWa#

BWE#

GW#

Pull-Up

LM_WE3#

LM_WE2#

LM_WE1#

LM_WE0#

GND

Pull-Up

LM_WE7#

LM_WE6#

LM_WE5#

LM_WE4#

GND

Pull-Up

LM_WE3#

LM_WE2#

LM_WE1#

LM_WE0#

GND

Pull-Up

LM_WE7#

LM_WE6#

LM_WE5#

LM_WE4#

GND

Pull-Up

CE#

SSRAMCS2#

GND

SSRAMCS2#

GND

SSRAMCS3#

GND

SSRAMCS3#

GND

CE2#

CE2

Pull-Up

OE#

LM_RD#

LM_D[0:31]

LM_RD#

LM_D[32:63]

LM_RD#

LM_D[0:31]

LM_RD#

LM_D[32:63]

DQa, b, c , d

†

LM_CLK refers to the “delayed” LM_CLK signal. See Figure 20 on page 48.

3.3

UTOPIA Interface

For the Universal Test and Operations Interface for ATM (UTOPIA) interface, the supported clock

rate is 37.5 to 50 MHz, to meet the OC-12 (4 x OC-3) line rate.

UTOPIA levels support:

• Level 1 (8-bit)

• Level 2 (16-bit)

• Level 3 (32-bit)

— Full duplex requires two IXF6401 processors.

— If the IXF6401 processor is programmed for UTOPIA III receive-mode only, the

TXDATA signal will carry the upper word [31:16] of the receive data.

— If the IXF6401 processor is programmed for UTOPIA III transmit-mode only,

RCDATA[15:0] is the upper 16 bits of the transmit data.

For information on configuring the local memory, refer to documentation on UTOPIA Control

Register 1, in the IXF6401 Broadband Access Processor Developer’s Manual (273453).

3.3.1

UTOPIA I

In UTOPIA I (8-bit), 53 octet cells are transferred.

28

Datasheet

IXF6401 Broadband Access Processor

Table 13. UTOPIA-I Bit Settings

Transmit / Receive Time

Bit 7 .. Bit 0

Header 1

Header 2

Header 3

Header 4

UDF / HEC

Payload 1

...

Payload 48

3.3.2

UTOPIA II

In UTOPIA II (16-bit), 54 octet cells are transferred.

Table 14. UTOPIA-II Bit Settings

Transmit / Receive Time

Bit 15

Bit 0

Header 1

Header 3

UDF1-HEC

Payload 1

...

Header 2

Header 4

UDF2-HEC

Payload 2

...

Payload 47

Payload 48

3.3.3

UTOPIA III

In UTOPIA III (32-bit), 52 octet cells are transferred. There is no HEC support.

Table 15. UTOPIA-III Bit Settings

Transmit / Receive

Time

Bit 31 ...

... Bit 16

Bit 15 ...

... Bit 0

Header 1

Payload 1

Payload 5

...

Header 2

Payload 2

Payload 6

...

Header 3

Payload 3

Payload 7

...

Header 4

Payload 4

Payload 8

...

Payload 45

Payload 46

Payload 47

Payload 48

Datasheet

29

IXF6401 Broadband Access Processor

3.3.4

UTOPIA Modes

Table 16. UTOPIA Modes

UTOPIA Mode

IXF6401

IXF6402

Direct Status

Direct Mode

Support – Rev B

Not supported

Supported

Address Polling

Not Supported

3.3.5

POS Mode

IXF6401 processor can support either one OC-3 port or one OC-12 port in the POS mode.

30

Datasheet

IXF6401 Broadband Access Processor

4.0

Package Information

4.1

Mechanical Specifications

Figure 7. 352-Pin Ball Grid Array

C

D

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AAABACADAEAF

AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A

1

2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

C

D

e

Bottom View

Top View

A

Side View

Table 17. Mechanical Dimensions

Description

Parameter

Value

Units

Maximum Mounted Package Height

Ball Footprint

A

C

D

e

1.4

31.75

35 x 35

1.27

26 x 26

4

mm

Body Size

Ball Pitch

Ball Matrix

Number of Rows

Number of Columns

4

4.2

Thermal Specifications

The IXF6401 Broadband Access Processor consumes 6 W of power when operating at 66 MHz.

The processor’s thermal design power (TDP) level is given in Table 30, “Power Dissipation

Requirements for Thermal Design” on page 42.

Datasheet

31

IXF6401 Broadband Access Processor

The processor’s Enhanced Ball Grid Array (EBGA) package dissipates the majority of its heat into

the environment via the metal cap that is attached to the die.

To ensure proper operation and reliability of the IXF6401 processor, the thermal solution must

maintain the case temperature at or below the values specified in Table 18. Considering the power

dissipation levels and typical system ambient environment of 0° C to 70° C, system or component-

level thermal enhancements will be required if the case temperature exceeds the referenced table’s

maximum temperatures.

Table 18. EBGA Thermal Absolute Maximum Rating

Parameter

Maximum

T_case

85° C

Note: A heat sink is strongly recommended when the processor is operating at 66 MHz.

To dissipate the highest possible thermal power, good system airflow is critical. Airflow is

determined by the size and number of fans, vents and/or ducts along with the placement of these

elements, in relation to the components and the airflow channels within the system. Noise

constraints may limit the size and/or types of fans, vents and/or ducts that can be used in a

particular design.

To develop a reliable, cost-effective thermal solution, all of the above variables must be

considered. Thermal characterization and simulation should be carried out at the entire system

level, accounting for the thermal requirements of each component.

4.2.1

4.2.2

Die Temperature

Case temperature is a function of the local ambient temperature and the internal temperature of the

component under evaluation. Since a local ambient temperature is not directly specified for the

IXF6401 processor, the only restriction is that the maximum case temperature (T ) is not

case

exceeded.

Package Temperatures

As an aid in determining the optimum airflow and heat sink combination for IXF6401 processor,

Table 19 and Table 20 are provided below. The tables show T

ambient temperature, at the Thermal Design Power level.

as a function of airflow and

case

These tables may be used to evaluate prospective thermal solutions.

32

Datasheet

IXF6401 Broadband Access Processor

Table 19. T

as a Function of Ambient Temperature and Airflow: Without Heat Sink

case

Ambient

Temperature (° C)

T_caseTemperature at Thermal Design Power Level (° C)

70

55

35

0

130

115

95

116

101

81

109

94

106

91

103

88

74

71

68

60

46

39

36

33

Airflow Linear

Feet per Minute

0

100

200

300

400

Note: Table 19 uses the same notes as Table 20.

Table 20. T

as a Function of Ambient Temperature and Airflow: Using a Heat Sink

case

Ambient

Temperature (° C)

T_caseTemperature at Thermal Design Power Level (° C)

70

55

35

0

119

104

84

103

88

95

80

60

25

91

76

56

21

89

74

54

19

68

49

33

Airflow Linear

Feet per Minute

0

100

200

300

400

NOTES:

1. The shaded table cells indicate airflow and ambient conditions that will exceed the allowable case

temperature.

2. The heat sink case in Table 20 assumes the default thermal solution (see “Thermal Solutions” on page 33).

3. The board used for this evaluation was a four-layer, standard JESEC printed circuit board.

4. The T_casemaximum temperature, with no heat sink is 122° C. The PSI-JT changes dramatically for a

package with a heat sink. The T_casemaximum temperature, with a heat sink, is 121° C.

5. All data is simulated and is not validated against physical examples.

6. An Airflow Linear Feet per Minute value of zero is defined as a natural-convection environment.

4.2.3

Thermal Solutions

If sufficient airflow cannot be supplied to the component and motherboard, one method frequently

used to improve thermal performance is to increase the surface area of the component by attaching

a metallic heat sink to the component’s heat spreader, connected to the top of the case. To

maximize the heat transfer, maximizing the surface area of the heat sink can reduce the thermal

resistance from the heat sink to the air.

Though each design may have unique mechanical volume and height restrictions or

implementation requirements, the height, width, and depth constraints typically placed on the

IXF6401 processor are shown in Figure 8.

Datasheet

33

IXF6401 Broadband Access Processor

Figure 8. EBGA Heat Sink Volume Restrictions

17 mm

Keep-out Zone

Above Board

37 mm Square

Keep-out Zone

A8674-01

For those who have no control over their end user’s thermal environment or for those who wish to

bypass the thermal modeling and evaluation process, a default thermal solution has been developed

for the IXF6401 processor. That thermal solution will replicate the performance, defined in Table

19 and Table 20, with the processor operating at the thermal design power level.

If implementing the default thermal solution does not bring the case temperature within the values

listed in Table 18, additional cooling will be needed. This is achieved by improving airflow to the

component and applying thermal enhancements.

If airflow improvements are not implemented or successful, the default thermal solution for the

IXF6401 processor is the use of an extruded heat sink. Figure 9 on page 35 is a drawing of the heat

sink. Possible sources for extruded heat sinks are listed in “Thermal-Solution Vendors” on page 37.

34

Datasheet

IXF6401 Broadband Access Processor

Figure 9. EBGA Extruded Heat Sink Measurements

15.0 mm

34.5 mm

A8675-01

4.2.3.1

System Requirements for Thermal Efficiency

General printed-circuit-board design guidelines are listed below as recommendations for

maximizing the thermal performance of the EBGA package.

• When connecting ground (thermal) vias to the ground plane(s), do not use thermal-relief

patterns. Thermal-relief patterns are designed to limit heat transfer between the vias and the

copper planes and constrict the heat flow path from the component to the ground planes in the

printed circuit board.

• When the package is in a still-air environment and without a heat sink, the primary heat path

for conducting heat out of the PBGA package is through the vias directly under the die,

internal planes, and the ground planes of the printed circuit board. Increasing the number of

ground planes in the printed circuit board, and increasing the thickness of those copper planes,

increases heat conduction and lowers the package’s temperature. Since the primary path of

heat dissipation for the IXF6401 processor EBGA package is through the top metallic heat

spreader, printed circuit boards using 1.0-ounce copper thickness are acceptable.

• Since the board temperature also has an effect on the thermal performance of the package,

avoid placing the IXF6401 processor adjacent to high-power dissipation devices.

• For maximum thermal performance, locate the components in the main stream of the airflow

path, if airflow exists. Avoid placing the components downstream, behind larger devices or

devices with heat sinks that obstruct the airflow or supply excessively heated air.

The preceding guidelines are not all-inclusive and are listed to give the designer known good-

design practices to maximize the thermal performance of the components.

The top view of the recommended printed-circuit-board layout, for the 35-mm, 352-ball EBGA is

shown in Figure 7 on page 31.

Datasheet

35

IXF6401 Broadband Access Processor

Figure 10. Recommended and Discouraged Via Connections (Top View)

Recommended:

Solid Connection

Not Recommended:

Thermal Relief

A8676-01

Figure 11. Recommended Printed-Circuit-Board Stack Up (Cross-Sectional View)

Thermal Solder Balls

Thermal Vias

2.0 oz Cu gnd plane

A8677-01

4.2.3.2

Recommendations for Thermal Solutions

When the clock for the IXF6401 processor is running at 66 MHz or higher, a passive heat sink is

strongly recommended. See “Thermal-Solution Vendors” on page 37 for a list of possible vendors.

36

Datasheet

IXF6401 Broadband Access Processor

4.2.4

Thermal-Solution Vendors

Table 21 provides a vendor list as a reference to our customers. This list should not be considered

recommendations or product endorsements by Intel^®.

Table 21. Thermal-Solution Vendor List

Heat Sink

ChipCoolers*, Inc. Heatsinks

Aavid Thermalloy

Corporate headquarters:

80 Commercial St.

333 Strawberry Field Road

Warwick, RI 02886

Concord, NH 03301

Telephone: (603) 224-9988

Telephone: (401) 739-7600 or (800) 227-0254

Web site: http://www.chipcoolers.com

E-mail: sales@chipcoolers.com

Other worldwide offices. Visit their Web site for

contact information: http://www.aavid.com

Sumitomo Corporation

International, group headquarters:

Osaka:

5-33, Kitahama 4-chome,

Chuo-ku, Osaka 540-8666

2-2, Hitotsubashi 1-chome,

Chiyoda-ku, Tokyo 100-8601

Tokyo:

Sumitomo Corporation of America

Americas headquarters:

600 Third Ave.

New York, NY 10016-2001

Telephone: (212) 207-0700

Other worldwide offices. Visit their Web site for contact information: http://www.sumitomocorp.com

Clips

Chip Coolers* Inc.

(See listing under “Heat Sink”)

Adhesives

Loctite Corporation

Parker Hannifin Corp.

Chomerics Division

World headquarters:

77 Dragon Court

Woburn, MA 01888-4014

Telephone: (781) 935-4850

Americas headquarters:

1001 Trout Brook Crossing

Rocky Hill, CT 06067-3910

Telephone: (860) 571-5100

Other worldwide offices. Visit their Web site for

contact information: http://www.loctite.com

Other worldwide offices. Visit their Web site for

contact information: http://www.chomerics.com

E-mail address: mailbox@chomerics.com

Datasheet

37

IXF6401 Broadband Access Processor

4.3

Ordering Information

Figure 12 shows the markings on the IXF6401 Broadband Access Processor. Table 22 shows gives

the details for the figure’s codes.

Figure 12. IXF6401 Broadband Access Processor Markings

Intel Logo

with trademark

Date Code

YYWW XXXX

IXF6401BEC-S

Part Number

XXXXXXX

Country

Country of Origin

Pin #1

Indicator

A8721-01

Table 22. IXF6401 Broadband Access Processor Date and Part-Number Codes

Code

Description(s)

Date Codes

YY

Two-digit designation for year

WW

Two-digit designation for work week

Part-Number Codes

IXF6401

B

Designates the IXF6401 Broadband Access Processor

The die revision and stepping

Indicates the Enhanced Ball Grid Array Package (352

balls)

E

C

Operating temperature range

C = 0 to 70° C

Speed grade

7 = 66.6 MHz

S

Country

Country of manufacture

38

Datasheet

IXF6401 Broadband Access Processor

5.0

5.1

Electrical Specifications

Absolute Maximum Ratings

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only.

Table 23. Absolute Maximum Ratings

Parameter

Maximum Rating

Case temperature under bias

Storage temperature

0° C to 85° C

–65° C to 150° C

Ambient temperature (Power ON)

Junction temperature

0° C to 70° C

125° C

Voltage on any pin

–0.3 V to V_cc+0.3 V (with respect to GND)

–0.5 V to 7.0 V

DC input Voltage

5.2

Operating Conditions

Warning: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond

the “Operating Conditions” may affect device reliability.

Table 24. Operating Conditions

Parameter

Minimum

Maximum

Supply voltage, I/O V_cc

Ambient temperature

3.3 V – 5%

0° C

3.3 V + 5%

70° C

5.3

DC Specifications

This section contains the tables listed below.

• Table 25, “DC Characteristics (Single-PHY,155 Mbps, 622 Mbps)” on page 40 — The DC

characteristics for UTOPIA Level 2 Version 1.0

• Table 26, “DC Characteristics for (Multi-PHY, 622 Mbps)” on page 40

• Table 27, “DC Characteristics for UTOPIA Level 3 Baseline Text” on page 41

• Table 28, “DC Characteristics for PCI” on page 41

• Table 29, “DC Characteristics for LM” on page 42

• Table 30, “Power Dissipation Requirements for Thermal Design” on page 42

Datasheet

39

IXF6401 Broadband Access Processor

Table 25. DC Characteristics (Single-PHY,155 Mbps, 622 Mbps)

Symbol

Parameters

Input LOW Voltage

Test Conditions

Min

Max

Units

Notes

VIL

VIH

VOH

VOL

IOH

IOL

IIH

-0.3 V

+2.0 V

+2.4 V

+0.8 V

V

1

2

3

4

5

6

7

Input HIGH Voltage

V

_cc+ 0.3 V

Output or bidirectional HIGH Voltage

Output or bidirectional LOW Voltage

Output current at HIGH Voltage

Input current at HIGH Voltage

Input current at LOW Voltage

IOH > -4 mA

IOL > +4 mA

VOH > +2.4 V

VOL < +0.5 V

V

+0.5 V

V

-4 mA

+4 mA

mA

IIL

Note: Table 25 uses the same notes as Table 26.

Table 26. DC Characteristics for (Multi-PHY, 622 Mbps)

Symbol

Parameters

Test Conditions

Min

Max

Units

Notes

VIL

VIH

VOH

VOL

IOH

IOL

IIH

Input LOW Voltage

Input HIGH Voltage

-0.3 V

+2.0 V

+2.4 V

+0.8 V

V

1

2

3

4

5

6

7

V

_cc+ 0.3 V

Output or bidirectional HIGH Voltage

Output or bidirectional LOW Voltage

Output current at HIGH Voltage

Input current at HIGH Voltage

Input current at LOW Voltage

IOH > –8 mA

IOL > +8 mA

VOH > +2.4 V

VOL < +0.5 V

V

+0.5 V

V

-4 mA

mA

+4 mA

IIL

NOTES:

1. A device with VIL, min. < –0.3 V is compliant to this specification.

2. A device with VIH, max. > VDD + 0.3 V is compliant with this specification.

3. Negative current flows out of the considered node (out of the PHY/ATM layer device pin). A device with VOH,

min. > +2.4 V (and IOH > –4 mA ) is compliant with this specification.

4. Positive current flows into the considered node (into PHY/ATM layer device pin). A device with VOL, max. <

+0.5 V (and IOL > +4 mA) is compliant with this specification.

5. Negative current flows out of the considered node (out of the PHY/ATM layer device pin). IOH, min. defines

the minimal required IOH value for the driver.

A device with IOH, min. > –4 mA (and VOH > +2.4 V) is compliant to this specification.

6. Positive current flows into the considered node (into the PHY/ATM layer device pin). IOL, min. defines the

minimal required IOL value for the driver.

7. To allow several technologies, no values for IIH and IIL are specified. An input can sink and source.

40

Datasheet

IXF6401 Broadband Access Processor

Table 27. DC Characteristics for UTOPIA Level 3 Baseline Text

Symbol

Parameters

Test Conditions

Min

Max

Units

Notes

VOH

High-Level Output Voltage

Normal Switching Point

Low-Level Input Voltage

Input Current-Input Only

Input Current-I/O Terminals

Test Condition

2.4 V

2.0 V

V

IOH = –8 mA

VIL

0.8

0.4

+5

V

VOL

Vin = 0 or

Vin = Vdd

IIN

µA

+15

Table 28. DC Characteristics for PCI

Symbol

Parameters

Test Conditions

Min

Max

Units

Notes

VCC

VIH

Supply Voltage

Input HIGH Voltage

Input LOW Voltage

Input Leakage Current

Output HIGH Voltage

Output LOW Voltage

Input Pin Capacitance

CLK Pin Capacitance

IDSEL Pin Capacitance

Pin Inductance

3.0 V

0.5 V_cc

–0.5 V

0.7 V_cc

3.6 V

V_cc+0.5

0.3 V_cc

V

VIL

V

VIPU

IIL

V

1

2

0 < Vin < V_cc

Iout = –500 µA

Iout = 1,500 µA

+10

µA

V

VOH

VOL

CIN

0.9 V_cc

0.1 V_cc

10

V

pF

nH

3

CCLK

CIDSEL

LPIN

5

12

8

4

5

20

NOTES:

1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are

calculated to pull a floated network. Applications sensitive to static power utilization should assure that the

input buffer is conducting minimum at this input voltage.

2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with three-state outputs.

3. Absolute maximum pin capacitance for the PCI input is 10 pF (except for CLK) with an exception granted to

motherboard-only devices, which could be up to 16 pF, in order to accommodate PGA packaging. This would

mean in general that components for expansion boards would need to use alternatives to ceramic PGA

packaging, i.e., SGA.

4. Lower capacitance in this input-only pin allows for non-resistive coupling.

5. This is a recommendation, not an absolute requirement.

Datasheet

41

IXF6401 Broadband Access Processor

Table 29. DC Characteristics for LM

Symbol

Parameters

Test Conditions

Min

Max

Units

Notes

VCC

VIH

VIL

Supply Voltage

Input HIGH Voltage

Input LOW Voltage

Input Leakage Current

Output HIGH Voltage

Output LOW Voltage

0.3 V

0.5 V_cc

–0.5 V

3.6 V

V_cc+ 0.5

0.3 V_cc

+10

V

IlL

0 < Vin < Vcc

Iout = 500 µA

µA

V

VOH

VOL

0.9 V_cc

Iout = –1,500 µA

0.1 V_cc

V

Figure 13. Tval (min) and Slew Rate

0.5 inch maximum

V

CC

1 KΩ

10 pF

Output Buffer

A8422-01

Table 30. Power Dissipation Requirements for Thermal Design

Parameter

Typical^†

Maximum^††

Unit

Frequency

Thermal design power

Active power^†††

TBD

4.5

6

Watts

66.6 MHz

TBD

NOTES:

†

This value is an estimate of the typical power dissipation in a system. The value is expected to be the

average value that will be measured in a system, using a typical device at the specified voltage and running

typical applications. This value is dependent upon the specific system configuration. Typical power

specifications are not tested.

†† Systems must be designed to thermally dissipate the maximum thermal design power (TDP) unless the

system uses thermal feedback to limit the processor’s maximum power. The maximum thermal design power

is determined using a worst-case instruction mix and takes into account the thermal time constant of the

package. The given value is an estimate.

††† Active power is the average power measured in a system, using a typical device that is running typical

applications under normal operating conditions at nominal V_ccand room temperature.

42

Datasheet

IXF6401 Broadband Access Processor

5.4

Timing Specifications

5.4.1

Clock Timing

The clock waveform must be delivered to each 66-Mhz PCI component in the system. In the case

of add-in boards, compliance with clock specification is measured at the add-in board component,

not at the connector slot.

Figure 14 shows the clock waveform and required measurement points for 3.3-V signaling

environments.

Figure 14. 3.3 V Clock Waveform

3.3 V Clock

T

cyc

T

high

0.6 V

CC

0.5 V

0.4 V

cc

0.3 V

cc

0.2 V

T

CC

0.4 V , peak-to-peak

cc

(minimum)

low

A8423-01

5.4.2

Clock Specifications

Table 31. 33-MHz/66-MHz Timing Parameters

66 MHz

33 MHz

Symbol

Parameter

Units

Notes

Min

Max

Min

Max

Tcyc

Thigh

Tlow

Clock cycle time

Clock high time

Clock low time

Clock slew rate

15

6

30

11

1

ns

1, 3

6

ns

1.5

4

V/ns

2

NOTES:

1. In general, all 66.6-MHz PC components must work with a clock frequency of up to 66.6 MHz. Device

operational parameters at frequencies under 33 MHz must conform to the specifications in Chapter 4 of the

PCI specification, rev 2.1.

2. The clock frequency may be changed at any time during the operation of the system as long as the clock

edges remain “clean” (monotonic) and the minimum cycle and high and low times are not violated. The clock

maybe stopped only in a low state. A variance on this specification is allowed for components designed for

use on the system planar only. For clock frequency between 33 MHz and 66.6 MHz, the clock frequency may

not change except in conjunction with a PCI reset.

3. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met

across the minimum peak-to-peak portion of the clock waveform as shown in Figure 31. Clock slew rate is

measured by the slew rate circuit shown in Figure 13, “Tval (min) and Slew Rate” on page 42. The minimum

clock rate must not be violated for any single clock cycle, i.e., accounting for all system jitter.

Datasheet

43

IXF6401 Broadband Access Processor

5.4.3

PCI Timing Parameters

Table 32. 33-MHz and 66-MHz Timing Parameters

66 MHz

33 MHz

Symbol

Parameter

Units

Notes

Min

Max

Min

Max

PCI_CLK to signal valid delay –

bused signals

Tval

2

6

2

11

ns

1, 2, 3

PCI_CLK to signal valid delay –

point-to-point signals

Tval(ptp)

2

6

2

12

28

Ton

Toff

Float to active delay

Active to Float delay

ns

1, 5

14

Input setup time to PCI_CLK –

bused signals

Tsu

3

5

ns

3, 4

10

12

Input setup time to PCI_CLK –

point-to-point signals

Tsu(ptp)

3, 4

4

Th

Input Hold time from PCI_CLK

0

1

0

1

ns

RESET active time after Power

stable

Trst

ms

RESET active time after

PCI_CLK stable

Trst-clk

Trst-off

Trrsu

100

µs

ns

RESET active to output float

delay

40

50

40

50

PCI_REQ64# to PCI_RST#

setup time

10 Tcyc

0

10 Tcyc

0

PCI_RST# to PCI_REQ64#

HOLD time

Trrh

NOTES:

1. See the timing measurement conditions in Figure 15 and Figure 16. It is important that all driven signal

transitions drive to their Voh or Vol level within one Tcyc.

2. Minimum times are measured at the package pin with the load circuit shown in Figure 17 on page 46 and

Figure 18 on page 46. Maximum times are measured with the load circuit shown in Figure 17 on page 46 and

Figure 18 on page 46.

3. PCI_REQ64# and PCI_GNT# are point-to-point signals and have different input setup times than do bused

signals. The PCI_REQ64# and PCI_GNT# signals have a setup time of 5 ns at 66.6 Mhz. All other signals

are bused. See the timing measurement conditions in chapter four of the PCI specification.

4. PCI_RST# is asserted and deasserted asynchronously with respect to PCI_CLK. All output drivers must be

floated when PCI_RST# is active.

5. For the purposes of active/float timing measurements, the HI-Z or “off” state is defined as when the total

current delivered through the component pin is less than or equal to the current leakage specification.

44

Datasheet

IXF6401 Broadband Access Processor

Figure 15. Output Timing Measurement Conditions

V

TH

TL

CLK

T

Output Delay

tval

V

= 0.3 V

tfall

CC

V

= 0.5 V

CC

trise

Three-state Output

T

on

T

off

A8424-01

Figure 16. Input Timing Measurement Conditions

V

th

V

CLK

test

tl

T

h

T

su

V

th

Valid

V

Input

max

V

tl

V

test

A8425-01

Datasheet

45

IXF6401 Broadband Access Processor

Figure 17. Tval (max) Rising Edge

0.5 inch maximum

25 Ω

10 pF

Output Buffer

A8426-01

Figure 18. Tval (max) Falling Edge

0.5 inch maximum

V

CC

25 Ω

Output Buffer

10 pF

A8427-01

5.4.4

UTOPIA Timing Parameters

The IXF6401 processor’s UTOPIA interface is fully compliant with the ATM Forum

specifications. The following timing description is an extract from the ATM Form UTOPIA Level

2 Specification, Version 1.0 of June 1995 (af-phy-0039.0000).

Table 33. Transmit Timing

16-bit Data Bus, UTOPIA-II 50-MHz at Cell Interface, Single/Multi-PHY

Input (I)

Output (O)

Signal Name

Item

Description

Min

Max

f1

TXCLK frequency (nominal)

TXCLK duty cycle

TXCLK peak-to-peak jitter

0

40%

50 MHz

60%

5%

tT2

tT3

tT4

TXCLK

I

TXCLK rise/fall time

2 ns

TXDATA[15:0],

tT5

tT6

O

I

Output delayed

4 ns

13 ns

TXPRTY, TXSOC,

TXEN#

TXFULL#/

TXCLAV

tT7

tT8

Input setup to TXCLK

Input hold from TXCLK

4 ns

1 ns

46

Datasheet

IXF6401 Broadband Access Processor

Table 34. Receive Timing

16-bit Data Bus, UTOPIA-II 50-MHz at Cell Interface, Single/Multi-PHY

Input (I)

Output (O)

Signal Name

Item

Description

Min

Max

f1

RCCLK frequency (nominal)

RCCLK duty cycle

RCCLK peak-to-peak jitter

TXCLK rise/fall time

0

40%

50 MHz

60%

5%

tT2

tT3

tT4

RCCLK

I

O

I

2 ns

tT5

tT6

RXEN#

Output delayed

4 ns

13 ns

RCDATA[15:0],

RCPRTY, RCSOC,

RCEMPTY#/

RCCLAV

tT7

tT8

Input setup to RCCLK

Input hold from RCCLK

4 ns

1 ns

5.4.5

Local Memory Bus Timing

Table 35. Local Memory Bus Timing Parameters

66 MHz

33 MHz

Min Max

Symbol

Parameter

Units

Notes

Min

Max

Tcyc

Thigh

Tlow

Clock cycle time

Clock high time

Clock low time

Input setup

15

6

ns

1, 2

9

6

Tsetup

Thold

Tdly

1

Input hold

4

Output delay

4

13

14

Thigh-z

High impedance delay

5

NOTES:

1. See the timing measurement conditions in Figure 14. It is important that all driven signal transitions drive to

their Voh or Vol level within one Tcyc.

2. Minimum times are measured at the package pin with the load circuit shown in Figure 17 on page 46 and

Figure 18 on page 46. Maximum times are measured with the load circuit shown in Figure 17 on page 46 and

Figure 18 on page 46.

Datasheet

47

IXF6401 Broadband Access Processor

Figure 19. Local Memory Bus Timing Specifications

T

high

T

low

CLK

T

cyc

T

hold

setup

Inputs

T

dly

Valid

Outputs

T

hi-Z

A8428-01

Figure 20. Recommended Local Memory Clock Circuitry

LM_D

LM_A

IXF6401

SSRAM / SDRAM

LM_CLK

2.5 ~ 3 ns

Programmable Delay

Note:

The value is 2.5 ns for 8 pF of loading on local-memory bus. The value is 3.5 ns for 30-pF loading.

A8429-01

48

Datasheet

厂商	型号	描述	页数
ILSI	IXF	晶体滤波器3线金属包装[ Crystal Filter 3 Lead Metal Package ]	1 页
ILSI	IXF-10A15AF	晶体滤波器3线金属包装[ Crystal Filter 3 Lead Metal Package ]	1 页
ILSI	IXF-10A15AT	晶体滤波器3线金属包装[ Crystal Filter 3 Lead Metal Package ]	1 页
ILSI	IXF-10A15BF	晶体滤波器3线金属包装[ Crystal Filter 3 Lead Metal Package ]	1 页
ILSI	IXF-10A15BT	晶体滤波器3线金属包装[ Crystal Filter 3 Lead Metal Package ]	1 页
ILSI	IXF-10A15CF	晶体滤波器3线金属包装[ Crystal Filter 3 Lead Metal Package ]	1 页
ILSI	IXF-10A15CT	晶体滤波器3线金属包装[ Crystal Filter 3 Lead Metal Package ]	1 页
ILSI	IXF-10A15DF	晶体滤波器3线金属包装[ Crystal Filter 3 Lead Metal Package ]	1 页
ILSI	IXF-10A15DT	晶体滤波器3线金属包装[ Crystal Filter 3 Lead Metal Package ]	1 页
ILSI	IXF-10A20AF	晶体滤波器3线金属包装[ Crystal Filter 3 Lead Metal Package ]	1 页