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OXFW970-TQ-A

型号：

OXFW970-TQ-A

品牌：

OXFORD[ OXFORD SEMICONDUCTOR ]

页数：

10 页

PDF大小：

278 K

下载PDF手册
Data Sheet  
OXFW970  
7.1 Channel-Streaming Audio FireWire Controller  
Features  
„
„
„
4 serial-audio ports providing 8 channels (4 stereo channels)  
2 input channels  
Supports standard AM824 audio format (as specified in  
IEC 61883-6)  
„
„
Supports master & slave modes (bit/word clocks) on serial audio  
interface  
Provides a master clock (256 fs) & synchronized serial audio  
interface to an external DAC  
„
„
Provides low-jitter audio master clock (256 fs) clock recovery  
External DAC can be set up using a conventional serial control  
interface (using GPIO pins)  
„
„
„
ARM7TDMI® embedded processor  
Supports both IEEE1394a & IEEE 1394b at speeds up to S800  
1394 isochronous serial audio interface supports 4 × 2 audio  
channels  
„
„
Integrated 512-kbit flash memory  
Supports remote flash programming via the 1394 serial bus  
(firmware & flash programming utilities supplied by Oxford  
Semiconductor)  
„
„
„
„
Debug capabilities using internal UART or JTAG ports  
3.3-V I/O, 1.8-V core operating voltage  
100-pin TQFP (14 × 14 × 1 mm)  
Supports audio sample rates of 32 kHz, 44.1 kHz, 48 kHz &  
96 kHz, with 16-, 24-, & 32-bit samples  
„
„
Supports external audio master clock smoothing  
Supports Mac OS & Windows  
DS-0004 Jun 05 (2)  
External—Free Release  
1
OXFW970 Data Sheet  
Oxford Semiconductor Ltd.  
Device  
The OXFW970 is a cost-effective 1394-to-audio native bridge.  
Overview  
This highly-integrated device offers a two-chip solution to native bridge  
applications using an external 1394 PHY. The device is compatible with  
both 1394-1995, 1394a and 1394b PHYs.  
Applications can receive up to two channels of audio and stream data to  
multiple speakers via DACs, generating 7.1 audio channels.  
Device  
Functionality  
Within the device, the link controller complies with 1394-1995, 1394a and  
1394b specifications. The 1394 transaction layer is implemented using a  
combination of the ARM7TDMI (low-power 32-bit RISC processor) and a  
high-performance buffer manager.  
The FIFO manager has a RAM bandwidth of 1600 Mbps. It stores 1394  
packets, passing them to the appropriate destinations without processor  
intervention.  
Configuration data, including the IEEE organizational unique identifier  
(OUI) and device serial number, is stored in the flash ROM which may  
be uploaded from the 1394 bus even when blank. The device also  
facilitates firmware uploads from the 1394 bus.  
The audio core in the OXFW970 can handle the transfer of samples in  
standard 61883-6 format to multiple serial-audio interfaces. Interfaces  
are configured to support stereo audio (4 × 2-channels gives the  
necessary left/right samples). The audio core can support two versions of  
serial-audio protocol and communicate with devices that use different  
numbers of bits per sample. Input channels are handled via the internal  
UART.  
The OXFW970 also provides the master clock (256 fs) to the external  
DAC, to which the serial-audio interface is synchronized. Clock recovery  
is performed to synchronize the master clock to the 1394 transmitting  
node. The performance of clock jitter can be further enhanced by using a  
suitable external circuit.  
Eight GPIO pins can be used to extend the device capabilities. GPIOs can  
be used to control an external DAC via a DAC serial control interface.  
On the device, UART signals are multiplexed to support debugging; and  
other signals are wired to generate device interrupts.  
Figure 1 shows the OXFW970.  
2
External—Free Release  
DS-0004 Jun 05 (2)  
Oxford Semiconductor Ltd.  
OXFW970 Data Sheet  
Figure 1 OXFW970 Diagram  
GPIO  
Bit Clock  
Word Clock  
Data (0)  
Data (1)  
Data (2)  
Data (3)  
Serial Audio  
ARM  
Reference  
Peripheral Set  
RAM control  
Asynch-  
ronous  
Engine/  
Isoch Rx  
Engine  
FIFO pointers  
Fill level  
information  
1394  
1394  
Link  
Layer  
Audio 256-fs Clock Out  
Audio 256-fs Clock In  
Audio PD VCO Out  
Audio PD SYS Out  
Unified memory  
architecture:  
Clock  
Recovery  
Flash  
Memory  
APB  
Bridge  
Queue  
Selector  
Audio-In  
UART  
Scratch  
RAM  
ARM7TMDI  
Environmental  
Characteristics  
Tables 1 to 3 detail the required operating conditions for the device and  
the DC electrical characteristics.  
Table 1 Absolute Maximum Device Ratings  
Symbol  
Parameter  
Rating  
Units  
V
V
V
T
DC supply voltage  
1.8 V  
3.3 V  
2.7  
3.8  
V
DD  
DC input voltage  
3.3-V input buffer  
3.3-V interface/5-V tolerant input buffer  
3.8  
6.5  
V
V
IN  
DC output voltage  
Storage temperature  
3.3-V output buffer  
3.3-V interface/5-V tolerant output buffer  
3.8  
6.5  
OUT  
Storage temperature  
–40 to 85  
°C  
STG  
Table 2 Recommended Operating Conditions  
Symbol  
Parameter  
Rating  
Units  
V
V
V
T
DC supply voltage for internal  
DC supply voltage for I/O block 3.3 V  
1.8 V  
1.8 ± 0.15  
3.3 ± 0.3  
V
DD  
DC input voltage  
3.3-V input buffer  
3.3-V interface/5-V tolerant input buffer  
3.3 ± 0.3  
3.0~5.25  
V
IN  
DC output voltage  
3.3-V output buffer  
3.3-V interface/5-V tolerant output buffer  
3.3 ± 0.3  
3.3 ± 0.3  
OUT  
Industrial temperature range  
–40 to 85  
°C  
A
DS-0004 Jun 05 (2)  
External—Free Release  
3
OXFW970 Data Sheet  
Oxford Semiconductor Ltd.  
Table 3 Device I/O Buffer Electrical Characteristics  
Symbol  
Parameter  
Input high voltage  
Condition  
Min  
Type  
Max  
Units  
V
V
CMOS Interface  
2.0  
V
IH  
IL  
Input low voltage  
CMOS Interface  
0.8  
V
V
VT  
Switching threshold  
1.4  
+
-
Schmitt trigger, positive-going threshold  
Schmitt trigger, negative-going threshold  
CMOS  
CMOS  
V = V  
2.0  
V
VT  
VT  
0.8  
V
I
Input high current:  
Input buffer  
Input buffer with pull-down  
μA  
IH  
IN  
DD  
SS  
–10  
10  
10  
60  
33  
I
Input low current:  
Input buffer  
Input buffer with pull-up  
V = V  
μA  
IL  
IN  
–10  
–60  
10  
–10  
–33  
V
Output high voltage  
Output low voltage  
I
I
= –1 μA  
= –1 mA to –24 mA  
V – 0.05  
DD  
V
V
OH  
OL  
OH  
OH  
2.4  
V
I
I
= 1 μA  
= 1 mA to 24 mA  
0.05  
0.4  
OL  
OL  
I
Tri-state output leakage current  
Quiescent supply current  
Input capacitance  
V
= V V  
SS or DD  
-10  
10  
100  
4
μA  
μA  
pF  
OZ  
OUT  
I
DD  
C
Any input &  
IN  
bidirectional buffers  
C
Output capacitance  
Any output buffer  
4
pF  
OUT  
Power  
Table 4 gives power consumption figures for the OXFW970.  
Consumption  
Table 4 OXFW970 Power Consumption  
Idle  
Max  
mA  
115  
6
mW  
207  
mA  
250  
25  
mW  
1.8 V  
3.3 V  
Core  
I/O  
450  
19.8  
82.5  
4
External—Free Release  
DS-0004 Jun 05 (2)  
Oxford Semiconductor Ltd.  
OXFW970 Data Sheet  
Pinout &  
Package  
The device is supplied as a 100-pin TQFP package (14 × 14 × 1 mm).  
Figure 2 shows the chip layout.  
Information  
Figure 2 OXFW970 Pinout  
DNC  
DNC  
VDD1V8  
VDD3V3  
JTAG_TDI  
JTAG_TCLK  
JTAG_TMS  
DNC  
1
75  
DNC  
DNC  
VSS3V3  
VDD3V3  
DNC  
DNC  
AUDIO_FS_WORD_CLK  
DNC  
DNC  
VSS3V3  
AUDIO_PD_VCO_OUT  
VSS1V8  
AUDIO_PD_SYS_OUT  
VSS1V8  
VDD1V8  
GPIO_7  
GPIO_6  
GPIO_5  
GPIO_4  
DNC  
VDD1V8  
DNC  
OXFW970  
DNC  
DNC  
JTAG_UART_SEL  
VDD1V8  
VSS1V8  
GPIO_3  
DNC  
GPIO_2  
VSS3V3  
DNC  
GPIO_1  
GPIO_0  
DNC  
VDD3V3  
VSS3V3  
DNC  
DNC  
Z_FORCE_FLASH  
Z_RESET  
DNC  
25  
51  
Table 5 on page 6 details the pin allocations for the device.  
DS-0004 Jun 05 (2)  
External—Free Release  
5
OXFW970 Data Sheet  
Oxford Semiconductor Ltd.  
Table 5 OXFW970 Pin Allocations (Sheet 1 of 2)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
LINK (External Interface) (16 pins)  
26,27,28,29,32,33,34,  
35  
8
5_BD_4T PD[7:0]  
PHY-link data bus  
36,37  
41  
2
1
5_BD_4T CTL[1:0]  
PHY-link control bus  
5_IU  
PCLK  
49.152-/ 98.304-MHz clock sourced by PHY. Drives  
main clock system  
42  
1
1
1
1
1
O_4  
5_IU  
O_4  
O_8  
5_IU  
LREQ  
LINKON  
LPS  
Link request  
43  
Requests link to power up when in a low power mode  
Indicates to PHY that link is powered and ready  
B only—PCLK returned to PHY  
B only—PHY Interrupt  
45  
40  
LCLK  
PINT  
44  
AUDIO  
85  
1
1
1
1
4
1
1
5_O_4  
5_I  
256FS_CLK_O  
256FS_CLK_I  
Sys clock generated 256Fs clock (to DAC)  
Returned (smoothed) 256Fs clock (from VCO)  
Serial audio bit clock  
84  
49  
5_BD_4T BIT_CLK  
68  
5_B_4T  
5_B_4T  
5_B_4T  
5_B_4T  
WORD_CLK  
Serial audio word clock  
76,77,81,48  
AUDIO_DATA[3:0]  
SYS_FS_PDOUT  
VCO_FS_PDOUT  
Audio data synchronised to BIT_CLK  
Output-of-audio phase detector from SYS_CLK  
Output-of-audio phase detector from VCO clock  
65  
66  
GPIO (8 pins)  
62,61,60,59,18,19,20,  
21  
8
5_B_4T  
GPIO[7:0]  
General purpose I/O pins  
PLL (5 pins)  
91  
93  
92  
90  
89  
1
1
1
1
1
P
P
P
P
P
PLL_DVDD  
PLL_DVSS  
PLL_AVDD  
PLL_AVSS  
VBB_PLL  
PLL digital 1.8V  
PLL digital GND  
PLL analogue 1.8 V  
PLL analogue GND  
PLL bulk bias  
UART / JTAG (4 pins) mode defined by JTAG_UART_SEL pin  
100  
4
1
1
1
1
O_4  
UART_SOUT  
UART transmitter serial data output  
Active-low request-to-send output  
Receiver serial data input  
5_BU_4T UART_Z_RTS  
5
5_IU  
5_IU  
UART_SIN  
6
UART_Z_CTS  
Active-low clear-to-send input.  
MISC  
24  
25  
98  
1
1
1
5_IU  
5_I  
Z_FORCE_FLASH Allows flash memory programming  
Z_RESET  
Main asynchronous reset  
5_ID  
SEL_B_PHY  
Selects between 1394a & 1394b mode:  
High—B PHY  
Low—A PHY  
6
External—Free Release  
DS-0004 Jun 05 (2)  
Oxford Semiconductor Ltd.  
OXFW970 Data Sheet  
Table 5 OXFW970 Pin Allocations (Sheet 2 of 2)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
15  
JTAG_UART_SEL  
Selects UART mode:  
Low—UART  
Power & Ground  
2,11,16,38,63,88  
6
9
VDD1V8  
VDD3V3  
3,22,30,46,50,71,83,  
97,99  
10,17,39,64,87  
5
8
VSS1V8  
VSS3V3  
9,23,31,47,56,72,  
82,96  
NC  
1,7,8,12,13,14,78,80,  
86,94,95  
11  
14  
NC  
51,52,53,54,55,57,58,  
67,69,70,73,74,75,79  
Reserved  
Tie low using 4K7 Ω resistor (typical)  
Note:  
1
Type key: format is [(W_)X(Y)(_Z(A))] where the following conventions apply:  
W—Tolerance  
X—Type  
Input  
Y—Pull  
Z—Drive  
4 mA  
T—Tristate  
Tristate  
Normal  
5
5 V  
I
U
D
Pull up  
4
8
T
3V3  
O
B
Output  
Pull down  
None  
8 mA  
Bidirectional  
12  
12 mA  
Figure 3 on page 8 shows the OXFW970 package.  
DS-0004 Jun 05 (2)  
External—Free Release  
7
OXFW970 Data Sheet  
Oxford Semiconductor Ltd.  
Figure 3 OXFW970 Package  
8
External—Free Release  
DS-0004 Jun 05 (2)  
Oxford Semiconductor Ltd.  
OXFW970 Data Sheet  
Ordering  
Information  
The following conventions are used to identify Oxford Semiconductor  
products:  
FW970 - TQ - A  
FW970 - TQ - A G  
Conventional package  
Green package  
Green (RoHS compliant)  
Revision  
Package Type: TQ 100 TQFP  
Part Number  
Contacting  
Oxford Semi-  
conductor  
Oxford Semiconductor contact details:  
Oxford Semiconductor Ltd.  
25 Milton Park  
Abingdon  
Oxfordshire  
OX14 4SH  
United Kingdom  
Website:  
http://www.oxsemi.com  
Telephone:  
Fax:  
+44 (0) 1235 824900  
+44 (0) 1235 821141  
Email:  
sales@oxsemi.com  
Alternatively, you can contact your local representative.  
Revision  
Table 6 documents the revisions of this guide.  
Information  
Table 6 Revision Information  
Revision  
Jan 05  
Modification  
Revised to clarify the use of the UART for audio input channels  
Revised to reinstate missing pin & classify some NCs as reserved, tie low  
Revised to correct erroneous electrical characteristics in Table 3 on page 4  
Jun 05  
Jun 05 (2)  
DS-0004 Jun 05 (2)  
External—Free Release  
9
OXFW970 Data Sheet  
Oxford Semiconductor Ltd.  
All trademarks are the property of their respective owners  
© Oxford Semiconductor Limited 2005  
The content of this paper is furnished for informational use only, is subject to change without notice, and should not be construed  
as a commitment by Oxford Semiconductor Limited. Oxford Semiconductor Limited assumes no responsibility or liability for  
any errors or inaccuracies that may appear in this paper.  
10  
External—Free Release  
DS-0004 Jun 05 (2)  
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