IXF3208
Octal T1/E1/J1 Framer with On-Chip PRM
Advance Information Datasheet
The Intel® IXF3208 with On Chip PRM is an octal framer for T1/E1/J1 and ISDN primary rate
interfaces operating at 1.544 Mbps or 2.048 Mbps. Each framer consists of a receive and
transmit framer, receive and transmit slip buffer. Each of the eight framers operates
independently, allowing each channel to be individually configured for T1, E1, or J1 operation
through software. The Intel® IXF3208 interfaces directly with the Intel® LXT3108 Octal T1/
E1/J1 Long-Haul Short-Haul Line Interface Unit or the Intel® LXT384 Octal T1/E1/J1 Short-
Haul Line Interface Unit. To comply with both ANSI T1.231, T1.403 and ETSI G.821
specifications, comprehensive performance monitoring is done on-chip providing Intel On-chip
Performance Report Messaging (Intel PRM). The PRM collects 18 parameters every second,
15 minutes and 24 hours. The Intel IXF3208 is the ideal framer for voice and data applications as
it incorporates 24 independent HDLC controllers that can be allocated to any time slot in the 8
T1/E1/J1 links it supports. This greatly simplifies the implementation of scalable GR-303 and
V5.2 interfaces. GR-303 and V5.2 are interface standards to a digital switching facility
comprised by multiple T1/E1/J1 links. The Intel IXF3208 has an 8 bit microprocessor bus
supporting both Intel and Motorola interface. A flexible TDM interface supports bus rates from
1.544 MHz to 16.384 MHz and industry-standard buses including MVIP, HMVIP, H100, CHI
etc. The Intel IXF3208 is available in a 17x17 mm PBGA package to enable the design of high-
port density, multi-service line cards.
Applications
■ Voice over packet gateways
■ Wireless base stations
■ Integrated Multi-service Access Platforms ■ Routers
(IMAPs)
■ Frame relay access devices, CSU/DSU
equipment
■ Integrated Access Devices (IADs)
■ Inverse multiplexing for ATM (IMA)
Product Features
■ Intel Performance Report Message (PRM) ■ FDL and DDL support. HDLC formatting
per T1.231 T1.403 and ITU G.826 is done
on-chip offloading the system CPU and
speeds development by gathering and
building the performance monitoring
database, which is an essential part of the
network reliability data.
for FDL or transparent mode.
■ BERT generators and analyzers for
extensive testing on chip.
■ 24 HDLC controllers on chip allow
compliance to V5.1, V5.2 and GR-303
specifications. Frame relay applications can
be designed without the use of external
HDLC controllers.
■ Framer support for T1: SF, ESF, SLC96,
J1-12, J1-24. E1: G.704, G.706, FAS/NFAS,
CAS, CRC-4-CAS, CRC4.
■ Separate or multiplexed system bus
operating at either 1x, 2x, 4x, 8x of the data
rate.
Notice: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 249544-001
June 2001
