IDT5V10007
VCXO PLUS AUDIO CLOCK FOR STB
VCXO AND SYNTHESIZER
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors on the
PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture and
frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
External Component Selection
The IDT5V10007 requires a minimum number of external
components for proper operation.
De coupling Capacitors
Decoupling capacitors of 0.01µF should be connected
between VDD and GND on pins 3 and 4, pins 6 and 7, and
pins 11 and 14 as close to the IDT5V10007 as possible. For
optimum device performance, the de coupling capacitors
should be mounted on the component side of the PCB.
Avoid the use of vias in the de coupling circuit.
The procedure for determining the value of these capacitors
can be found in application note MAN05.
Series Termination Resistor
When the PCB traces between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ωresistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
Quartz Crystal
The IDT5V10007 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To assure
the best system performance (frequency pull range) and
reliability, a crystal device meeting IDT’s recommended
parameters must be used, and the layout guidelines
discussed in the following section must be followed.
See Application Note MAN05 for a full list of crystal
parameters.
The frequency of oscillation of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
IDT5V10007 incorporates on-chip variable load capacitors
that “pull” (change) the frequency of the crystal. The crystal
specified for use with the IDT5V10007 is designed to have
zero frequency error when the total of on-chip + stray
capacitance is 14pF.
The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the IDT5V10007. There should be no via’s between the
crystal pins and the X1 and X2 device pins. There should be
no signal traces underneath or close to the crystal.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
IDT™ VCXO PLUS AUDIO CLOCK FOR STB
3
IDT5V10007 REV C 071907
