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7P032ATA3305I25

型号：

7P032ATA3305I25

品牌：

WEDC[ WHITE ELECTRONIC DESIGNS CORPORATION ]

页数：

21 页

PDF大小：

103 K

下载PDF手册
ATA PCMCIA Card  
ATA33 Series  
WHITE ELECTRONIC DESIGNS  
ATA Flash card  
FEATURES  
• PC Card ATA compatible  
- 68 pin two piece connector and type I or type II housing  
(5mm)  
WEDC ATA33 Series flash memory cards are ATA  
compatible cards and are suitable for usage as a data  
storage memory medium for PC’s or any other  
electronic equipment. This product is built with high  
performance NAND memory devices and SanDisk  
controller.  
- PCMCIA/JEIDA 4.1  
• x8/x16 PCMCIA standard interface  
• Single 3 Volt / 5 Volt Supply  
Packaged in a PCMCIA type I or type II housing,  
the WEDC ATA series cards provide a lightweight,  
low power, reliable nonvolatile storage medium.  
Built in to the card controller, Error Correcting Code  
(ECC) provides a high level of reliability and MTBF  
(Mean Time Between Failures).  
• ISA standard, Read/Write unit is 1 sector (512 bytes)  
- Sector Read/Write transfer rate:  
-sustain: approx 1MB/sec (ATA33)  
- High reliability based on internal ECC function (Error  
Correcting Code)  
• Card Capacity  
- 32 MB to 1024 MB (unformatted)  
WEDC’s standard cards are shipped with the WEDC  
FLASH Logo. Cards are also available with blank  
housings (no Logo). The blank housings are available  
in both a recessed (for label) and flat housing. Please  
contact your WEDC sales representative for further  
information on Custom artwork.  
• Card Access mode:  
- Memory card mode  
- I/O card mode  
- True-IDE mode  
• Reliability:  
• MTBF  
1,000,000 hours  
• Data reliability is 1 error in 1014 bits read  
NOTE: ATA33 product family is electrically and  
functionally compatible with the older ATA30.  
• Auto Sleep Function  
Block Diagram  
Memory Array  
Code/software  
DATA  
ADRS  
...  
DATA I/O  
CONTROLLER  
CONTROL  
OSC  
October 2001  
1
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Internal Vcc  
Vcc  
GND  
A0 to A10  
-CE1, -CE2  
-OE, -ATASEL  
-WE  
-IORD  
-IOWR  
Flash  
-REG  
Memory  
Bus  
RESET/-RESET  
Flash  
Memory  
array  
Controller  
-CSEL  
D0 TO D15  
RDY/-BSY/-IREQ/INTRQ  
WP/-IOIS16  
Control signal  
-INPACK  
BVD1/STSCHG/-PDIAG  
-WAIT/IORDY  
VS1  
VS2  
OPEN  
BVD2/-SPKR/-DASP  
-CD1  
-CD2  
October 2001  
2
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Mechanical  
Type I  
Interconnect area  
1.6mm ± 0.05  
(0.063”)  
10.0mmMIN  
(0.400”)  
3.0mm MIN  
1.0mm ± 0.05  
(0.039”)  
Substrate area  
54.0mm ± 0.10  
(2.126”)  
85.6mm ± 0.20  
(3.370”)  
1.0mm ± 0.05  
(0.039”)  
10.0mmMIN  
(0.400”)  
3.3mm ± T1 (0.130”)  
T1=0.10mm interconnect area  
T1=0.20mm substrate area  
Type II  
1.6mm ± 0.05  
0.063”  
85.6mm ± 0.20  
3.370”  
1.0mm ±0.05  
0.039’  
3.0mm  
MIN.  
Substrate area  
54.0mm ± 0.10  
2.126”  
1.0mm ±0.05  
0.039’  
10.0mm MIN  
0.400”  
Interconnect area  
3.3mm ± 0.10mm  
5.0mm ± T1  
0.197”  
October 2001  
3
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Start up time / System Performance  
Sleep to Write  
2.5ms max  
Sleep to Ready  
2.0 ms max  
Reset to Ready  
50 ms typ, 400 ms max  
4.0MB/sec burst  
6.0MB/sec burst  
Programable  
Data trasfer rate to/from Flash  
Data trasfer rate to/from Host  
Active to Sleep Delay  
Controller overhead Command to DRQ <1.25 ms  
Power requirements (Note 1)  
DC input voltage  
Commercial  
3.3V ±5%, 5V ±10%  
Industrial  
3.3V ±5%, 5V ±5%  
Typ power Dissipation (Note 3, 4)  
Sleep  
Read  
Write  
200uA (3.3V), 500uA (5V)  
32-50mA (3.3V), 46-90mA (5V)  
32-70mA (3.3V), 46-110mA (5V)  
Environmental Spec.  
Temperature  
Operating Commercial  
Operating Industrial  
Non-operating Commercial  
Humidity  
0 to 60 C  
-40 to 85 C  
-25 to 85 C  
200uA (3.3V), 500uA (5V)  
8 - 95% non-condensing  
8 - 95% non-condensing  
Operating  
Non-operating  
Vibration  
Operating  
Non-operating  
Shock  
15G peak to peak max  
15G peak to peak max  
Operating  
Non-operating  
Reliability  
1000 G max  
1000 G max  
MTBF  
1,000,000 hours  
Notes:  
1.  
All values are typical at ambient temperature and nominal supply voltage, unless  
otherwise stated  
2.  
3.  
All performance timing asuumes the controller is in the default (I.e. faster) mode  
Sleep mode currently is specified under the condition that all card inputs are in static  
CMOS levels and in a “Not Busy” operating state.  
4.  
The current specified, shows the bounds of programmability of the product  
October 2001  
4
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Pinout  
Memory card mode  
Pin Number Signal Name  
I/O Card Mode  
Signal Name  
GND  
D3  
True IDE Mode  
I/O  
I/O  
Signal Name  
GND  
D3  
I/O  
1
2
GND  
D3  
I/O  
I/O  
I/O  
3
D4  
I/O  
D4  
I/O  
D4  
I/O  
4
D5  
I/O  
D5  
I/O  
D5  
I/O  
5
D6  
I/O  
D6  
I/O  
D6  
I/O  
6
D7  
I/O  
D7  
I/O  
D7  
I/O  
7
CE1#  
A10  
OE#  
N.C.  
A9  
I
I
I
-
I
I
-
-
I
CE1#  
A10  
OE#  
N.C.  
A9  
I
I
I
-
I
I
-
-
I
CE1#  
A10  
ATASEL#  
N.C.  
A9  
I
I
I
-
I
I
-
-
I
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
A8  
A8  
A8  
N.C.  
N.C.  
WE#  
RDY/BSY  
Vcc  
N.C.  
N.C.  
WE#  
IREQ#  
Vcc  
N.C.  
N.C.  
N.C.  
N.C.  
A7  
N.C.  
N.C.  
WE#  
INTRQ  
Vcc  
N.C.  
N.C.  
N.C.  
N.C.  
A7  
O
O
O
N.C.  
N.C.  
N.C.  
N.C.  
A7  
A6  
A5  
A4  
A3  
-
-
-
-
I
I
I
I
I
-
-
-
-
I
I
I
I
I
-
-
-
-
I
I
I
I
I
A6  
A5  
A4  
A3  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
D0  
D1  
D2  
WP  
GND  
I
I
I
A2  
A1  
A0  
D0  
D1  
D2  
I
I
I
A2  
A1  
A0  
D0  
D1  
D2  
I
I
I
I/O  
I/O  
I/O  
O
I/O  
I/O  
I/O  
O
I/O  
I/O  
I/O  
O
IOIS16#  
GND  
IOIS16#  
GND  
October 2001  
5
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Pinout  
Memory card mode  
Pin Number Signal Name  
I/O Card Mode  
Signal Name  
GND  
CD1#  
D11  
True IDE Mode  
Signal Name  
I/O  
I/O  
I/O  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
GND  
CD1#  
D11  
GND  
CD1#  
D11  
O
O
O
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
D12  
D12  
D12  
D13  
D14  
I/O  
I/O  
D13  
D14  
I/O  
I/O  
D13  
D14  
I/O  
I/O  
D15  
CE2#  
VS1  
IORD#  
IOWR#  
NC  
I
I
D15  
CE2#  
VS1  
IORD#  
IOWR#  
NC  
I
I
D15  
CE2#  
VS1  
IORD#  
IOWR#  
NC  
I
I
O
I
O
I
O
I
I
-
I
-
I
-
NC  
NC  
NC  
-
-
-
NC  
NC  
NC  
-
-
-
NC  
NC  
NC  
-
-
-
NC  
Vcc  
-
NC  
Vcc  
-
NC  
Vcc  
-
NC  
NC  
-
-
NC  
NC  
-
-
NC  
NC  
-
-
NC  
NC  
-
-
NC  
NC  
-
-
NC  
NC  
-
-
CSEL#  
VS2  
I
O
I
O
O
I
CSEL#  
VS2  
I
O
I
O
O
I
CSEL#  
VS2  
I
O
I
O
O
I
RESET  
Wait#  
INPACK#  
REG#  
BVD2  
BVD1  
D8  
RESET  
Wait#  
INPACK#  
REG#  
SPKR#  
STSCHG#  
D8  
RESET#  
IORDY  
INPACK#  
REG#  
DASP  
PDIAG#  
D8  
I/O  
I/O  
I/O  
I/O  
O
O
I/O  
I/O  
I/O  
I/O  
O
O
I/O  
I/O  
I/O  
I/O  
O
O
D9  
D10  
D9  
D10  
D9  
D10  
CD2#  
GND  
CD2#  
GND  
CD2#  
GND  
Notes:  
1) CD1# and CD2# are grounded internal to PC Card  
October 2001  
6
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Card Signal Description  
Symbol  
Type  
Name and Function  
A0 – A10  
INPUT  
ADDRESS INPUTS: A0 through A10 Signal A0 is not used in word  
access mode. A10 is the most significant bit. In True IDE Mode only  
HA[2..0] are used for selecting the eight registers in the Task File, the  
remaining address lines should be grounded.  
D0 - D15  
INPUT/OUT  
PUT  
DATA INPUT/OUTPUT: D0 THROUGH D15 constitute the bi-  
directional databus. D0 - D7 constitute the lower (even) byte and D8 -  
D15 the upper (odd) byte. D15 is the MSB.  
CE1#, CE2#  
INPUT  
CARD ENABLE 1 AND 2: active low signals; CE1# enables even  
byte accesses, CE2# enables odd byte accesses. In True IDE Mode  
CE2# is used to select the Alternate Status Register and the Device  
control Register while CE1# is the cheap select for the other task file  
registers.  
OE#,  
ASTEL#  
INPUT  
OUTPUT ENABLE, ATA Select: Active low signal enabling read  
data from Attribute and Common memory area. To enable True IDE  
Mode this input should be grounded by the host.  
WE#  
INPUT  
WRITE ENABLE: Active low signal gating write data to the memory  
card. In true IDE Mode this input signal is not used and should be  
connected to Vcc.  
RDY/BSY#  
IREQ#  
INTRQ  
OUTPUT  
Ready/Busy, Interrupt Request: In I/O mode this signal is is  
IREQ# pin. The signal of low level indicates that the card is requesting  
software service to host, and high level indicate that the card is not  
requesting. In memory mode, the signal is set high when the ATA card  
is ready to accept new data transfer operation and held low when card  
is busy.  
At power up and at Reset, the RDY/BSY is low until (busy) until the  
card has completed its power up or reset function.  
Host should provide a pull up resistor  
CD1#, CD2#  
OUTPUT  
OUTPUT  
CARD DETECT 1 and 2: Provide card insertion detection. These  
signals are connected to ground internally on the memory card. The  
host socket interface circuitry shall supply 10K-ohm or larger pull-up  
resistors on these signal pins.  
Write Protect, 16 bit I/O port: In memory mode, WP is held low:  
always writable). In I/O mode , IOIS16# is asserted low when Task  
File Registers are accessed in 16 bit mode. In True IDE mOde this  
signal is asserted low when this device is expecting a word data transfer  
cycle.  
WP  
IOIS16#  
VPP1, VPP2  
N.C.  
PROGRAM/ERASE POWER SUPPLY: No Connection for ATA  
card.  
VCC  
GND  
CARD POWER SUPPLY: 5.0V for all internal circuitry.  
GROUND: for all internal circuitry.  
REG#  
INPUT  
INPUT  
ATTRIBUTE MEMORY SELECT: Used to enable access to  
Attribute space. Should be in high level during common memory area  
access. In True IDE Mode input signal is not used and should be  
connected to Vcc.  
Reset, Reset#: Active signal will clear all registers on the card (power  
on default). In True IDE Mode Reset# is the active low hardware reset  
from the host.  
Reset  
Reset#  
October 2001  
7
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Card Signal Description  
Symbol  
WAIT#  
Type  
OUTPUT  
Name and Function  
WAIT: This signal outputs low level for purpose of delaying memory  
or I/O access cycle. In True IDE Mode this signal can be used as  
IORDY.  
BVD2  
SPKR#  
DASP#  
Input/Output  
Input/Output  
Battery Voltage Detect 2, Data audio output, Disk active/slave  
present: In memory card mode, BVD2 is always high. In I/O mode,  
SPKR# is held high: no digital audio signals. In True IDE Mode  
DASP# is Disk Active/Slave Present signal in Master/Slave  
handshake protocol.  
Battery Voltage Detect 1, Status Change, Pass Diagnostic: In  
memory card mode BVD1 Is set to high level. In I/O mode  
STSCHNG# is used to alert the host to changes in Status registers. In  
True IDE mode PDIG is the Pass Diagnostic signal in Master/Slave  
handshake protocol.  
BVD1  
STSCHNG#  
PDIAG#  
VS1, VS2  
CSEL#  
OUTPUT  
Input  
VOLTAGE SENSE: Notifies the host socket of the card's VCC  
requirements. VS1 and VS2 are open to indicate a 5V, 16 bit card has  
been inserted.  
Card Select: This signal is not used in memory and I/O mode. With  
internal pull up resistor this signal is used to configure this card as  
Master or Slave when configured in True IDE Mode. When this pin is  
GND, selected Master config, when pin is open the card is configured  
as a Slave.  
INPACK#  
Output  
Input Acknowledge: This signal is not used in memory mode. It is  
asserted by the card when the card is selected and responding to an  
I/O read cycle at the address that is on the address bus. This signal is  
used for the input data buffer control. In True IDE Mode this signal is  
not used and should not be connected at the host.  
IORD#  
IOWR#  
Input  
Input  
I/O Read: is used for control of read data in Task File area. This card  
respond to this signal only in I/O interface mode  
I/O Write: is used for control of data write in Task File area. This card  
respond to this signal only in I/O interface mode  
October 2001  
8
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Card Function Explanation  
Register Construction  
§
Attribute Region  
·
Configuration Register  
¾ Configuration Option Register  
¾ Configuration and Status Register  
¾ Pin Replacement Register  
Socket and Copy Register  
¾
·
CIS (Card Information Structure)  
§
Task File Region  
Error Register  
Feature Register  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
Sector Count Register  
Sector Number Register  
Cylinder Low Register  
Cylinder High Register  
Drive/Head Register  
Status Register  
Command Register  
Disk Address Pointer  
Buffer RAM Size Control Register  
Host Interrupt Status Register  
Host Interrupt Enable Register  
ECC Control Register  
ECC 0-2 Registers  
DMA Control Register  
October 2001  
9
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
HOST ACCESS SPECIFICATION  
1. Attribute access specification  
When the CIS-ROM region or Configuration register region is accessed, read and write operations are  
executed under the condition of REG# = Low as follows. That region can be accessed by Byte/Word/Odd-  
byte modes which are defined by the PC card standard specification.  
Attribute Read Access Mode  
Mode  
REG# CE2# CE1# A0 OE# WE# D15 - D8  
D7 - D0  
High Z  
even byte  
invalid  
Standby Mode  
Byte access  
X
L
L
L
L
H
H
H
L
H
L
L
X
L
H
X
X
X
L
L
L
L
X
H
H
H
H
High Z  
High Z  
High Z  
invalid  
invalid  
Word access (16 bit)  
Odd Byte access (8 bit  
L
H
even byte  
High Z  
L
Attribute Write Access Mode  
Mode  
REG# CE2# CE1# A0 OE# WE# D15 - D8  
D7 - D0  
Standby Mode  
Byte access  
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
Don't care Don't care  
Don't care even byte  
Don't care Don't care  
Don't care even byte  
Don't care Don't care  
Word access (16 bit)  
Odd Byte access (8 bit  
L
October 2001  
10  
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
2. Task File register access specification  
There are two cases of Task File register mapping, one is the mapped I/O address area, the  
other is the Mapped Memory address area. Each case of the Task File register read and  
write operation is executed under the following conditions. The area can be accessed by  
Byte/Word/Odd Byte mode which is defined by the PC card standard specification.  
(a) I/O address map  
Task File Register Read Access Mode (a)  
Mode  
REG# CE2# CE1# A0 IORD# IOWR# OE# WE# D15 - D8  
D7 - D0  
High Z  
even byte  
odd byte  
even byte  
High Z  
Standby Mode  
Byte access  
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
High Z  
High Z  
High Z  
odd byte  
odd byte  
Word access (16 bit)  
Odd Byte access (8 bit  
L
Task File Register Write Access Mode (a)  
Mode  
REG# CE2# CE1# A0 IORD# IOWR# OE# WE# D15 - D8  
D7 - D0  
Standby Mode  
Byte access  
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
Don't care Don't care  
Don't care even byte  
Don't care  
odd byte  
odd byte  
odd byte  
even byte  
Don't care  
Word access (16 bit)  
Odd Byte access (8 bit  
L
(b) Memory address map  
Task File Register Read Access Mode (b)  
Mode  
REG# CE2# CE1# A0 IORD# IOWR# OE# WE# D15 - D8  
D7 - D0  
High Z  
even byte  
odd byte  
even byte  
High Z  
Standby Mode  
Byte access  
X
H
H
H
H
H
H
H
L
H
L
L
X
L
H
X
X
X
H
H
H
H
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
High Z  
High Z  
High Z  
Word access (16 bit)  
Odd Byte access (8 bit  
L
H
odd byte  
odd byte  
L
Task File Register Write Access Mode (b)  
Mode  
REG# CE2# CE1# A0 IORD# IOWR# OE# WE# D15 - D8  
D7 - D0  
Standby Mode  
Byte access  
X
H
H
H
H
H
H
H
L
H
L
L
X
L
H
X
X
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
X
L
L
L
L
Don't care Don't care  
Don't care even byte  
Don't care  
odd byte  
odd byte  
odd byte  
even byte  
Don't care  
Word access (16 bit)  
Odd Byte access (8 bit  
L
H
L
October 2001  
11  
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
3. True IDE mode  
The card can be configured in a True IDE Mode of operation. This card is configured in this mode  
only when the OE# input signal is asserted low by the host during the power off to power on cycle.  
In this True IDE Mode the PCMCIA protocol and configuration are disabled and only an I/O  
operation to the Task File registers is allowed. In this mode no Memory or Attribute registers are  
accessible to the host. The card permits 8 bit access if the user issues a Set feature Command to  
put the device in the 8 bit Mode.  
True IDE Mode Read I/O function  
Mode  
Invalid Mode  
Standby Mode  
Data Register Access  
All status access  
Other task file access  
CE2# CE1# A0..A2 IORD# IOWR# D15 - D8  
D7 - D0  
High Z  
High Z  
even byte  
status out  
data  
L
H
H
L
L
H
L
H
L
X
X
0h  
X
X
L
L
L
X
X
H
H
H
High Z  
High Z  
odd byte  
High Z  
High Z  
6h  
H
1-7h  
True IDE Mode Read I/O function  
Mode  
CE2# CE1# A0..A2 IORD# IOWR# D15 - D8  
D7 - D0  
Invalid Mode  
L
H
H
L
L
H
L
H
L
X
X
0h  
6h  
1-7h  
X
X
H
H
H
X
X
L
L
L
Don't care Don't care  
Don't care Don't care  
Standby Mode  
Data Register Access  
All status access  
Other task file access  
odd byte  
Don't care control in  
Don't care data  
even byte  
H
October 2001  
12  
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Configuration register specifications  
This card supports four Configuration registers for the purpose of the configuration and  
observation of this card.  
1. Configuration Option register (Address 200H)  
This register is used for the configuration of the card configuration status and for the issuing the  
soft reset to the card.  
bit7  
bit6  
bit5  
bit4  
bit3  
bit2  
bit1  
bit0  
SRESET  
LevlREQ  
INDEX  
Note: initial value: 00H  
Name  
R/W Function  
SRESET  
(HOST->)  
R/W Setting this bit to "1", places the card in the reset state (Card Hard Reset). This  
operation is equal to Hard Reset, except this bit is not cleared.
 
Then this bit is set to "0",  
places the card in the reset state of Hard Reset (This bit is set to "0" by Hard Reset) .  
Card configuration status is reset and the card internal initialized operation starts when  
Card Hard Reset is executed, so the next access to the card should be the same  
sequence as the power on sequence.  
LevlREQ  
(HOST->)  
R/W This bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode  
interrupt is selected.  
INDEX  
(HOST->)  
R/W This bit is used to select the operation mode of the card as follows.  
When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose  
of Memory card interface recognition.  
INDEX bit assignment  
INDEX bit  
5
0
0
0
0
4
0
0
0
0
3
0
0
0
0
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
Card mode  
Task File register address  
Mapping mode  
Memory card 0H to FH, 400H to 7FFH  
memory mapped  
I/O card  
I/O card  
I/O card  
xx0H toxxFH  
contiguous I/O mapped  
primary I/O mapped  
secondary I/O mapped  
1F0H to 1F7H, 3F6H to 3F7H  
170H to 177H, 376H to 377H  
October 2001  
13  
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
2. Configuration and Status register (Address 202H)  
This register is used for observing the card state.  
bit7  
bit6  
bit5  
bit4  
bit3  
bit2  
bit1  
bit0  
CHGED  
SIGCHG  
IOIS8  
0
0
PWD  
INTR  
0
Note: initial value: 00H  
Name  
R/W Function  
CHGED  
(CARD->)  
R
This bit indicates that the CRDY/-BSY bit on the Pin Replacement register is set to "1".  
When CHGED bit is set to "1", the -STSCHG pin is held "L" at the condition of SIGCHG  
bit set to "1" and the card configured for the I/O interface.  
SIGCHG  
(HOST->)  
R/W This bit is set or reset by the host for enabling and disabling the status-change signal (-  
STSCHG pin). When the card is configured I/O card interface and this bit is set to "1", -  
STSCHG pin is controlled by the CHGED bit. If this bit is set to "0", the -STSCHG pin is  
kept "H".  
IOIS8  
(HOST->)  
R/W The host sets this field to "1" when it can provide I/O cycles only with on 8 bit data bus  
(D7 to D0).  
PWD  
(HOST->)  
R/W When this bit is set to "1", the card enters the sleep state (Power Down mode). When  
this bit is reset to "0", the card transfers to the idle state (active mode). RRDY/-BSY bit  
on the Pin Replacement Register becomes BUSY when this bit is changed. RRDY/-  
BSY will not become Ready until the power state requested has been entered. This  
card automatically powers down when it is idle, and powers back up when it receives a  
command.  
INTR  
(CARD->)  
R
This bit indicates the internal state of the interrupt request. This bit state is available  
whether the I/O card interface has been configured or not.
 
This signal remains true until  
the condition which caused the interrupt request has been serviced. If interrupts are  
disabled by the -IEN bit in the Device Control Register, this bit is a zero.  
October 2001  
14  
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
3. Pin Replacement register (Address 204H)  
t7  
bit6  
bit5  
bit4  
bit3  
bit2  
bit1  
bit0  
0
0
CRDY/-BSY 0  
1
1
RRDY/-BSY 0  
Note: initial value: 0CH  
Name  
CRDY/-BSY R/W This bit is set to "1" when the RRDY/-BSY bit changes state. This bit may also be  
(HOST->) written by the host.  
RRDY/-BSY R/W When read, this bit indicates +READY pin states. When written, this bit is used for  
(HOST->) CRDY/-BSY bit masking.  
R/W Function  
4. Socket and Copy register (Address 206H)  
This register is used for identification of the card from the other cards. The host can read and  
write this register. This register should be set by the host before this card's Configuration Option  
register set.  
bit7  
bit6  
bit5  
bit4  
bit3  
bit2  
bit1  
bit0  
0
0
0
DRV#  
0
0
0
0
Note: initial value: 00H  
Name  
R/W Function  
R/W This field is used for the configuration of the plural cards.  
DRV#  
(HOST->)  
October 2001  
15  
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Sector Transfer Protocol  
1. Sector read: 1 sector read procedure after the card configured I/O interface is shown as follows.  
Start  
I/O Access index = 1  
Set the cylinder low / high register  
Set the head No. of drive head register  
(1) Set the logical sector number  
Set the sector number register  
Set “01H” in sector count register  
Set “20H” in command register  
(2)  
Read Status register  
(3)  
58H  
Read 256 times the data (512 bytes)  
(4) Burst data transfer  
Read Status register  
50H  
(5)  
Wait the command input  
(1)  
(2)  
(3)  
(4)  
(5)  
4H 5H 6H
 
3H 2H
 
7H  
7H  
7H  
0H  
0H  
7H 7H  
A0 to A10  
-CE1  
-CE2  
-IOWR  
-IORD  
01H20H 80H 58H (Transfer data)  
80H 50H  
D0 to D15  
-IREQ  
October 2001  
16  
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
2. Sector write: 1 sector write procedure after the card configured I/O interface is shown as follows  
Start  
I/O Access index = 1  
Set the cylinder low / high register  
Set the head No. of drive head register  
Set the sector number register  
Set “01H” in sector count register  
Set “30H” in command register  
(1) Set the logical sector number  
(2)  
Read Status register  
58H  
(3)  
Write 256 times the data (512 bytes)  
Read Status register  
(4) Burst data transfer  
50H  
(5)  
Wait the command input  
(1)  
(2)  
(3)  
(4)  
(5)  
4H 5H 6H
 
3H 2H
 
7H  
7H  
7H  
0H  
0H  
7H 7H  
A0 to A10  
-CE1  
-CE2  
-IOWR  
-IORD  
01H30H 80H 58H (data Transfer)  
80H 50H  
D0 to D15  
-IREQ  
October 2001  
17  
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
AC Characteristics  
Read Timing Parameters  
250ns  
Min  
SYM  
(PCMCIA)  
Parameter  
Max  
Unit  
tRC  
Read Cycle Time  
250  
ns  
ta(A)  
Address Access Time  
Card Enable Access Time  
Output Enable Access Time  
Address Setup Time  
250  
250  
150  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ta(CE)  
ta(OE)  
tsu(A)  
tsu(CE)  
th(A)  
30  
0
Card Enable Setup Time  
Address Hold Time  
20  
th(CE)  
tv(A)  
Card Enable Hold Time  
20  
0
Output Hold from Address  
Change  
tdis(CE)  
tdis(OE)  
tdis(CE)  
tdis(CE)  
Output Disable Time from CE#  
100  
100  
ns  
ns  
ns  
ns  
Output Disable Time from OE#  
Output Enable Time from CE#  
Output Enable Time from OE#  
5
5
Notes:  
1. AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications  
Read Timing Diagram  
tc(R)  
th(A)  
ta(A)  
A[25::0], /REG  
/CE1, /CE2  
tv(A)  
ta(CE)  
tsu(CE)  
NOTE 1  
NOTE 1  
th(CE)  
ta(OE)  
tsu(A)  
tdis(CE)  
/OE  
tdis(OE)  
ten(OE)  
D[15::0]  
DATA VALID  
Note 1: Signal may be high or low in this area  
October 2001  
18  
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Write Timing Parameters  
250ns  
Min  
SYM  
Parameter  
Max  
Unit  
(PCMCIA)  
tCW  
Write Cycle Time  
250  
150  
30  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tw(WE)  
Write Pulse Width  
tsu(A)  
Address Setup Time  
Address Setup Time for WE#  
tsu(A-WEH)  
180  
180  
80  
tsu(CE-WEH) Card Enable Setup Time for WE#  
tsu(D-WEH)  
th(D)  
Data Setup Time for WE#  
Data Hold Time  
30  
trec(WE)  
tdis(WE)  
tdis(OE)  
Write Recover Time  
30  
Output Disable Time from WE#  
Output Disable Time from OE#  
Output Enable Time from WE#  
Output Enable Time from OE#  
Output Enable Setup from WE#  
Output Enable Hold from WE#  
Card Enable Setup Time from OE#  
Card Enable Hold Time  
100  
100  
ten(WE)  
tdis(OE)  
5
5
tsu(OE-WE)  
th(OE-WE)  
tsu(CE)  
10  
10  
0
th(CE)  
20  
Notes:  
1. AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications  
Write Timing Diagram  
tc(W)  
A[25::0], /REG  
tsu(A-WEH)  
trec(WE)  
th(CE)  
tsu(CE-WEH)  
tsu(CE)  
/CE1, /CE2  
NOTE 1  
NOTE 1  
/OE  
th(OE-WE)  
th(D)  
tsu(A)  
tw(WE)  
/WE  
tsu(OE-WE)  
tsu(D-WEH)  
DATA INPUT  
D[15::0](Din)  
NOTE 2  
tdis(WE)  
tdis(OE)  
ten(OE)  
ten(WE)  
NOTE 2  
D[15::0]( Dout)  
Notes: 1)Signal may be high or low in this area  
2)When the data I/O pins are in the output state, no signals shall be applied to the  
data pins (D15 - D0) by the host system.  
October 2001  
19  
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
PRODUCT MARKING  
WED 7P512ATA3304C15 C995 9915  
EDI  
Date code  
Lot code / trace number  
Part number  
Company Name  
Note:  
Some products are currently marked with our pre-merger company name/acronym (EDI). During our  
transition period some products will also be marked with our new company name/acronym (WED). Starting  
October 2000 all PCMCIA products will be marked only with WED prefix.  
PART NUMBERING  
7P512ATA3303C15  
Card access time  
15  
25  
150ns  
250ns  
Temperature range  
C
I
Commercial 0C to +60 C  
Industrial -40C to +85C  
Packaging option  
03  
Standard, type 2  
Card family and version  
- see Card Family and Version Info. for details (next page)  
Card capacity  
512 512MB  
PC card  
P
Standard PCMCIA  
R
Ruggedized PCMCIA  
Card technology  
7
8
FLASH  
SRAM  
October 2001  
20  
ATA30 Series  
PC Card Products  
ATA PCMCIA Card  
ATA33 Series  
Ordering Information  
7P XXX ATA YY SS T ZZ  
where  
XXX:  
(032  
064  
128  
256  
384  
512  
640  
896  
1G0  
32MB) in the future  
64MB  
128MB  
256MB  
384MB  
512MB  
640MB  
896MB  
1024MB  
YY:  
SS:  
33  
Standard: 3.3V / 5V (Controller type = SD) NAND mem  
00  
01  
02  
03  
04  
05  
WEDC FLASH Logo,  
Blank Housing,  
Type I  
Type I  
Blank Housing,  
WEDC FLASH Logo,  
Type I Recessed  
Type II  
Blank Housing,  
Type II  
Blank Housing,  
Type II Recessed  
T:  
C
I
Commercial  
Industrial  
ZZ:  
25  
250ns  
Revision history:  
rev level  
rev 0  
rev 1  
description  
initial release  
final release  
date  
Sept 25, 2001  
Oct 25, 2001  
October 2001  
21  
ATA30 Series  
PC Card Products  
厂商 型号 描述 页数 下载

WEDC

 		7P001FEA0200C15 [ Flash Card, 1MX8, 150ns, CARD-68 ] 6 页

WEDC

 		7P001FEA0300C15 [ Flash Card, 1MX8, 150ns, CARD-68 ] 6 页

WEDC

 		7P001FLG0100C15 [ Flash Card, 512MX16, 150ns, CARD-68 ] 11 页

ETC

 		7P001FLG0100C20 周边其他\n[ Peripheral Miscellaneous ] 13 页

WEDC

 		7P001FLG0100I15 [ Flash Card, 512MX16, 150ns, CARD-68 ] 11 页

WEDC

 		7P001FLG0100I20 [ Flash Card, 512MX16, 200ns, CARD-68 ] 11 页

WEDC

 		7P001FLG0101C15 [ Flash Card, 512MX16, 150ns, CARD-68 ] 11 页

WEDC

 		7P001FLG0101C20 [ Flash Card, 512MX16, 200ns, CARD-68 ] 11 页

WEDC

 		7P001FLG0101I15 [ Flash Card, 512MX16, 150ns, CARD-68 ] 11 页

ETC

 		7P001FLG0101I20 周边其他\n[ Peripheral Miscellaneous ] 13 页

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