HYMP564S64(L)P8
PIN DESCRIPTION
Symbol
Type Polarity
Pin Description
The system clock inputs. All adress an commands lines are sampled on the cross point of the
rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
CK[1:0],
CK[1:0]
Cross
Point
Input
Input
Input
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
CKE[1:0]
Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
Active
Low
/S[1:0]
/RAS, /CAS, /
WE
Active
Low
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS and
WE define the operation to be excecuted by the SDRAM.
Input
Input
Input
BA[1:0]
Selects which DDR2 SDRAM internal bank of four or eight is activated.
Active
High
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 SDRAM
mode register.
ODT{1:0]
During a Bank Activate command cycle, difines the row address when sampled at the cross
point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle,
defines the column address when sampled at the cross point of the rising edge of CK and fall-
ing edge of CK. In addition to the column address, AP is used to invoke autoprecharge opera-
tion at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and
BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a
Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to
precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn
inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
A[9:0], A10/AP,
A[15:11]
Input
DQ[63:0]
DM[7:0]
In/Out
Input
Data Input/Output pins.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high.
In Read mode, DM lines have no effect.
Active
High
The data strobe, associated with one data byte, sourced whit data transfers. In Write mode,
the data strobe is sourced by the controller and is centered in the data window. In Read
mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of the data
window. DQS signals are complements, and timing is relative to the crosspoint of respective
DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals
must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed
approriately.
DQS[7:0],
DQS[7:0]
Cross
point
In/Out
VDD
VDDSPD,VSS
,
Supply
In/Out
Power supplies for core, I/O, Serial Presense Detect, and ground for the module.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister must
be connected to VDD to act as a pull up.
SDA
This signals is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from SCL to VDD to act as a pull up.
SCL
Input
Input
In/Out
SA[1:0]
TEST
Address pins used to select the Serial Presence Detect base address.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory mod-
ules(SODIMMs).
Rev. 0.1 / Jul. 2004
3
