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CYP32G0401DX-BGC

型号:

CYP32G0401DX-BGC

品牌:

CYPRESS[ CYPRESS ]

页数:

34 页

PDF大小:

538 K

PRELIMINARY  
CYP32G0401DX  
Multi-Gigabit Multi-Mode Quad HOTLink-III™ Transceiver  
Features  
Functional Description  
• Third-generation HOTLink® technology  
2488- to 3125-Mbps signaling rate per serial link  
XAUI/10G Ethernet compatible mode  
InfiniBandcompatible  
Programmable 8-bit or 10-bit SERDES  
Selectable 8B/10B encoding/decoding  
Ethernet PCS functions using the IEEE802.3z ordered  
set state machine  
Programmable receive framer provides alignment to  
A1/A2: SONET/SDH  
The CYP32G0401DX Quad HOTLink-IIITransceiver is a  
point-to-point communications building block allowing the  
transfer of data over high-speed serial links (optical fiber, bal-  
anced, and unbalanced copper transmission lines) at signaling  
speeds ranging from 2488 to 3125 Mbps per serial link.  
Each transmit channel accepts parallel characters in an Input  
Register, encodes each character for transport, and converts  
it to serial data. Each receive channel accepts serial data and  
converts it to parallel data, decodes the data into characters,  
and presents these characters to an output register. Figure 1  
illustrates typical connections between independent host sys-  
tems and corresponding CYP32G0401DX parts. As a third-  
generation HOTLink transceiver, the CYP32G0401DX ex-  
tends the HOTLink family with enhanced levels of integration,  
multi-gigabit data rates, and multi-mode versatility.  
8B/10B COMMA: Ethernet, InfiniBand, XAUI  
Synchronous SSTL_2 parallel input/output interface  
Internal PLLs with no external PLL components  
Differential CML serial inputs per channel  
Differential CML serial outputs per channel  
Source matched for 50transmission lines  
The transmit section of the CYP32G0401DX Quad HOTLink-  
III shown in Figure 2 consists of four channels. Each channel  
can accept either 8-bit data characters or pre-encoded 10-bit  
transmission characters. Data characters are passed from the  
Transmit Input Register to an embedded bypassable 8B/10B  
Encoder to improve their serial transmission characteristics.  
These encoded characters are then serialized and output from  
Current Mode Logic (CML) differential transmission-line driv-  
ers at a bit-rate which is a multiple of the input reference clock.  
No external bias resistors required  
Compatible with  
Fiber-optic modules  
Copper cables  
Circuit board traces  
The receive section of the CYP32G0401DX Quad HOTLink-III  
consists of four channels. Each channel accepts a serial bit-  
stream from a CML differential line receiver and, using a com-  
pletely integrated PLL Clock Synchronizer, recovers the timing  
information necessary for data reconstruction. Each recov-  
ered bit-stream is deserialized and framed into characters,  
8B/10B decoded, and checked for transmission errors. Recov-  
ered decoded characters are then written to an internal Elas-  
ticity Buffer, and presented to the destination host system. The  
integrated 8B/10B encoder/decoder may be bypassed for sys-  
tems that present externally encoded or scrambled data at the  
parallel interface.  
Diagnostic loop back and line loop back  
Signal detect input  
Low Power (2.5W typical)  
Single +2.5V VDD supply  
256-ball Thermally Enhanced BGA  
Commercial temperature range 0°C to +70°C  
Industrial temperature range 40°C to +85°C  
10  
10  
Serial Links  
10  
10  
10  
10  
10  
10  
10  
10  
10  
Serial Links  
10  
10  
10  
CYP32G0401DX  
CYP32G0401DX  
10  
10  
Serial Links  
Serial Links  
Backplane or  
Cabled  
Connections  
Figure 1. HOTLink-IIISystem Connections  
Cypress Semiconductor Corporation  
Document #: 38-02019 Rev. *C  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised November 7, 2001  
PRELIMINARY  
CYP32G0401DX  
The parallel I/O interface may be configured for numerous  
forms of clocking to provide the highest flexibility in system  
architecture. The receive interface may be configured to  
present data relative to a recovered clock (output) or to a local  
reference clock (input). The CYP32G0401DX is illustrated in  
greater detail in Figure 3.  
HOTLink-III devices are ideal for a variety of applications  
where parallel interfaces can be replaced with high-speed,  
point-to-point serial links. Some applications include intercon-  
necting workstations, backplanes, servers, mass storage, and  
video transmission equipment.  
x10  
x10  
x10  
x10  
x12  
x12  
x12  
x12  
Phase  
Align  
FIFO  
Phase  
Align  
FIFO  
Phase  
Align  
FIFO  
Phase  
Align  
FIFO  
Elasticity  
FIFO  
Elasticity  
FIFO  
Elasticity  
FIFO  
Elasticity  
FIFO  
Decoder  
8B/10B  
Decoder  
8B/10B  
Decoder  
8B/10B  
Encoder  
8B/10B  
Decoder  
8B/10B  
Encoder  
8B/10B  
Encoder  
8B/10B  
Encoder  
8B/10B  
Framer  
Framer  
Framer  
Framer  
Serializer  
Serializer  
Deserializer  
Deserializer  
Serializer  
Deserializer  
Serializer  
Deserializer  
RX  
RX  
RX  
RX  
TX  
TX  
TX  
TX  
Figure 2. CYP32G0401DX Transceiver Logic Block Diagram  
Document #: 38-02019 Rev. *C  
Page 2 of 34  
PRELIMINARY  
CYP32G0401DX  
Channel a  
TXD[7:0]  
TXEN  
8B/10B  
ENCODER  
PCS  
8
PAR  
TO  
SER  
PHASE ALIGN  
FIFO  
TXP  
LINE  
DRIVER  
TXER  
LAYER  
RE-TIME  
GTXCLK  
CI  
CO  
TXN  
CKI  
CKQ  
CLOCK  
RECOVERY  
DPLL  
8B/10B Bypass  
8
RXD[7:0]  
RXER  
RXDV  
CRS  
RXP  
ELASTICITY  
FIFO  
8B/10B  
DECODER  
PCS  
FRAME  
ALIGNMENT  
SER  
TO  
PAR  
LINE  
RCVR  
FRP  
CLK  
DATA  
RECOVERY  
LAYER  
RXN  
COL  
CLK  
RCLKIN  
CI  
CO  
OOF  
LOS  
POL  
LOSS  
OF  
SIGNAL  
TIMING  
DIVIDE  
RXCLK  
BY 8 or 10  
TCLKOUT  
MANAGEMENT  
INTERFACE/  
FRAME  
ENCODE  
SER8_10  
Channel b  
Channel c  
Channel d  
TIMING  
DIVIDE  
BY 8 or 10  
2
FRSYN[1:0]  
LBEN  
TEST  
MDIO  
TEST/  
AUTO-NEG  
MDC  
RESETN  
2
FREQUENCY  
SYNTHESIZER  
PHASE-LOCKED  
LOOP  
REFP  
REFN  
2
ANTEST[1:0]  
Figure 3. CYP32G0401DX Transceiver Block Diagram  
Document #: 38-02019 Rev. *C  
Page 3 of 34  
PRELIMINARY  
CYP32G0401DX  
Pin Configuration (Top View)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
DGND  
DGND  
DGND  
RCLKINc RXD2c RXCLKc GTXCLKc TXD5c DGND DGND TCLKOUT GTXCLKb DGND TXD4b RCLKINb RXD7b RXCLKb DGND  
DGND  
DGND  
A
B
C
D
E
F
DGND  
DGND  
DVDD  
DVDD  
RXDVc  
RXD7d  
RXD5d  
RXD2d  
RXD0d  
TXD1d  
TXD4d  
TXD7d  
TXENd  
TEST  
DVDD  
DVDD  
RXERc  
RXDVd  
RXD6d  
RXD3d  
RXD1d  
TXD0d  
TXD3d  
TXD6d  
DVDD  
RXD5c  
RXD7c  
DVDD  
RXD3c RXD0c  
RXD4c RXD1c  
TXD1c  
COLc  
DVDD  
TXD3c TXD7c TXENc  
TXD2c TXD6c TXERc  
TXD0c TXD4c DVDD  
VDIGCc  
TSYNC  
GDIGCc  
TXD0b  
TXD1b  
TXD2b TXD5b  
TXD3b TXD7b  
RXDVb  
TXENb  
TXERb  
RXD6b  
RXD5b  
RXERb  
RXD4b  
RXD3b  
DVDD  
COLb  
DVDD  
DVDD  
RXD2b  
CRSb  
DVDD  
DVDD  
RXD1b  
OOFa  
RXERa  
RXD4a  
CRSa  
DGND  
DGND  
RXD0b  
RXCLKa  
RXD7a  
RXD3a  
RCLKINa  
DGND  
DGND  
TXD1a  
TXD5a  
DGND  
VDIGCb  
TMS  
OOFd  
RXD6c  
CRSc  
GDIGCb TXD6b DVDD  
RXCLKd  
RXD4d  
RCLKINd  
DGND  
OOFc  
RXERd  
GDIGCd  
COLd  
OOFb  
RXDVa  
GDIGCa RXD6a  
G
H
J
RXD5a  
RXD1a  
DVDD  
TXD4a  
TXENa  
MDIO  
RXD2a  
RXD0a  
GTXCLKd  
TXD5d  
CRSd  
COLa  
TXD2d  
VDIGCd  
TXERd  
TXD0a GTXCLKa  
K
L
DGND  
TXD3a  
TXD7a  
TXERa  
VRXMb  
TRS  
TXD2a  
TXD6a  
VDIGCa  
MDC  
DGND  
M
N
P
R
T
RESETN  
FRSYN1 FRSYN0  
ANTEST0 ANTEST1 GTXMc  
AVDD  
GTXMd  
VRXMd  
AVDD  
AVDD  
REFP  
REFN  
VTXMc  
GRXMc  
VRXMc  
VTXMd  
VTXMb  
TCK  
GRXMa GTXMb  
TDI  
TDO  
GRXMd  
AGND  
AGND  
AGND  
ENCODE FRAME  
LOSd  
GRXDd  
POLd  
RXPd  
RXNc  
AVDD  
GRXDc  
VTXDd  
RXPc  
TXNd  
TXPd GTXDc  
VTXDb  
TXPb  
TXNa  
TXNb  
TXPa  
AVDD  
GRXDa GTXMa  
AVDD  
POLa  
VRXMa  
AVDD  
AVDD  
AGND  
LBEN  
AVDD  
AVDD  
AGND  
GRXMb  
AGND  
AGND  
AGND  
U
V
W
Y
AVDD  
AVDD  
AGND  
AVDD  
AVDD  
AGND  
SER8_10 LOSc  
GTXDd TXNc  
TXPc  
GTXDa GRXDb  
VTXDa VRXDb  
VRXDa  
RXNa  
RXPb  
LOSb  
RXPa  
POLb  
VRXDd  
POLc  
RXNd  
GFS3 VTXDc GFS1  
VFS2  
GTXDb  
AGND  
VTXMa  
LOSa  
VRXDc  
AGND  
VFS3  
VFS1  
AGND  
GFS2  
RXNb  
Document #: 38-02019 Rev. *C  
Page 4 of 34  
PRELIMINARY  
CYP32G0401DX  
Pin Configuration (Bottom View)  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
DGND  
DGND  
DGND RXCLKb RXD7b RCLKINb TXD4b DGND GTXCLKb TCLKOUT DGND DGND TXD5c GTXCLKc RXCLKc RXD2c RCLKINc  
DGND  
DGND  
DGND  
A
B
C
D
E
F
DGND  
DGND  
RXD0b  
RXCLKa  
RXD7a  
RXD3a  
RCLKINa  
DGND  
DGND  
TXD1a  
TXD5a  
DGND  
VDIGCb  
TMS  
DVDD  
DVDD  
RXD1b  
OOFa  
RXERa  
RXD4a  
CRSa  
DVDD  
DVDD  
RXD2b  
CRSb  
RXD4b  
RXD3b  
DVDD  
COLb  
RXD6b  
RXD5b  
RXERb  
RXDVb  
TXENb  
TXERb  
TXD5b TXD2b  
TXD7b TXD3b  
TXD0b  
TXD1b  
VDIGCc  
TSYNC  
GDIGCc  
TXENc TXD7c TXD3c  
TXERc TXD6c TXD2c  
DVDD TXD4c TXD0c  
TXD1c  
COLc  
DVDD  
RXD0c RXD3c  
RXD1c RXD4c  
RXD5c  
RXD7c  
DVDD  
DVDD  
DVDD  
RXERc  
RXDVd  
RXD6d  
RXD3d  
RXD1d  
TXD0d  
TXD3d  
TXD6d  
DVDD  
DVDD  
DVDD  
RXDVc  
RXD7d  
RXD5d  
RXD2d  
RXD0d  
TXD1d  
TXD4d  
TXD7d  
TXENd  
TEST  
DGND  
DGND  
DVDD TXD6b GDIGCb  
CRSc  
RXD6c  
OOFd  
OOFc  
RXCLKd  
RXD4d  
RCLKINd  
DGND  
RXDVa  
OOFb  
RXERd  
GDIGCd  
COLd  
RXD6a GDIGCa  
G
H
J
RXD2a  
RXD0a  
RXD5a  
RXD1a  
DVDD  
TXD4a  
TXENa  
MDIO  
COLa  
CRSd  
GTXCLKd  
TXD5d  
GTXCLKa TXD0a  
TXD2d  
VDIGCd  
TXERd  
K
L
TXD2a  
TXD6a  
VDIGCa  
MDC  
TXD3a  
TXD7a  
TXERa  
VRXMb  
TRS  
DGND  
DGND  
M
N
P
R
T
FRSYN0 FRSYN1  
RESETN  
AVDD  
AVDD  
GTXMd  
VRXMd  
AVDD  
GTXMc ANTEST1 ANTEST0  
TCK  
VTXMb  
VRXMc  
VTXMd  
VTXMc  
GRXMc  
REFP  
REFN  
TDO  
TDI  
GTXMb GRXMa  
GRXMb  
AGND  
AGND  
AGND  
LBEN  
AVDD  
AVDD  
AGND  
VRXMa  
AVDD  
AVDD  
AGND  
AVDD  
POLa  
GTXMa GRXDa  
AVDD  
TXPa  
TXNa  
TXNb  
VTXDb  
TXPb  
GTXDc TXPd  
TXNd  
AVDD  
GRXDc  
VTXDd  
RXPc  
GRXDd  
POLd  
RXPd  
RXNc  
LOSd  
FRAME ENCODE  
GRXMd  
AGND  
AGND  
AGND  
U
V
W
Y
LOSb  
RXPa  
POLb  
VRXDa  
RXNa  
RXPb  
GRXDb GTXDa  
VRXDb VTXDa  
TXPc  
TXNc GTXDd  
LOSc SER8_10  
AVDD  
AVDD  
AGND  
AVDD  
AVDD  
AGND  
VTXMa  
LOSa  
GTXDb  
AGND  
VFS2  
GFS1 VTXDc GFS3  
RXNd  
VRXDd  
POLc  
RXNb  
GFS2  
AGND  
VFS1  
VFS3  
AGND  
VRXDc  
Document #: 38-02019 Rev. *C  
Page 5 of 34  
PRELIMINARY  
CYP32G0401DX  
Static Discharge Voltage.................................................> 500 V  
(per JEDEC)  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-Up Current...........................................................> 200 mA  
Operating Range  
Ambient  
Storage Temperature..................................65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................55°C to +100°C  
Range  
Commercial  
Industrial  
Temperature  
0°C to +70°C  
40°C to +85°C  
VDD  
+2.5V ±5%  
+2.5V ±5%  
Supply Voltage to Ground Potential............... 0.5V to +3.0V  
DC Voltage Applied on Any Pin with Respect to Ground  
(with VDD in Normal Operating Range)....0.5V to VDD+0.5V  
Pin Descriptions  
[1]  
CYP32G0401DX Transmitter Pins (53)  
Pin  
Name  
Level  
I/O  
Description  
K18, L20  
L19, L18  
L17, M20  
M19, M18  
TXD0a, TXD1a  
TXD2a, TXD3a  
TXD4a, TXD5a  
TXD6a, TXD7a  
SSTL_2  
inputs  
Channel a transmit data in. The transmit data TXDa[7:0] are  
clocked into the Phase Align FIFO on the rising edge of the  
GTXCLKa signal. The data are read out of the Phase Align FIFO  
with TCLKOUT. The phase of GTXCLKa may differ from that of  
TCLKOUT by any amount. In MODE 1[1] the frequency of  
GTXCLKa may differ from that of TCLKOUT by up to 200 ppm.  
M17  
N18  
TXENa  
TXERa  
SSTL_2  
SSTL_2  
input  
input  
Channel a transmit enable (TXENa) in MODE 1  
Channel a transmit data bit 8 (TXD8a) in MODE 2  
Not used in MODE 3 (Suggest user drive to zero)  
Not used in MODE 4 (Suggest user drive to zero)  
Channel a transmit error (TXERa) in MODE 1  
Channel a transmit data bit 9 (TXD9a) in MODE 2  
Channel a transmit code-group select (TXKa) in MODE 3  
Not used in MODE 4 (Suggest user drive to zero)  
K19  
U13  
GTXCLKa  
TXPa  
SSTL_2  
CML  
input  
Channel a transmit clock. The rising edge of GTXCLKa clocks the  
input data into the Phase Align FIFO.  
output  
Channel a differential serial data transmit. TXPa is the positive  
differential output pin of the channel a Line Driver. The TXPa and  
TXNa look like a differential amplifier witheach of the output drains  
connected to VDD through a 50resistor.  
U12  
TXNa  
CML  
output  
inputs  
Channel a differential serial data transmit. TXNa is the negative  
differential output pin of the channel a Line Driver. The TXPa and  
TXNa look like a differential amplifier witheach of the output drains  
connected to VDD through a 50resistor.  
B12, C12  
B13, C13  
A14, B14  
D13, C14  
TXD0b, TXD1b  
TXD2b, TXD3b  
TXD4b, TXD5b  
TXD6b, TXD7b  
SSTL_2  
Channel b transmit data in. The transmit data TXDb[7:0] are  
clocked into the Phase Align FIFO on the rising edge of the GTX-  
CLKb signal. The data are read out of the Phase Align FIFO with  
TCLKOUT. The phase of GTXCLKb may differ from that of TCLK-  
OUT by any amount. In MODE 1 the frequency of GTXCLKb may  
differ from that of TCLKOUT by up to 200 ppm.  
C15  
D15  
TXENb  
SSTL_2  
SSTL_2  
SSTL_2  
input  
input  
input  
Channel b transmit enable (TXENb) in MODE 1  
Channel b transmit data bit 8 (TXD8b) in MODE 2  
Not used in MODE 3 (Suggest user drive to zero)  
Not used in MODE 4 (Suggest user drive to zero)  
TXERb  
Channel b transmit error (TXERb) in MODE 1  
Channel b transmit data bit 9 (TXD9b) in MODE 2  
Channel b transmit code-group Select (TXKb) in MODE 3  
Not used in MODE 4 (Suggest user drive to zero)  
A12  
GTXCLKb  
Channel b transmit clock. The rising edge of GTXCLKb clocks the  
input data into the Phase Align FIFO.  
Note:  
1. Transmitter pins are MODE-dependent where indicated. See Table 1 for defined MODES of operation.  
Document #: 38-02019 Rev. *C  
Page 6 of 34  
PRELIMINARY  
CYP32G0401DX  
Pin Descriptions  
CYP32G0401DX Transmitter Pins (53) (continued)  
[1]  
Pin  
Name  
Level  
I/O  
Description  
V11  
TXPb  
CML  
output  
Channel b differential Serial Data Transmit. TXPb is the positive  
differential output pin of the channel b Line Driver. The TXPb and  
TXNb look like a differential amplifier witheach of the output drains  
connected to VDD through a 50resistor.  
V12  
TXNb  
CML  
output  
inputs  
Channel b differential serial data transmit. TXNb is the negative  
differential output pin of the channel b Line Driver. The TXPb and  
TXNb look like a differential amplifier witheach of the output drains  
connected to VDD through a 50resistor.  
D8, B7  
C8, B8  
D9, A8  
C9, B9  
TXD0c, TXD1c  
TXD2c, TXD3c  
TXD4c, TXD5c  
TXD6c, TXD7c  
SSTL_2  
Channel c transmit data in. The transmit data TXDc[7:0] are  
clocked into the Phase Align FIFO on the rising edge of the GTX-  
CLKc signal. The data are read out of the Phase Align FIFO with  
TCLKOUT. The phase of GTXCLKc may differ from that of TCLK-  
OUT by any amount. In MODE 1 the frequency of GTXCLKc may  
differ from that of TCLKOUT by up to 200 ppm.  
B10  
C10  
TXENc  
TXERc  
SSTL_2  
SSTL_2  
input  
input  
Channel c transmit enable (TXENc) in MODE 1  
Channel c transmit data bit 8 (TXD8c) in MODE 2  
Not used in MODE 3 (Suggest user drive to zero)  
Not used in MODE 4 (Suggest user drive to zero)  
Channel c transmit error (TXERc) in MODE 1  
Channel c transmit data bit 9 (TXD9c) in MODE 2  
Channel c transmit code-group select (TXKc) in MODE 3  
Not used in MODE 4 (Suggest user drive to zero)  
A7  
GTXCLKc  
TXPc  
SSTL_2  
CML  
input  
Channel c transmit clock.The rising edge of GTXCLKc clocks the  
input data into the Phase Align FIFO.  
V10  
output  
Channel c differential serial data transmit. TXPc is the positive  
differential output pin of the channel c Line Driver. The TXPc and  
TXNc look like a differential amplifier with each of the output drains  
connected to VDD through a 50resistor.  
V9  
TXNc  
CML  
output  
inputs  
Channel c differential serial data transmit. TXNc is the negative  
differential output pin of the channel c Line Driver. The TXPc and  
TXNc look like a differential amplifier with each of the output drains  
connected to VDD through a 50resistor.  
J3, J2  
K4, K3  
K2, K1  
L3, L2  
TXD0d, TXD1d  
TXD2d, TXD3d  
TXD4d, TXD5d  
TXD6d, TXD7d  
SSTL_2  
Channel d transmit data in. The transmit data TXDd[7:0] are  
clocked into the Phase Align FIFO on the rising edge of the GTX-  
CLKd signal. The data are read out of the Phase Align FIFO with  
TCLKOUT. The phase of GTXCLKd may differ from that of  
TCLKOUT by any amount. In MODE 1 the frequency of GTXCLKd  
may differ from that of TCLKOUT by up to 200 ppm.  
M2  
M4  
TXENd  
TXERd  
SSTL_2  
SSTL_2  
input  
input  
Channel d transmit enable (TXENd) in MODE 1  
Channel d transmit data bit 8 (TXD8d) in MODE 2  
Not used in MODE 3 (Suggest user drive to zero)  
Not used in MODE 4 (Suggest user drive to zero)  
Channel d transmit error (TXERd) in MODE 1  
Channel d transmit data bit 9 (TXD9d) in MODE 2  
Channel d transmit code-group select (TXKd) in MODE 3  
Not used in MODE 4 (Suggest user drive to zero)  
J1  
GTXCLKd  
TXPd  
SSTL_2  
CML  
input  
Channel d transmit clock. The rising edge of GTXCLKd clocks the  
input data into the Phase Align FIFO.  
U9  
output  
Channel d differential serial data transmit. TXPd is the positive  
differential output pin of the channel d Line Driver. The TXPd and  
TXNd look like a differential amplifier witheach of the output drains  
connected to VDD through a 50resistor.  
Document #: 38-02019 Rev. *C  
Page 7 of 34  
PRELIMINARY  
CYP32G0401DX  
Pin Descriptions  
CYP32G0401DX Transmitter Pins (53) (continued)  
[1]  
Pin  
Name  
Level  
I/O  
Description  
U8  
TXNd  
CML  
output  
Channel d differential serial data transmit. TXNd is the negative  
differential output pin of the channel d Line Driver. The TXPd and  
TXNd look like a differential amplifier witheach of the output drains  
connected to VDD through a 50resistor.  
A11  
TCLKOUT  
SSTL_2  
output  
Reference transmit clock output. TCLKOUT is the word clock sig-  
nal used to clock data out of the Transmit Phase Align FIFOs of  
allfourchannels. TCLKOUTis deriveddirectlyfromtheFrequency  
Synthesizer output.  
[2]  
CYP32G0401DX Receiver Pins (76)  
Pin  
Name  
Level  
I/O  
Description  
J18, J17  
H18, G20  
G19, H17  
G18, F20  
RXD0a, RXD1a  
RXD2a, RXD3a  
RXD4a, RXD5a  
RXD6a, RXD7a  
SSTL_2  
outputs  
Channel a receive data. The receive data RXDa[7:0] are clocked  
out of the Elasticity FIFO by RCLKINa.  
[2]  
F19  
F18  
H19  
J19  
E20  
RXERa  
RXDVa  
CRSa  
SSTL_2  
SSTL_2  
SSTL_2  
SSTL_2  
SSTL_2  
output  
output  
output  
output  
output  
Channel a receive error (RXERa) in MODE 1  
Channel a receive data bit9 (RXD9a) in MODE 2  
Channel a receive invalid character flag (ERRa) in MODE 3  
Not used in MODE 4  
Channel a receive data valid (RXDVa) in MODE 1  
Channel a receive data bit8 (RXD8a) in MODE 2  
Channel a receive code-group select (RXKa) in MODE 3  
Not used in MODE 4  
Channel a receive carrier sense indicate (CRSa) in MODE 1  
Not used in MODE 2  
Channel a receive idle code (IDLEa) in MODE 3  
Channel a receive frame pulse flag (FRPa) in MODE 4  
COLa  
Channel a receive collision indicate (COLa) in MODE 1  
Not used in MODE 2  
Channel a receive invalid character flag (ERRa) in MODE 3  
Not used in MODE 4  
RXCLKa  
Channel a receive clock output reference. The RXCLKa pin out-  
puts either a buffered RCLKINa, or the recovered clock. This is  
determined by the status of LBEN on the rising edge of RESETN  
as follows: LBEN = 0 selects the buffered RCLKINa; LBEN = 1  
selects the recovered clock.  
E19  
OOFa  
SSTL_2  
input  
Not used in MODE 1  
Not used in MODE 2  
Not used in MODE 3  
Channel a OOF indicate in MODE 4  
H20  
RCLKINa  
RXPa  
SSTL_2  
CML  
input  
input  
Channel a receive Elasticity FIFO output clock. RCLKINa clocks  
the receive data RXDa[7:0], RXDVa, and RXERa out of the chan-  
nel a Elasticity FIFO.  
W16  
Channel a serial receive data, ext. ac coupled, int. bias. RXPa is  
the positive differential input pin of the channel a Line Receiver.  
The RXPa and RXNa look like a differential amplifier with each of  
the input pins connected to VDD/2 through a 150resistor. When  
inputs are differentially terminated with a 150resistor, the line  
termination is nominally 100Ω. See Figure 6.  
Note:  
2. Receiver pins are MODE-dependent where indicated. See Table 1 for defined MODES of operation.  
Document #: 38-02019 Rev. *C  
Page 8 of 34  
PRELIMINARY  
CYP32G0401DX  
[2]  
CYP32G0401DX Receiver Pins (76) (continued)  
Pin  
Name  
Level  
I/O  
Description  
W15  
RXNa  
CML  
input  
Channel a serial receive data, ext. ac coupled, int. bias. RXNa is  
the negative differential input pin of the channel a Line Receiver.  
The RXPa and RXNa look like a differential amplifier with each of  
the input pins connected to VDD/2 through a 150resistor. When  
inputs are differentially terminated with a 150resistor, the line  
termination is nominally 100Ω. See Figure 6.  
Y17  
LOSa  
LVPECL  
input  
Channel a receive loss of signal indicate. The signal input on the  
LOSa pin may come from a fiber module and indicates if there is  
a Loss of Signal (LOS) condition. If a LOS condition occurs, the  
data input is squelched and no data is sent to the data recovery  
block. When no data edges are present at the inputs to the clock  
recovery Digital Phase-Locked Loop (DPLL), its output frequency  
will be locked to the frequency of the transmit Frequency Synthe-  
sizer. The polarity of the LOSa signal is controlled by the POLa pin  
as shown in Table 4.  
V17  
POLa  
SSTL_2  
SSTL_2  
input  
Channel a receive loss of signal polarity. The POLa pin controls  
the polarity of the LOSa signal as shown in Table 4.  
D20, D19  
D18, C17  
B17, C16  
B16, A16  
RXD0b, RXD1b  
RXD2b, RXD3b  
RXD4b, RXD5b  
RXD6b, RXD7b  
outputs  
Channel b receive data. The receive data RXDb[7:0] are clocked  
out of the Elasticity FIFO by RCLKINb.  
D16  
B15  
E18  
E17  
A17  
RXERb  
RXDVb  
CRSb  
SSTL_2  
SSTL_2  
SSTL_2  
SSTL_2  
SSTL_2  
output  
output  
output  
output  
output  
Channel b receive error (RXERb) in MODE 1  
Channel b receive data bit9 (RXD9b) in MODE 2  
Channel b receive invalid character flag (ERRb) in MODE 3  
Not used in MODE 4  
Channel b receive data valid (RXDVb) in MODE 1  
Channel b receive data bit8 (RXD8b) in MODE 2  
Channel B receive code-group select (RXKb) in MODE 3  
Not used in MODE 4  
Channel b receive carrier sense indicate (CRSb) in MODE 1  
Not used in MODE 2  
Channel b receive idle code (IDLEb) in MODE 3  
Channel b receive frame pulse flag (FRPb) in MODE 4  
COLb  
Channel b receive collision indicate (COLb) in MODE 1  
Not used in MODE 2  
Channel b receive invalid character flag (ERRb) in MODE 3  
Not used in MODE 4  
RXCLKb  
Channel b receive clock output reference. The RXCLKb pin out-  
puts either a buffered RCLKINb, or the recovered clock. This is  
determined by the status of LBEN on the rising edge of RESETN  
as follows: LBEN = 0 selects the buffered RCLKINb; LBEN = 1  
selects the recovered clock.  
F17  
OOFb  
SSTL_2  
input  
Not used in MODE 1  
Not used in MODE 2  
Not used in MODE 3  
Channel b OOF indicate in MODE 4  
A15  
Y15  
RCLKINb  
RXPb  
SSTL_2  
CML  
input  
input  
Channel b receive Elasticity FIFO output clock. RCLKINb clocks  
the receive data RXDb[7:0], RXDVb, and RXERb out of the chan-  
nel b Elasticity FIFO.  
Channel b serial receive data, ext. ac coupled, int. bias. RXPb is  
the positive differential input pin of the channel b Line Receiver.  
The RXPb and RXNb look like a differential amplifier with each of  
the input pins connected to VDD/2 through a 150resistor. When  
inputs are differentially terminated with a 150resistor, the line  
termination is nominally 100Ω. See Figure 6.  
Document #: 38-02019 Rev. *C  
Page 9 of 34  
PRELIMINARY  
CYP32G0401DX  
[2]  
CYP32G0401DX Receiver Pins (76) (continued)  
Pin  
Name  
Level  
I/O  
Description  
Y14  
RXNb  
CML  
input  
Channel b serial receive data, ext. ac coupled, int. bias. RXNb is  
the negative differential input pin of the channel b Line Receiver.  
The RXPb and RXNb look like a differential amplifier with each of  
the input pins connected to VDD/2 through a 150resistor. When  
inputs are differentially terminated with a 150resistor, the line  
termination is nominally 100Ω. See Figure 6.  
V16  
LOSb  
LVPECL  
input  
Channel b receive loss of signal indicate. The signal input on the  
LOSb pin may come from a fiber module and indicates if there is  
a Loss of Signal (LOS) condition. If a LOS condition occurs, the  
data input is squelched and no data is sent to the data recovery  
block. When no data edges are present at the inputs to the clock  
recovery Digital Phase-Locked Loop (DPLL), its output frequency  
will be locked to the frequency of the transmit Frequency Synthe-  
sizer. The polarity of the LOSb signal is controlled by the POLb pin  
as shown in Table 4.  
Y16  
POLb  
SSTL_2  
SSTL_2  
input  
Channel b receive loss of signal polarity. The POLb pin controls  
the polarity of the LOSb signal as shown in Table 4.  
B6, C6  
A5, B5  
C5, B4  
D5, C4  
RXD0c, RXD1c  
RXD2c, RXD3c  
RXD4c, RXD5c  
RXD6c, RXD7c  
outputs  
Channel c receive data. The receive data RXDc[7:0] are clocked  
out of the Elasticity FIFO by RCLKINc.  
D3  
D2  
D6  
C7  
A6  
RXERc  
RXDVc  
CRSc  
SSTL_2  
SSTL_2  
SSTL_2  
SSTL_2  
SSTL_2  
output  
output  
output  
output  
output  
Channel c receive error (RXERc) in MODE 1  
Channel c receive data bit9 (RXD9c) in MODE 2  
Channel c receive invalid character flag (ERRc) in MODE 3  
Not used in MODE 4  
Channel c receive data valid (RXDVc) in MODE 1  
Channel c receive data bit8 (RXD8c) in MODE 2  
Channel c receive code-group select (RXKc) in MODE 3  
Not used in MODE 4  
Channel c receive carrier sense indicate (CRSc) in MODE 1  
Not used in MODE 2  
Channel c receive idle code (IDLEc) in MODE 3  
Channel c receive frame pulse flag (FRPc) in MODE 4  
COLc  
Channel c receive collision indicate (COLc) in MODE 1  
Not used in MODE 2  
Channel c receive invalid character flag (ERRc) in MODE 3  
Not used in MODE 4  
RXCLKc  
Channel c receive clock output reference. The RXCLKc pin out-  
puts either a buffered RCLKINc, or the recovered clock. This is  
determined by the status of LBEN on the rising edge of RESETN  
as follows: LBEN = 0 selects the buffered RCLKINc; LBEN = 1  
selects the recovered clock.  
E4  
OOFc  
SSTL_2  
input  
Not used in MODE 1  
Not used in MODE 2  
Not used in MODE 3  
Channel c OOF indicate in MODE 4  
A4  
Y7  
RCLKINc  
RXPc  
SSTL_2  
CML  
input  
input  
Channel c receive Elasticity FIFO output clock. RCLKINc clocks  
the receive data RXDc[7:0], RXDVc, and RXERc out of the chan-  
nel c Elasticity FIFO.  
Channel c serial receive data, ext. ac coupled, int. bias. RXPc is  
the positive differential input pin of the channel c Line Receiver.  
The RXPc and RXNc look like a differential amplifier with each of  
the input pins connected to VDD/2 through a 150resistor. When  
inputs are differentially terminated with a 150resistor, the line  
termination is nominally 100Ω. See Figure 6.  
Document #: 38-02019 Rev. *C  
Page 10 of 34  
PRELIMINARY  
CYP32G0401DX  
[2]  
CYP32G0401DX Receiver Pins (76) (continued)  
Pin  
Name  
Level  
I/O  
Description  
Y6  
RXNc  
CML  
input  
Channel c serial receive data, ext. ac coupled, int. bias. RXNc is  
the negative differential input pin of the channel c Line Receiver.  
The RXPc and RXNc look like a differential amplifier with each of  
the input pins connected to VDD/2 through a 150resistor. When  
inputs are differentially terminated with a 150resistor, the line  
termination is nominally 100Ω. See Figure 6.  
V5  
LOSc  
LVPECL  
input  
Channel c receive loss of signal indicate. The signal input on the  
LOSc pin may come from a fiber module and indicates if there is  
a Loss of Signal (LOS) condition. If a LOS condition occurs, the  
data input is squelched and no data is sent to the data recovery  
block. When no data edges are present at the inputs to the clock  
recovery Digital Phase-Locked Loop (DPLL), its output frequency  
will be locked to the frequency of the transmit Frequency Synthe-  
sizer. The polarity of the LOSc signal is controlled by the POLc pin  
as shown in Table 4.  
Y4  
POLc  
SSTL_2  
SSTL_2  
input  
Channel c receive loss of signal polarity. The POLc pin controls  
the polarity of the LOSc signal as shown in Table 4.  
H2, H3  
G2, G3  
F1, F2  
F3, E2  
RXD0d, RXD1d  
RXD2d, RXD3d  
RXD4d, RXD5d  
RXD6d, RXD7d  
outputs  
Channel d receive data. The receive data RXDd[7:0] are clocked  
out of the Elasticity FIFO by RCLKINd.  
F4  
E3  
J4  
RXERd  
RXDVd  
CRSd  
SSTL_2  
SSTL_2  
SSTL_2  
SSTL_2  
SSTL_2  
output  
output  
output  
output  
output  
Channel d receive error (RXERd) in MODE 1  
Channel d receive data bit9 (RXD9d) in MODE 2  
Channel d receive invalid character flag (ERRd) in MODE 3  
Not used in MODE 4  
Channel d receive data valid (RXDVd) in MODE 1  
Channel d receive data bit8 (RXD8d) in MODE 2  
Channel d receive code-group select (RXKd) in MODE 3  
Not used in MODE 4  
Channel d receive carrier sense indicate (CRSd) in MODE 1  
Not used in MODE 2  
Channel d receive idle code (IDLEd) in MODE 3  
Channel d receive frame pulse flag (FRPd) in MODE 4  
H4  
E1  
COLd  
Channel d receive collision indicate (COLd) in MODE 1  
Not used in MODE 2  
Channel d receive invalid character flag (ERRd) in MODE 3  
Not used in MODE 4  
RXCLKd  
Channel d receive clock output reference. The RXCLKd pin out-  
puts either a buffered RCLKINd, or the recovered clock. This is  
determined by the status of LBEN on the rising edge of RESETN  
as follows: LBEN = 0 selects the buffered RCLKINd; LBEN = 1  
selects the recovered clock.  
D1  
OOFd  
SSTL_2  
input  
Not used in MODE 1  
Not used in MODE 2  
Not used in MODE 3  
Channel d OOF indicate in MODE 4  
G1  
RCLKINd  
RXPd  
SSTL_2  
CML  
input  
input  
Channel d receive Elasticity FIFO output clock. RCLKINd clocks  
the receive data RXDd[7:0], RXDVd, and RXERd out of the chan-  
nel d Elasticity FIFO.  
W6  
Channel d serial receive data, ext. ac coupled, int. bias. RXPd is  
the positive differential input pin of the channel d Line Receiver.  
The RXPd and RXNd look like a differential amplifier with each of  
the input pins connected to VDD/2 through a 150resistor. When  
inputs are differentially terminated with a 150resistor, the line  
termination is nominally 100Ω. See Figure 6.  
Document #: 38-02019 Rev. *C  
Page 11 of 34  
PRELIMINARY  
CYP32G0401DX  
[2]  
CYP32G0401DX Receiver Pins (76) (continued)  
Pin  
Name  
Level  
I/O  
Description  
W5  
RXNd  
CML  
input  
Channel d serial receive data, ext. ac coupled, int. bias. RXNd is  
the negative differential input pin of the channel d Line Receiver.  
The RXPd and RXNd look like a differential amplifier with each of  
the input pins connected to VDD/2 through a 150resistor. When  
inputs are differentially terminated with a 150resistor, the line  
termination is nominally 100Ω. See Figure 6.  
U5  
LOSd  
LVPECL  
input  
Channel d receive loss of signal indicate. The signal input on the  
LOSd pin may come from a fiber module and indicates if there is  
a Loss of Signal (LOS) condition. If a LOS condition occurs, the  
data input is squelched and no data is sent to the data recovery  
block. When no data edges are present at the inputs to the clock  
recovery Digital Phase-Locked Loop (DPLL), its output frequency  
will be locked to the frequency of the transmit Frequency Synthe-  
sizer. The polarity of the LOSd signal is controlled by the POLd pin  
as shown in Table 4.  
V6  
POLd  
SSTL_2  
[3]  
input  
Channel d receive loss of signal polarity. The POLd pin controls  
the polarity of the LOSd signal as shown in Table 4.  
CYP32G0401DX Control pins (11)  
Pin  
Name  
Level  
I/O  
Description  
N1  
RESETN  
SSTL_2  
Bidir  
Chip global reset (active LOW bidirectional pull down). The  
RESETN pinreflects theoperationofthePowerOnReset(POR)  
circuit. When POR is active, RESETN is driven LOW. When  
POR is inactive, RESETN is three-stated and an internal pull-up  
resistor (approximately 50 k) establishes the inactive (HIGH)  
state. The RESETN pin may also be driven from an external  
device in order to re-initialize the chip regardless of the internal  
operating state and regardless of the state of POR. In this case  
RESETN must be driven LOW for a minimum of two cycles of  
the reference clock (REFP, REFN), though no other timing rela-  
tionship between RESETN and the reference clock need exist.  
P19  
N17  
MDC  
SSTL_2  
SSTL_2  
SSTL_2  
input  
Bidir  
input  
Management Interface Data Clock  
MDIO  
Management Interface Data Input/Output  
N4  
N3  
FRSYN0  
FRSYN1  
Frequency Synthesizer PLL ratio select. The FRSYN0 and  
FRSYN1 pins, together with the SER8_10 pin, select from the  
allowable reference clock frequency ranges for input to the fre-  
quency synthesizer. See Table 2.  
V4  
SER8_10  
ENCODE  
SSTL_2  
SSTL_2  
input  
input  
8-bit (SER8_10 = 1), 10-bit (SER8_10 = 0) data select.[3] The  
parallel-to-serial and serial-to-parallel converters operate in two  
modes, eight-bit and ten-bit, under the control of the SER8_10  
pin, as shown inTable 3. The 8-bit/10-bit selection made using  
the SER8_10 pin will also affect the choice of reference clock  
frequency range made using the FRSYN0 and FRSYN1 pins, as  
shown in Table 2.  
Encode select.[3] The 8B/10B encode and decode functions are  
enabled when ENCODE = 1. The encoder translates the 8-bit  
input byte to a 10-bit symbol for transmit, and the decoder trans-  
lates the received 10-bit symbol to the 8-bit byte originally en-  
coded at the other end. Both encode and decode functions are  
bypassed when ENCODE = 0.  
U2  
Note:  
3. The control pins SER8_10, ENCODE and FRAME together select the operating MODE. See Table 1 for defined operating MODES.  
Document #: 38-02019 Rev. *C  
Page 12 of 34  
PRELIMINARY  
CYP32G0401DX  
[3]  
CYP32G0401DX Control pins (11) (continued)  
Pin  
Name  
Level  
I/O  
Description  
U3  
FRAME  
SSTL_2  
input  
Frame select.[3] The Ethernet PCS functions are enabled when  
FRAME=1. This performs Ethernet PCS functions using the  
IEEE802.3z ordered set state machine (Section 36.2.5.2.1 and  
Figures 36-5 and 36-6) during transmit, and the receive and syn-  
chronization state machines (Section 36.2.5.2.2 and Figures 36-  
7a, 36-7b, 36-8, and 36-9) during receive.  
U19  
LBEN  
SSTL_2  
input  
Loop back enable. When loop back is enabled (LBEN = 1) both  
the high-speed line side data and the byte input data are looped  
back. The parallel input data (TXD[7:0], TXEN, TXER) are  
looped back to the receive side parallel data (RXD[7:0], RXDV,  
RXER), and the line-received data (RXP and RXN) are looped  
back and sent to the line driver (TXP and TXN). In MODE 1 the  
transmit driver (TXP, TXN) is disabled, as required in IEEE802.3  
Section 22.2.4.1.2. Note: LBEN is logically ORed with bit 0.14  
of the control register.  
R1  
T1  
REFP  
REFN  
CML  
CML  
input  
input  
Differential Frequency Synthesizer clock input, externally ac  
coupled, internally biased. REFP is the positive differential input  
pin for the reference clock (REFCLK) used by the frequency  
synthesizer. The REFP and REFN look like a differential ampli-  
fier with each of the input pins connected to 0.75xVDD through  
a 150resistor. See Table 7.  
Differential Frequency Synthesizer clock input, externally ac  
coupled, internally biased. REFN is the negative differential in-  
put pin for the reference clock (REFCLK) used by the frequency  
synthesizer. The REFP and REFN look like a differential ampli-  
fier with each of the input pins connected to 0.75xVDD through  
a 150resistor. See Table 7.  
CYP32G0401DX Analog Power Pins (65)  
Pin  
Y10  
W11  
Y9  
Name  
Function  
Description  
VFS1  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Frequency Synthesizer PLL VDD1  
Frequency Synthesizer PLL VDD2  
Frequency Synthesizer PLL VDD3  
Frequency Synthesizer PLL GND1  
Frequency Synthesizer PLL GND2  
Frequency Synthesizer PLL GND3  
Channel a transmit VDD1  
Channel a transmit VDD2  
Channel a transmit GND1  
Channel a transmit GND2  
Channel b transmit VDD1  
Channel b transmit VDD2  
Channel b transmit GND1  
Channel b transmit GND2  
Channel c transmit VDD1  
Channel c transmit VDD2  
Channel c transmit GND1  
Channel c transmit GND2  
Channel d transmit VDD1  
Channel d transmit VDD2  
Channel d transmit GND1  
VFS2  
VFS3  
W10  
Y13  
W8  
GFS1  
GFS2  
GFS3  
W13  
W17  
V13  
U16  
U11  
R17  
W12  
T18  
W9  
VTXDa  
VTXMa  
GTXDa  
GTXMa  
VTXDb  
VTXMb  
GTXDb  
GTXMb  
VTXDc  
VTXMc  
GTXDc  
GTXMc  
VTXDd  
VTXMd  
GTXDd  
R2  
U10  
P3  
W7  
T3  
V8  
Document #: 38-02019 Rev. *C  
Page 13 of 34  
PRELIMINARY  
CYP32G0401DX  
CYP32G0401DX Analog Power Pins (65) (continued)  
Pin  
Name  
GTXMd  
VRXDa  
VRXMa  
GRXDa  
GRXMa  
VRXDb  
VRXMb  
GRXDb  
GRXMb  
VRXDc  
VRXMc  
GRXDc  
GRXMc  
VRXDd  
VRXMd  
GRXDd  
GRXMd  
AVDD  
Function  
Description  
R4  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Analog Power  
Channel d transmit GND2  
Channel a receive VDD1  
Channel a receive VDD2  
Channel a receive GND1  
Channel a receive GND2  
Channel b receive VDD1  
Channel b receive VDD2  
Channel b receive GND1  
Channel b receive GND2  
Channel c receive VDD1  
Channel c receive VDD2  
Channel c receive GND1  
Channel c receive GND2  
Channel d receive VDD1  
Channel d receive VDD2  
Channel d receive GND1  
Channel d receive GND2  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog VDD  
General Analog GND  
General Analog GND  
General Analog GND  
General Analog GND  
General Analog GND  
General Analog GND  
General Analog GND  
General Analog GND  
General Analog GND  
General Analog GND  
General Analog GND  
General Analog GND  
General Analog GND  
V15  
U18  
U15  
T17  
W14  
P18  
V14  
U20  
Y5  
R3  
V7  
T2  
W4  
T4  
U6  
U1  
P4  
P17  
U4  
AVDD  
AVDD  
U7  
AVDD  
U14  
U17  
V2  
AVDD  
AVDD  
AVDD  
V3  
AVDD  
V18  
V19  
W2  
W3  
W18  
W19  
V1  
AVDD  
AVDD  
AVDD  
AVDD  
AVDD  
AVDD  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
V20  
W1  
W20  
Y1  
Y2  
Y3  
Y8  
Y11  
Y12  
Y18  
Y19  
Y20  
Document #: 38-02019 Rev. *C  
Page 14 of 34  
PRELIMINARY  
CYP32G0401DX  
CYP32G0401DX Digital Power Pins (42)  
Pin  
N19  
P20  
B11  
L4  
Name  
VDIGCa  
VDIGCb  
VDIGCc  
VDIGCd  
GDIGCa  
GDIGCb  
GDIGCc  
GDIGCd  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
DGND  
Function  
Description  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Digital Power  
Channel a Core VDD  
Channel b Core VDD  
Channel c Core VDD  
Channel d Core VDD  
Channel a Core GND  
Channel b Core GND  
Channel c Core GND  
Channel d Core GND  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring VDD  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
Digital IO Ring GND  
G17  
D12  
D11  
G4  
B2  
B3  
B18  
B19  
C2  
C3  
C18  
C19  
D4  
D7  
D10  
D14  
D17  
K17  
M3  
A1  
A2  
A3  
A9  
A10  
A13  
A18  
A19  
A20  
B1  
B20  
C1  
C20  
H1  
J20  
K20  
L1  
M1  
N20  
Document #: 38-02019 Rev. *C  
Page 15 of 34  
PRELIMINARY  
CYP32G0401DX  
CYP32G0401DX Cypress Test Pins (6) User Connect to Ground  
Pin  
R20  
R19  
T19  
R18  
N2  
Name  
Level  
I/O  
Description  
TMS  
-
-
-
-
-
-
-
-
-
-
-
-
User Connect to Ground  
User Connect to Ground  
User Connect to Ground  
User Connect to Ground  
User Connect to Ground  
User Connect to Ground  
TCK  
TDI  
TRS  
TEST  
TSYNC  
C11  
CYP32G0401DX Cypress Special Pins (3) N/C  
Pin  
Name  
Level  
I/O  
Description  
No Connection  
No Connection  
T20  
TDO  
-
-
-
-
P1  
P2  
ANTEST0  
ANTEST1  
Document #: 38-02019 Rev. *C  
Page 16 of 34  
PRELIMINARY  
CYP32G0401DX  
and Ethernet PCS functions. (SER8_10 = 0, ENCODE = 1,  
FRAME = 1).  
CYP32G0401DX HOTLink-III Operation  
The CYP32G0401DX is a highly configurable device designed  
to support reliable transfer of large quantities of data, using  
high-speed serial links. This device supports four single-byte  
or single-character channels.  
MODE 2 10-bit SERDES (no encoding/decoding; no  
framing)  
The transmit side accepts data in the form of 10-bit words at  
up to 312.5 Mwps, and serializes them into a bit stream trans-  
mitting at up to 3.125 Gbps. The receive side deserializes the  
data. No encoding/decoding or framing functions are per-  
formed. (SER8_10 = 0, ENCODE = 0, FRAME = 0).  
General Description  
The CYP32G0401DX is a fully integrated quad transceiver de-  
vice capable of operating at serial rates up to 3.125 Gbps per  
channel. The CYP32G0401DX has four operating modes:  
MODE 1 10-bit SERDES (Ethernet PCS functions; 8B/10B  
encoding/decoding; COMMA framing), MODE 2 10-bit SER-  
DES (no encoding/decoding; no framing), MODE 3 10-bit  
SERDES (8B/10B encoding/decoding; COMMA framing), and  
MODE 4 8-bit SERDES (no encoding/decoding; A1/A2 fram-  
ing). It performs the 8B/10B encode and decode functions  
compatible with the 10G Ethernet and InfiniBand physical lay-  
er, parallel-to-serial conversion, serial-to-parallel conversion,  
and clock recovery functions for use in LAN and WAN applica-  
tions. The Multi-Gigabit Multi-Mode versatility of the  
CYP32G0401DX was designed for backplane applications for  
WAN, LAN, WIN, and storage networksswitches and routers  
as well as for InfiniBand and XAUI 10G Ethernet port applica-  
tions.  
MODE 3 10-bit SERDES (8B/10B encoding/decoding;  
COMMA framing)  
The transmit side accepts data in the form of 8-bit bytes at up  
to 312.5 MBps, performs 8B/10B encoding, and serializes the  
encoded words into a bit stream transmitting at up to 3.125  
Gbps. The receive side deserializes the data, and performs  
COMMA framing and 8B/10B decoding. (SER8_10 = 0,  
ENCODE = 1, FRAME = 0).  
MODE 4 8-bit SERDES (no encoding/decoding; A1/A2  
framing)  
The transmit side accepts data in the form of 8-bit bytes at up  
to 350 MBps, and serializes them into a bit stream transmitting  
at up to 2.8 Gbps. The receive side deserializes the data and  
performs SONET/SDH A1/A2 framing. (SER8_10 = 1,  
ENCODE = 0, FRAME = 0).  
Functional Description  
Overview  
Table 1. CYP32G0401DX Operating Mode[4]  
Figure 4 shows a block diagram of a typical four-channel ap-  
plication. The transceiver has four defined modes of operation  
as shown in Table 1.  
SER  
MODE 8_10  
EN-  
CODE FRAME  
APPLICATION  
10 bit SERDES, 8B/10B  
encoding/decoding,  
COMMA framing,  
1
0
1
1
and PCS functions  
10 bit SERDES,  
no encoding/decoding,  
and no framing  
10 bit SERDES, 8B/10B  
encoding/decoding,  
and COMMA framing  
8 bit SERDES,  
no encoding/decoding,  
and A1/A2 framing  
CYP32G0401DX  
FIBER  
Tx  
2
3
0
0
1
0
1
0
0
0
0
P
A
R
A
L
L
E
L
a
b
Rx  
S
E
R
I
A
L
Tx  
Rx  
4
Tx  
Rx  
c
Note:  
D
A
T
4. Choose from four defined operating modes by setting variables SER8_10,  
ENCODE and FRAME. Selected mode applies to all four channels.  
D
A
T
Tx  
d
Rx  
A
Architecture Overview  
A
Figure3isablockdiagramshowingoneofthefourmulti-gigabit  
transceiver channels contained within the CYP32G0401DX.  
Also shown are the internal Management Interface and Fre-  
quency Synthesizer blocks, whicharecommon toall channels.  
Pin names are written in uppercase letters, with lowercase suf-  
fixes (a, b, c, d) applied later, as needed, to distinguish among  
the four channels. In generic cases, the lowercase suffix xwill  
be used to denote channels a, b, c, and d.  
Figure 4. Typical CYP32G0401DX  
Application Block Diagram  
MODE 1 10-bit SERDES(EthernetPCSfunctions; 8B/10B  
encoding/decoding; COMMA framing)  
The transmit side accepts data in the form of 8-bit bytes at up  
to 312.5 MBps, performs Ethernet PCS functions using the  
IEEE802.3z ordered set state machine, 8B/10B encoding and  
serialization of the encoded words into a serial bit stream  
transmitting at up to 3.125 Gbps. The receive side deserializes  
the data and performs COMMA framing, 8B/10B decoding,  
Frequency Synthesizer  
A Frequency Synthesizer PLL generates the low jitter transmit  
clock. This clock is derived from a low jitter reference frequen-  
cy applied differentially at pins REFP and REFN. The output  
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Page 17 of 34  
PRELIMINARY  
CYP32G0401DX  
frequency of the synthesizer is set to provide data output rates  
between 2.488 Gbps and 3.125 Gbps, and is a multiple of the  
reference clock frequency. Allowable reference clock frequen-  
cy ranges are selected by the SER8_10 and FRSYN[1:0] sig-  
nals, as shown in Table 2.  
forms Ethernet PCS functions using the IEEE802.3z ordered  
set state machine, Section 36.2.5.2.1 and Figures 36-5 and  
36-6.  
8B/10B Encoder  
The CYP32G0401DX contains an 8B/10B encoder to translate  
the 8-bit input byte to a 10-bit symbol. This function can be  
bypassed by setting ENCODE LOW. To facilitate alignment of  
the 10-bit word by the Receive FRAMER, a COMMA character  
may be generated. This is automatic when in MODE 1, or under  
the control of TXER (TXK) in MODE 3. The 8B/10B encoder is  
standards compliant with ANSI/NCITS ASC X3.230-1994 (Fi-  
bre Channel), IEEE 802.3z (Gigabit Ethernet), the IBM® ES-  
CON® and FICONchannels, and ATM Forum standards for  
data transport.  
Table 2. Frequency Synthesizer Selectable Input  
Frequency Range  
Selected Input  
Reference  
Frequency  
Range  
Data  
Output  
Rate  
TCLKOUT  
(MHz)  
(MHz)  
(Gbps)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
125156.25  
62.578.125  
31.2539.0625  
250312.5  
250312.5  
250312.5  
2.53.125  
2.53.125  
2.53.125  
Notation Conventions  
test modedo not use  
The 8B/10B transmission code uses letter notation for describ-  
ing the bits of an unencoded information octet and a single  
control variable. Each bit of the unencoded information octet  
contains either a binary zero or a binary one. A control vari-  
able, Z, has either the value D or the value K. When the control  
variable associated with an unencoded information octet con-  
tains the value D, the associated encoded code-group is re-  
ferred to as a data code-group. When the control variable as-  
sociated with an unencoded information octet contains the  
value K, the associated encoded code-group is referred to as  
a special code-group. The bit notation of A,B,C,D,E,F,G,H for  
an unencoded information octet is used in the description of  
the 8B/10B transmission code. The bits A,B,C,D,E,F,G,H are  
translated to bits a,b,c,d,e,i,f,g,h,j of 10-bit transmission code-  
groups. See Table 11 at the end of this document for the  
8B/10B code-group bit assignments, or refer to Table 36-1 of  
IEEE802.3. Each valid code-group has been given a name  
using the following convention: /Dx.y/ for the 256 valid data  
code-groups, and /Kx.y/ for special control code-groups,  
where x is the decimal value of bits EDCBA, and y is the dec-  
imal value of bits HGF.  
155.5175  
311-350  
311350  
311350  
2.4882.8  
2.4882.8  
2.4882.8  
77.7587.5  
38.87543.75  
test modedo not use  
The Frequency Synthesizer output is divided to produce a  
word clock signal that clocks data out of the Transmit Phase  
Align FIFO. This word clock is available at the TCLKOUT pin.  
The Frequency Synthesizer output also clocks data out of the  
parallel-to-serial converter.  
Transmit Phase Align FIFO  
The input data TXD[7:0], TXEN, and TXER are clocked into  
the Phase Align FIFO on the rising edge of the GTXCLK sig-  
nal. The data is read out of the FIFO with TCLKOUT. The  
phase of GTXCLK can differ from that of TCLKOUT with any  
difference and relative jitter absorbed by the FIFO. This is a  
10-bit wide by 64-word deep FIFO. Note: To minimize latency  
through the FIFO, only two data words need be input before  
data output from the FIFO begins.  
Valid special code-groups  
See Table 12 at the end of this document for the valid special  
code-groups, or refer to Table 36-2 of IEEE802.3.  
Parallel-to-Serial Converter  
The parallel-to-serial converter operates in two modes, eight-  
bit and ten-bit, under the control of the SER8_10 pin, as shown  
in Table 3.  
Loop back  
When loop back is enabled (LBEN = 1) both the high-speed  
line side data and the byte input data are looped back as fol-  
lows:  
Table 3. Serial Conversion Modes  
SER8_10 Signal  
Logic 1  
Serializer Function  
8 to 1  
The parallel input data (TXD[7:0], TXEN, TXER) is looped  
back to the receive side parallel data (RXD[7:0], RXDV,  
RXER)  
Logic 0  
10 to 1  
The line-received data (RXP and RXN) is looped back and  
sent to the line driver (TXP and TXN).  
In MODE 1 the transmit driver (TXP, TXN) is disabled, as  
required in IEEE802.3 Section 22.2.4.1.2.  
Note: The serializer always outputs data LSB first (Ethernet  
convention). However in MODE 4 the convention is to transmit  
MSB first. In order to conform to the desired standard, when  
the pin SER8_10 is active HIGH, data is presented to the se-  
rializer in reverse bit order; i.e., a data word presented at the  
TXD pins as {D7, D6, D5, D4, D3, D2, D1, D0} is presented to  
the serializer as {D0, D1, D2, D3, D4, D5, D6, D7}.  
Note: LBEN is logically ORed with bit 0.14 of the control reg-  
ister.  
Line Driver  
The line driver operates at CML levels, with the output pins  
TXP and TXN. Electrically, the TXP and TXN look like a differ-  
ential amplifier with each of its output drains connected to VDD  
through a 50resistor.  
Ethernet PCS Functions  
The Ethernet PCS functions are enabled (FRAME = 1) when-  
ever the CYP32G0401DX is operated in MODE 1. This per-  
Document #: 38-02019 Rev. *C  
Page 18 of 34  
PRELIMINARY  
CYP32G0401DX  
Line Receiver  
A1=0xF6 (8b11110110), A2=0x28 (8b00101000),  
A differential signal input on the input pins (RXP, RXN) will be  
recovered and converted into a binary stream by the receiver.  
The line receiver is internally biased, and should be capacitive-  
ly coupled to the driving stage. The RXP and RXN pins are  
inputs to a differential amplifier with each of the pins connected  
to VDD/2 through a 150resistor.  
where 0x indicates hexadecimal, and 8b indicates 8-bit  
binary.  
COMMA Framer  
In MODE 1 and MODE 3 the framing of the 10-bit symbol at the  
receive side is achieved by a barrel shifter as follows. Two  
sequential 10-bit symbols of the data are first loaded into the  
barrel shifter. When a COMMA character is detected at any  
alignment, that alignment is used to register the current data.  
Loss of Signal  
The signal input on the LOS pin may come from a fiber module  
and indicates if there is a Loss of Signal (LOS) condition. If a  
LOS condition occurs, the data input is squelched and no data  
is sent to the data recovery block. When no data edges are  
present at the inputs to the clock recovery Digital Phase-  
Locked Loop (DPLL), its output frequency will be locked to the  
frequency of the transmit Frequency Synthesizer. The polarity  
of the LOS signal is controlled by the POL pin as shown in  
Table 4.  
8B/10B Decoder  
The CYP32G0401DX contains an 8B/10B decoder to translate  
the 10-bit symbol to the 8-bit byte originally input to the encod-  
er at the other end. The data arrives at the decoder with the  
10-bit symbol having already been framed by the COMMA  
Framer as described above. The 8B/10B decode function can  
be bypassed by setting ENCODE LOW.  
Table 4. LOS Signal Polarity Control  
Ethernet PCS Functions  
POL  
LOS  
RX Data Path  
Enabled  
The Ethernet PCS functions are enabled (FRAME = 1) when-  
ever the CYP32G0401DX is operated in MODE 1. This per-  
forms Ethernet PCS functions using the IEEE802.3z receive  
and synchronization state machines, Section 36.2.5.2.2 and  
Figures 36-7a, 36-7b, 36-8, and 36-9.  
0
0
1
1
0
1
0
1
Disabled  
Disabled  
Enabled  
Serial-to-Parallel Converter  
The serial-to-parallel converter operates in two modes, eight-  
bit and ten-bit, under the control of the SER8_10 pin, as shown  
inTable 3.  
Clock and Data Recovery  
The input data is sent to a DPLL circuit, which recovers the  
clock. The data edges from the receiver are used to select a  
phase tapped from the transmit side Frequency Synthesizer.  
Any difference in frequency between the synthesizer and input  
data is accommodated by continually adjusting the phase that  
is tapped. This clock is used to determine the input signal to  
the deserializer.  
Receive Elasticity FIFO  
This is a 12-bit wide by 64-word deep FIFO used to absorb line  
input jitter and allow phase alignment to the selected output  
clock. The input data word comprises 10-bit data plus CRS  
and COL.  
Deserializer  
RXCLK Output  
The recovered data is converted into an 8-bit or 10-bit parallel  
word, with arbitrary alignment. The first bit received is as-  
signed to the least significant bit of that parallel word.  
The RXCLK pin outputs either a buffered RCLKIN, or the re-  
covered clock. This is determined by the status of LBEN on the  
rising edge of RESETN as follows: LBEN=0 selects the buff-  
ered RCLKIN; LBEN=1 selects the recovered clock.  
Data Framer  
Reset  
Note: The data input to this block from the deserializer is in an  
LSB firstformat (Ethernet style data). When in MODE 4 (indi-  
cated by SER8_10=1) the data alignment block reformats the  
incoming data word to follow the desired convention of MSB  
firsti.e., a data word presented by the deserializer as {0, 0,  
D7, D6, D5, D4, D3, D2, D1, D0} is reformatted to become {0,  
0, D0, D1, D2, D3, D4, D5, D6, D7}.  
An internal Power On Resetfunction (POR) ensures that fol-  
lowing the application of power at all supply pins of the  
CYP32G0401DX, all circuitry on the device is properly initial-  
ized and no external action is required for the device to com-  
mence operation. An external RESETN pin reflects the oper-  
ation of the POR circuit thus:  
When POR is active RESETN is driven LOW.  
A1/A2 Framer  
When POR is inactive RESETN is three-stated and an in-  
ternalpull up resistor (approximately 50k) establishes the  
inactive (HIGH) state.  
In MODE 4 when OOF is active (HIGH), framing is achieved as  
follows: The alignment state machine will search for the A1/A2  
framing sequence and when it is found, will pulse FRP for one  
cycle. The FRP output will appear on the CRS pin (MODE 4  
only). Also, the correctly realigned 8-bit word will be output. If  
OOF is inactive (low), the previous alignment will be used for  
the 8-bit word. The framing sequence will consist of 3 A1s  
followed by 3 A2s. The A1 and A2 characters used for framing  
are as follows:  
The RESETN pin may also be driven from an external device  
in order to re-initialize the chip regardless of the internal oper-  
ating state and regardless of the state of POR. In this case  
RESETN must be driven low for a minimum of two cycles of  
the reference clock (REFP, REFN), though no other timing re-  
lationship between RESETN and the reference clock need  
exist.  
Document #: 38-02019 Rev. *C  
Page 19 of 34  
PRELIMINARY  
CYP32G0401DX  
Built-In-Self-Test Mode (BIST)  
CYP32G0401DX is output on MDIO synchronously relative to  
MDC, and must be synchronously sampled externally.  
When operating in MODE 1 and with register 30.8 set, Built-In-  
Self-Test (BIST) mode is selected. In this mode a pseudo-ran-  
dom data sequence is continuously transmitted instead of the  
IDLE sequence (or any input data packet). The first character  
of this sequence is always the Start-of-packet, /S/ character  
(K27.7) which ensures that a receiver will recognize the data  
stream as a packet. The pseudo-random sequence is gener-  
ated by a 16-bit polynomial represented by Xn = Xn+15 EXOR  
MDC is an aperiodic signal with minimum HIGH and LOW  
times of 160 ns, and a minimum period of 400 ns. There are  
no maximum HIGH or LOW times for MDC.  
Table 5 identifies the available management interface regis-  
ters, and Table 6 provides the management frame format. The  
order of transmission is from left to right.  
Referring to Table 6:  
Xn+14  
.
PRE = Preamble (32 contiguous logic one bits)  
ST = Start of frame (01)  
A self-synchronizing comparator function incorporated within  
the FRAMER checks the incoming data stream against the ex-  
pected polynomial sequence and generates an error flag when  
a mismatch occurs. The error flag is logically ORed into the  
RXER output. The recovered pseudo-random sequence is  
also decoded and echoed on the RXD bus.  
OP = Operation code (Read = 10, Write = 01)  
PHYAD = PHY Address (Represented below as vwxyz)  
The PHYSICAL MDIO ADDRESS for the CYP32G0401DX is  
set at the end of reset. When RESETN goes HIGH the three  
signals ENCODE, FRAME and SER8_10 are locked in as the  
first three bits (vwx) of PHYAD (See Table 7). The last two bits  
(yz) identify the channel (See Table 8). For example, PHYAD  
= 11010 is the address for channel c for the case in which  
ENCODE = 1, FRAME = 1, and SER8_10 = 0 at the end of  
reset.  
Management Interface  
A management interface on the chip provides serial I/O capa-  
bilities as specified in IEEE802.3 Chapter 22. External access  
to the interface is made through two pins: the management  
data input/output pin, MDIO, and the management data clock  
input pin, MDC. Control and status information is serially trans-  
ferred to and from the CYP32G0401DX on MDIO, with refer-  
ence timing for the transfer supplied externally on MDC.  
REGAD = Register Address  
TA = Turnaround (delay for turn on/off of bus drivers)  
DATA = Data (16 bits, bit 15 transmitted first)  
IDLE = High impedance state on MDIO  
.
Control information must be input on MDIO synchronously rel-  
ative to MDC, allowing the CYP32G0401DX to sample it syn-  
chronously. In turn, status information from the  
Table 5. Management Interface Registers  
Register  
Description  
Default  
Register 0  
Register 1  
Register 2  
Register 3  
Register 4  
Register 5  
Register 6  
Register 15  
Register 30  
Register 31  
PHY control register (c.f. IEEE802.3 Table 22.7)  
0x3140  
0x0109  
0x000a  
0x3011  
0x0060  
0x0000  
0x0000  
0x0000  
0x0000  
0x0000  
PHY status register (c.f. IEEE802.3 Table 22.8)  
PHY identifier register upper bits (c.f. IEEE802.3 Figure 22.12)  
PHY identifier register lower bits (c.f. IEEE802.3 Figure 22.12)  
Autonegotiation advertisement register (c.f. IEEE802.3 Table 37.5)  
Autonegotiation partner ability register (c.f. IEEE802.3 Table 37.6)  
Autonegotiation expansion (c.f. IEEE802.3 Table 37.7)  
Extended status register (c.f. IEEE802.3 Table 22.9)  
Set BIT 8 = 1 for BIST (MODE 1 only). All other bits reserved.  
(RESERVED)  
Table 6. Management Frame Format[5]  
PRE  
11  
11  
ST  
01  
01  
OP  
10  
01  
PHYAD  
AAAAA  
AAAAA  
REGAD  
RRRRR  
RRRRR  
TA  
Z0  
10  
DATA  
IDLE  
READ  
DDDDDDDDDDDDDDDD  
DDDDDDDDDDDDDDDD  
Z
Z
WRITE  
Note:  
5. Z = high impedance on PHYs MDIO. It also occurs during READ TA as well as IDLE.  
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Page 20 of 34  
PRELIMINARY  
CYP32G0401DX  
Table 7. Chip Portion of PHYAD  
ENCODE FRAME SER8_10  
On Rising Edge of RESETN:  
First 3 Bits (vwx)  
VIH(min)  
VIL(max)  
Chip PHYAD  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
000  
001  
010  
011  
MDIO  
STA sourced  
100  
101  
VIH(min)  
10 ns min.  
VIL(max)  
110  
10 ns min.  
MDC  
111  
Table 8. Channel Portion of PHYAD  
Last 2 Bits (yz)  
Channel PHYAD  
Channel ID  
00  
01  
10  
11  
a
b
c
d
VIH(min)  
VIL(max)  
MDIO  
PHY sourced  
MDIO/MDC Timing Relationship  
0 ns min., 300 ns max.  
MDIO (Management Data Input/Output) is a bidirectional sig-  
nal that can be sourced by the Station Management Entity  
(STA) or the CYP32G0401DX. When the STA sources the  
MDIO signal, the STA shall provide a minimum of 10 ns of set-  
up time and a minimum of 10 ns of hold time referenced to the  
rising edge of MDC. When the MDIO signal is sourced by the  
CYP32G0401DX, it is sampled by the STA synchronously with  
respect to the rising edge of MDC. The clock to output delay  
from the CYP32G0401DX shall be a minimum of 0 ns and a  
maximum of 300ns. See Figure 5.  
Figure 5. MDIO/MDC Timing Relationship  
Internal  
External  
150  
RXP  
0.5xVDD  
150  
150  
INPUT  
SSTL_2 Outputs  
The SSTL_2 outputs meet the requirements of Section 3 of  
EIA/JESD8-9 for Class II outputs.  
RXN  
Line Receiver Requirements  
The line receiver is compatible with the line driver when capac-  
itively coupled and connected through a backplane of up to 19  
inches of properly terminated microstrip or stripline transmis-  
sion line on FR4. As shown in Figure 6, the RXP and RXN look  
like a differential amplifier with each of the input pins connect-  
ed to VDD/2 through a 150resistor. When inputs are differ-  
entially terminated with a 150resistor, the line termination is  
nominally 100Ω. Similarly the reference clock inputs, REFP  
and REFN, look like a differential amplifier with each of the  
input pins connected to 0.75xVDD through a 150resistor.  
This is shown in Figure 7.  
Figure 6. Receiver Input Termination  
Internal  
External  
150  
REFP  
0.75xVDD  
150  
150  
INPUT  
REFN  
Figure 7. Reference Clock Termination  
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PRELIMINARY  
CYP32G0401DX  
Line Driver Requirements  
with each of the output drains connected to VDD through a  
50resistor.  
The line driver has CML outputs which may be coupled to any  
fiber module. The TXP and TXN look like a differential amplifier  
CYP32G0401DX Operating Conditions  
Parameter  
Description  
Min.  
2.375  
40  
--  
Typ.  
2.5  
--  
Max.  
2.625  
85  
Unit  
VDD  
DC Supply Voltage  
V
TOP  
Operating Ambient Temperature Range  
Power Dissipation  
°C  
W
PDISS  
2.5  
--  
--  
VDDRIPPLE  
Ripple  
--  
50  
mV peak-to-peak  
CYP32G0401DX SSTL_2 Inputs[6]  
Parameter  
Description  
Min.  
Max.  
Unit  
V
[7]  
VREF  
Logic Reference Voltage  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current  
Low Level Input Current  
Pin Capacitance to ground  
0.5xVDD 5%  
0.5xVDD + 5%  
VIH  
VIL  
IIH  
1.56  
0.3  
--  
VDD + 0.3  
V
0.94  
40  
--  
V
µA  
µA  
pF  
IIL  
-600  
--  
CI  
4
[8]  
CYP32G0401DX SSTL_2 Outputs  
Parameter  
Description  
Min.  
Max.  
Unit  
V
[7]  
VREF  
Logic reference voltage  
High Level Output Voltage  
Low Level Output Voltage  
High level Output Current  
Low Level Output Current  
Pin Capacitance to ground  
0.5xVDD 5%  
0.5xVDD + 5%  
VOH  
VOL  
IOH  
0.75 x VDD  
VDD  
V
0
7.6  
--  
0.25 x VDD  
V
--  
7.6  
4
mA  
mA  
pF  
IOL  
CO  
--  
CYP32G0401DX Single Ended LVPECL Inputs  
Parameter  
Description  
Low Level Input Voltage  
High Level Input Voltage  
Min.  
Max.  
Unit  
V
VIL  
VIH  
VDD 2.0  
VDD 1.18  
VDD 1.47  
VDD 0.80  
V
CYP32G0401DX Differential Reference Clock Inputs (REFP, REFN) - Differential CML  
Parameter  
Description  
Common Mode Input Voltage  
Differential Input Voltage  
Input High Current  
Condition  
Min.  
0.65 x VDD  
175  
Max.  
0.85 x VDD  
2000  
2.0  
Unit  
VCM  
--  
V
[9]  
VIDIF  
|IIH|  
|IIL|  
--  
mV peak-to-peak  
VIDIF = 0.5V  
VIDIF = 0.5V  
--  
1.0  
mA  
mA  
%
Input Low Current  
1.0  
2.0  
Duty Cycle  
Percent Duty Cycle  
40  
60  
Notes:  
6. The inputs meet the requirements of Section 2.2 of EIA/JESD8-9.  
7. VREF is generated internally to the chip.  
8. The outputs meet the requirements of Section 3 of EIA/JESD8-9 for Class I outputs.  
9. AC coupled, with each input internally biased to 0.75xVDD through a 150resistor, as shown in Figure 7.  
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Page 22 of 34  
PRELIMINARY  
CYP32G0401DX  
CYP32G0401DX Transmit Data Input Timing  
Parameter  
Description  
Min.  
Max.  
Unit  
tTXDS  
Set-up time to GTXCLK rising  
TXD[7:0]x, TXENx, TXERx  
700  
--  
ps  
tTXDH  
Hold time from GTXCLK rising  
TXD[7:0]x, TXENx, TXERx  
200  
--  
ps  
tGTXCLKH  
tGTXCLKL  
tGTXCLK  
GTXCLKx high  
GTXCLKx low  
GTXCLKx period  
1.42  
1.42  
2.84  
--  
--  
--  
ns  
ns  
ns  
CYP32G0401DX Receive Data Output Timing  
Parameter  
Description  
Min.  
Max.  
Unit  
tRXDH  
Hold time with respect to RXCLKx rising  
RXD[7:0]X, RXERx, RXDVx, CRSx, COLx  
250  
--  
ps  
tRCLKINH  
tRCLKINL  
tRCLKIN  
RCLKINx high  
RCLKINx low  
RCLKINx period  
1.42  
1.42  
2.84  
--  
--  
--  
ns  
ns  
ns  
CYP32G0401DX RXPx-RXNx Line Receiver Inputs - Differential CML  
Parameter  
Description  
Common Mode Input Voltage  
Differential Input Voltage  
Input High Current  
Condition  
Min.  
0.4 x VDD  
175  
Max.  
Unit  
VCM  
--  
0.6 x VDD  
2000  
2.0  
V
VIDIF  
|IIH|  
--  
mV peak-to-peak  
VIDIF = 0.5V  
VIDIF = 0.5V  
--  
1.0  
mA  
mA  
dB  
|IIL|  
Input Low Current  
Input Return Loss[10]  
1.0  
2.0  
LOSSIR  
10  
--  
CYP32G0401DX TXPx-TXNx Line Driver Outputs - Differential CML  
PARAMETER  
DESCRIPTION  
Single Ended Output Voltage[11]  
Differential Output Voltage[11]  
Rise Time (10% to 90%)  
MIN  
400  
800  
110  
110  
MAX  
UNITS  
VoSE  
950  
1900  
200  
mV peak-to-peak  
VoDIFF  
tRISE  
mV peak-to-peak  
ps  
ps  
tFALL  
Fall Time (10% to 90%)  
200  
Notes:  
10. Using receiver input termination shown in Figure 6.  
11. Voltage swings measured with 100load AC coupled line to line.  
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PRELIMINARY  
CYP32G0401DX  
Switching Waveforms for the CYP32G0401DX Transmitter  
Transmit Interface Write Timing[12]  
tGTXCLK  
tGTXCLKH  
tGTXCLKL  
tTXDS  
GTXCLKx  
TXD[7:0]x  
TXENx  
TXERx  
tTXDH  
TCLKOUT Timing[13]  
FRSYN0 = 0  
FRSYN1 = 0  
tREFCLK  
tREFCLKL  
tREFCLKH  
tTCLKOUT  
REFLCK  
TCLKOUT  
FRSYN0 = 1  
FRSYN1 = 0  
tREFCLK  
tREFCLKL  
tREFCLKH  
REFLCK  
tTCLKOUT  
TCLKOUT  
FRSYN0 = 0  
FRSYN1 = 1  
tREFCLK  
tREFCLKL  
tREFCLKH  
REFLCK  
tTCLKOUT  
TCLKOUT  
Notes:  
12. Lowercase suffix xis used to denote channels a, b, c, and d.  
13. TCLKOUT is phase locked to REFCLK and is a multiple (2x, 4x, or 8x) of the REFCLK frequency. See Table 2 for further details.  
Document #: 38-02019 Rev. *C  
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PRELIMINARY  
CYP32G0401DX  
Switching Waveforms for the CYP32G0401DX Receiver  
Receive Interface Read Timing[14]  
tRCLKIN  
tRCLKINL  
tRCLKINH  
RCLKINx  
tRXDH  
RXD[7:0]x  
RXERx  
RXDVx  
CRSx  
COLx  
[14  
RXCLKx  
Note:  
14. RXCLKx is delayed in phase from RCLKINx.  
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PRELIMINARY  
CYP32G0401DX  
order, and the y is the decimal value of the binary number com-  
posed of the bits H, G, and F in that order. When c is set to K, xx  
and y are derived by comparing the encoded bit patterns of the  
Special Character to those patterns derived from encoded Valid  
Data bytes and selecting the names of the patterns most similar to  
the encoded bit patterns of the Special Character.  
ANSI X3.230 (FC-PH) Codes and Notation  
Information to be transmitted over a serial link is encoded 8  
bits at a time into a 10-bit Transmission Character and then  
sent serially, bit by bit. Information received over a serial link  
is collected ten bits at a time, and those Transmission Charac-  
ters that are used for data (Data Characters) are decoded into  
the correct eight-bit codes. The 10-bit Transmission Code sup-  
ports all 256 8-bit combinations. Some of the remaining Trans-  
mission Characters (Special Characters) are used for func-  
tions other than data transmission.  
Under the above conventions, the Transmission Character  
used for the examples above, is referred to by the name D5.2.  
The Special Character K29.7 is so named because the first six  
bits (abcdei) of this character make up a bit pattern similar to  
that resulting from the encoding of the unencoded 11101 pat-  
tern (29), and because the second four bits (fghj) make up a  
bit pattern similar to that resulting from the encoding of the  
unencoded 111 pattern (7).  
The primary rationale for use of a Transmission Code is to  
improve the transmission characteristics of a serial link. The  
encoding defined by the Transmission Code ensures that suf-  
ficient transitions are present in the serial bit stream to make  
clock recovery possible at the Receiver. Such encoding also  
greatly increases the likelihood of detecting any single or mul-  
tiple bit errors that may occur during transmission and recep-  
tion of information. In addition, some Special Characters of the  
Transmission Code selected by Fibre Channel Standard con-  
sist of a distinct and easily recognizable bit pattern (the Special  
Character COMMA) that assists a Receiver in achieving word  
alignment on the incoming bit stream.  
Note: This definition of the 10-bit Transmission Code is based  
on (and is in basic agreement with) the following references,  
which describe the same 10-bit transmission code.  
A.X. Widmer and P.A. Franaszek. A DC-Balanced, Parti-  
tioned-Block, 8B/10B Transmission CodeIBM Journal of Re-  
search and Development, 27, No. 5: 440451 (September, 1983).  
U.S. Patent 4,486,739. Peter A. Franaszek and Albert X. Wid-  
mer. Byte-Oriented DC Balanced (0.4) 8B/10B Partitioned  
Block Transmission Code(December 4, 1984).  
Notation Conventions  
Fibre Channel Physical and Signaling Interface (ANS X3.230−  
1994 ANSI FCPH Standard).  
The documentation for the 8B/10B Transmission Code uses  
letter notation for the bits in an 8-bit byte. Fibre Channel Stan-  
dard notation uses a bit notation of A, B, C, D, E, F, G, H for  
the 8-bit byte for the raw 8-bit data, and the letters a, b, c, d,  
e, i, f, g, h, j for encoded 10-bit data. There is a correspon-  
dence between bit A and bit a, B and b, C and c, D and d, E  
and e, F and f, G and g, and H and h. Bits i and j are derived,  
respectively, from (A,B,C,D,E) and (F,G,H).  
IBM Enterprise Systems Architecture/390 ESCON I/O Inter-  
face (document number SA227202).  
8B/10B Transmission Code  
The following information describes how the tables are used  
for both generating valid Transmission Characters (encoding)  
and checking the validity of received Transmission Characters  
(decoding). It also specifies the ordering rules to be followed  
when transmitting the bits within a character and the charac-  
ters within the higher-level constructs specified by the stan-  
dard.  
The bit labeled A in the description of the 8B/10B Transmission  
Code corresponds to bit 0 in the numbering scheme of the FC-  
2 specification, B corresponds to bit 1, as shown below.  
FC-2 bit designation—  
HOTLink D/Q designation7  
8B/10B bit designation—  
7
6
6
G F  
5
5
4
4
E
3
3
D
2
2
C
1
1
B
0
0
A
H
Transmission Order  
To clarify this correspondence, the following example shows  
the conversion from an FC-2 Valid Data Byte to a Transmission  
Character (using 8B/10B Transmission Code notation)  
Within the definition of the 8B/10B Transmission Code, the bit  
positions of the Transmission Characters are labeled a, b, c,  
d, e, i, f, g, h, j. Bit ais transmitted first followed by bits b, c,  
d, e, i, f, g, h, and j in that order. (Note that bit i is transmitted  
between bit e and bit f, rather than in alphabetical order.)  
FC-2 45  
Bits: 7654 3210  
0100 0101  
Valid and Invalid Transmission Characters  
Converted to 8B/10B notation (note carefully that the order of  
bits is reversed):  
The following tables define the valid Data Characters and valid  
Special Characters (K characters), respectively. The tables  
are used for both generating valid Transmission Characters  
(encoding) and checking the validity of received Transmission  
Characters (decoding). In the tables, each Valid-Data-byte or  
Special-Character-code entry has two columns that represent  
two (not necessarily different) Transmission Characters. The  
two columns correspond to the current value of the running  
disparity (Current RDor Current RD+). Running disparity  
is a binary parameter with either the value negative () or the  
value positive (+).  
Data Byte Name  
D5.2  
Bits:ABCDEFGH  
10100 010  
Translated to a transmission Character in the 8B/10B Trans-  
mission Code:  
Bits: abcdeifghj  
1010010101  
Each valid Transmission Character of the 8B/10B Transmis-  
sion Code has been given a name using the following conven-  
tion: cxx.y, where c is used to show whether the Transmission  
Character is a Data Character (c is set to D) or a Special Char-  
acter (c is set to K). When c is set to D, xx is the decimal value of  
the binary number composed of the bits E, D, C, B, and A in that  
After powering on, the Transmitter will assume a negative val-  
ue for its initial running disparity. Upon transmission of any  
Transmission Character, the transmitter selects the proper  
version of the Transmission Character based on the current  
running disparity value, and the Transmitter calculates a new  
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PRELIMINARY  
CYP32G0401DX  
value for its running disparity based on the contents of the  
transmitted character.  
transmitted. Table 9 shows naming notations and examples of  
valid transmission characters.  
After powering on, the Receiver may assume either a positive  
or negative value for its initial running disparity. Upon reception  
of any Transmission Character, the Receiver decides whether  
the Transmission Character is valid or invalid according to the  
following rules and tables and calculates a new value for its  
Running Disparity based on the contents of the received char-  
acter.  
Use of the Tables for Checking the Validity of Received  
Transmission Characters  
The column corresponding to the current value of the Receiv-  
ers running disparity is searched for the received Transmis-  
sion Character. If the received Transmission Character is  
found in the proper column, then the Transmission Character  
is valid and the associated Data byte or Special Character  
code is determined (decoded). If the received Transmission  
Character is not found in that column, then the Transmission  
Character is invalid. This is called a code violation. Indepen-  
dent of the Transmission Characters validity, the received  
Transmission Character is used to calculate a new value of  
running disparity. The new value is used as the Receivers  
current running disparity for the next received Transmission  
Character.  
The following rules for running disparity are used to calculate  
the new running-disparity value for Transmission Characters  
that have been transmitted (Transmitters running disparity)  
and that have been received (Receivers running disparity).  
Running disparity for a Transmission Character shall be calcu-  
lated from sub-blocks, where the first six bits (abcdei) form one  
sub-block and the second four bits (fghj) form the other sub-  
block. Running disparity at the beginning of the 6-bit sub-block  
is the running disparity at the end of the previous Transmission  
Character. Running disparity at the beginning of the 4-bit sub-  
block is the running disparity at the end of the 6-bit sub-block.  
Running disparity at the end of the Transmission Character is  
the running disparity at the end of the 4-bit sub-block.  
Table 9. Valid Transmission Characters  
Data  
DIN or QOUT  
Byte Name  
765  
43210  
Hex Value  
Running disparity for the sub-blocks are calculated as follows:  
1. Running disparity at the end of any sub-block is positive if  
the sub-block contains more ones than zeros. It is also pos-  
itive at the end of the 6-bit sub-block if the 6-bit sub-block  
is 000111, and it is positive at the end of the 4-bit sub-block  
if the 4-bit sub-block is 0011.  
D0.0  
000  
00000  
00  
D1.0  
D2.0  
000  
000  
00001  
00010  
01  
02  
2. Running disparity at the end of any sub-block is negative if  
the sub-block contains more zeros than ones. It is also neg-  
ative at the end of the 6-bit sub-block if the 6-bit sub-block  
is 111000, and it is negative at the end of the 4-bit sub-block  
if the 4-bit sub-block is 1100.  
.
.
.
.
.
.
.
.
D5.2  
010  
00010  
1
45  
3. Otherwise, running disparity at the end of the sub-block is  
the same as at the beginning of the sub-block.  
.
.
.
.
.
.
.
.
Use of the Tables for Generating Transmission Characters  
D30.7  
D31.7  
111  
111  
11110  
11111  
FE  
FF  
The appropriate entry in the table are found for the Valid Data  
byte or the Special Character byte for which a Transmission  
Character is to be generated (encoded). The current value of  
the Transmitters running disparity shall be used to select the  
Transmission Character from its corresponding column. For  
each Transmission Character transmitted, a new value of the  
running disparity shall be calculated. This new value shall be  
used as the Transmitters current running disparity for the next  
Valid Data byte or Special Character byte to be encoded and  
Detection of a code violation does not necessarily show that  
the Transmission Character in which the code violation was  
detected is in error. Code violations may result from a prior  
error that altered the running disparity of the bit stream which  
did not result in a detectable error at the Transmission Char-  
acter in which the error occurred. Table 10 shows an example  
of this behavior.  
Table 10. Code Violations Resulting from Prior Errors  
RD  
Character  
D21.1  
RD  
Character  
D10.2  
RD  
Character  
D23.5  
RD  
+
Transmitted data character  
Transmitted bit stream  
Bit stream after error  
101010 1001  
101010 1011  
D21.0  
010101 0101  
010101 0101  
D10.2  
111010 1010  
111010 1010  
Code Violation  
+
+
+
+
Decoded data character  
+
+
+
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PRELIMINARY  
CYP32G0401DX  
Table 11. Valid Data Characters (MODE 1 and MODE 3)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D0.0  
D1.0  
000 00000  
000 00001  
000 00010  
000 00011  
000 00100  
000 00101  
000 00110  
000 00111  
000 01000  
000 01001  
000 01010  
000 01011  
000 01100  
000 01101  
000 01110  
000 01111  
000 10000  
000 10001  
000 10010  
000 10011  
000 10100  
000 10101  
000 10110  
000 10111  
000 11000  
000 11001  
000 11010  
000 11011  
000 11100  
000 11101  
000 11110  
000 11111  
100111 0100 011000 1011  
011101 0100 100010 1011  
101101 0100 010010 1011  
110001 1011 110001 0100  
110101 0100 001010 1011  
101001 1011 101001 0100  
011001 1011 011001 0100  
111000 1011 000111 0100  
111001 0100 000110 1011  
100101 1011 100101 0100  
010101 1011 010101 0100  
110100 1011 110100 0100  
001101 1011 001101 0100  
101100 1011 101100 0100  
011100 1011 011100 0100  
010111 0100 101000 1011  
011011 0100 100100 1011  
100011 1011 100011 0100  
010011 1011 010011 0100  
110010 1011 110010 0100  
001011 1011 001011 0100  
101010 1011 101010 0100  
011010 1011 011010 0100  
111010 0100 000101 1011  
110011 0100 001100 1011  
100110 1011 100110 0100  
010110 1011 010110 0100  
110110 0100 001001 1011  
001110 1011 001110 0100  
101110 0100 010001 1011  
011110 0100 100001 1011  
101011 0100 010100 1011  
D0.1  
D1.1  
001 00000  
001 00001  
001 00010  
001 00011  
001 00100  
001 00101  
001 00110  
001 00111  
001 01000  
001 01001  
001 01010  
001 01011  
001 01100  
001 01101  
001 01110  
001 01111  
001 10000  
001 10001  
001 10010  
001 10011  
001 10100  
001 10101  
001 10110  
001 10111  
001 11000  
001 11001  
001 11010  
001 11011  
001 11100  
001 11101  
001 11110  
001 11111  
100111 1001 011000 1001  
011101 1001 100010 1001  
101101 1001 010010 1001  
110001 1001 110001 1001  
110101 1001 001010 1001  
101001 1001 101001 1001  
011001 1001 011001 1001  
111000 1001 000111 1001  
111001 1001 000110 1001  
100101 1001 100101 1001  
010101 1001 010101 1001  
110100 1001 110100 1001  
001101 1001 001101 1001  
101100 1001 101100 1001  
011100 1001 011100 1001  
010111 1001 101000 1001  
011011 1001 100100 1001  
100011 1001 100011 1001  
010011 1001 010011 1001  
110010 1001 110010 1001  
001011 1001 001011 1001  
101010 1001 101010 1001  
011010 1001 011010 1001  
111010 1001 000101 1001  
110011 1001 001100 1001  
100110 1001 100110 1001  
010110 1001 010110 1001  
110110 1001 001001 1001  
001110 1001 001110 1001  
101110 1001 010001 1001  
011110 1001 100001 1001  
101011 1001 010100 1001  
D2.0  
D2.1  
D3.0  
D3.1  
D4.0  
D4.1  
D5.0  
D5.1  
D6.0  
D6.1  
D7.0  
D7.1  
D8.0  
D8.1  
D9.0  
D9.1  
D10.0  
D11.0  
D12.0  
D13.0  
D14.0  
D15.0  
D16.0  
D17.0  
D18.0  
D19.0  
D20.0  
D21.0  
D22.0  
D23.0  
D24.0  
D25.0  
D26.0  
D27.0  
D28.0  
D29.0  
D30.0  
D31.0  
D10.1  
D11.1  
D12.1  
D13.1  
D14.1  
D15.1  
D16.1  
D17.1  
D18.1  
D19.1  
D20.1  
D21.1  
D22.1  
D23.1  
D24.1  
D25.1  
D26.1  
D27.1  
D28.1  
D29.1  
D30.1  
D31.1  
Document #: 38-02019 Rev. *C  
Page 28 of 34  
PRELIMINARY  
CYP32G0401DX  
Table 11. Valid Data Characters (MODE 1 and MODE 3) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D0.2  
D1.2  
010 00000  
010 00001  
010 00010  
010 00011  
010 00100  
010 00101  
010 00110  
010 00111  
010 01000  
010 01001  
010 01010  
010 01011  
010 01100  
010 01101  
010 01110  
010 01111  
010 10000  
010 10001  
010 10010  
010 10011  
010 10100  
010 10101  
010 10110  
010 10111  
010 11000  
010 11001  
010 11010  
010 11011  
010 11100  
010 11101  
010 11110  
010 11111  
100111 0101 011000 0101  
011101 0101 100010 0101  
101101 0101 010010 0101  
110001 0101 110001 0101  
110101 0101 001010 0101  
101001 0101 101001 0101  
011001 0101 011001 0101  
111000 0101 000111 0101  
111001 0101 000110 0101  
100101 0101 100101 0101  
010101 0101 010101 0101  
110100 0101 110100 0101  
001101 0101 001101 0101  
101100 0101 101100 0101  
011100 0101 011100 0101  
010111 0101 101000 0101  
011011 0101 100100 0101  
100011 0101 100011 0101  
010011 0101 010011 0101  
110010 0101 110010 0101  
001011 0101 001011 0101  
101010 0101 101010 0101  
011010 0101 011010 0101  
111010 0101 000101 0101  
110011 0101 001100 0101  
100110 0101 100110 0101  
010110 0101 010110 0101  
110110 0101 001001 0101  
001110 0101 001110 0101  
101110 0101 010001 0101  
011110 0101 100001 0101  
101011 0101 010100 0101  
D0.3  
D1.3  
011 00000  
011 00001  
011 00010  
011 00011  
011 00100  
011 00101  
011 00110  
011 00111  
011 01000  
011 01001  
011 01010  
011 01011  
011 01100  
011 01101  
011 01110  
011 01111  
011 10000  
011 10001  
011 10010  
011 10011  
011 10100  
011 10101  
011 10110  
011 10111  
011 11000  
011 11001  
011 11010  
011 11011  
011 11100  
011 11101  
011 11110  
011 11111  
100111 0011 011000 1100  
011101 0011 100010 1100  
101101 0011 010010 1100  
110001 1100 110001 0011  
110101 0011 001010 1100  
101001 1100 101001 0011  
011001 1100 011001 0011  
111000 1100 000111 0011  
111001 0011 000110 1100  
100101 1100 100101 0011  
010101 1100 010101 0011  
110100 1100 110100 0011  
001101 1100 001101 0011  
101100 1100 101100 0011  
011100 1100 011100 0011  
010111 0011 101000 1100  
011011 0011 100100 1100  
100011 1100 100011 0011  
010011 1100 010011 0011  
110010 1100 110010 0011  
001011 1100 001011 0011  
101010 1100 101010 0011  
011010 1100 011010 0011  
111010 0011 000101 1100  
110011 0011 001100 1100  
100110 1100 100110 0011  
010110 1100 010110 0011  
110110 0011 001001 1100  
001110 1100 001110 0011  
101110 0011 010001 1100  
011110 0011 100001 1100  
101011 0011 010100 1100  
D2.2  
D2.3  
D3.2  
D3.3  
D4.2  
D4.3  
D5.2  
D5.3  
D6.2  
D6.3  
D7.2  
D7.3  
D8.2  
D8.3  
D9.2  
D9.3  
D10.2  
D11.2  
D12.2  
D13.2  
D14.2  
D15.2  
D16.2  
D17.2  
D18.2  
D19.2  
D20.2  
D21.2  
D22.2  
D23.2  
D24.2  
D25.2  
D26.2  
D27.2  
D28.2  
D29.2  
D30.2  
D31.2  
D10.3  
D11.3  
D12.3  
D13.3  
D14.3  
D15.3  
D16.3  
D17.3  
D18.3  
D19.3  
D20.3  
D21.3  
D22.3  
D23.3  
D24.3  
D25.3  
D26.3  
D27.3  
D28.3  
D29.3  
D30.3  
D31.3  
Document #: 38-02019 Rev. *C  
Page 29 of 34  
PRELIMINARY  
CYP32G0401DX  
Table 11. Valid Data Characters (MODE 1 and MODE 3) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D0.4  
D1.4  
100 00000  
100 00001  
100 00010  
100 00011  
100 00100  
100 00101  
100 00110  
100 00111  
100 01000  
100 01001  
100 01010  
100 01011  
100 01100  
100 01101  
100 01110  
100 01111  
100 10000  
100 10001  
100 10010  
100 10011  
100 10100  
100 10101  
100 10110  
100 10111  
100 11000  
100 11001  
100 11010  
100 11011  
100 11100  
100 11101  
100 11110  
100 11111  
100111 0010 011000 1101  
011101 0010 100010 1101  
101101 0010 010010 1101  
110001 1101 110001 0010  
110101 0010 001010 1101  
101001 1101 101001 0010  
011001 1101 011001 0010  
111000 1101 000111 0010  
111001 0010 000110 1101  
100101 1101 100101 0010  
010101 1101 010101 0010  
110100 1101 110100 0010  
001101 1101 001101 0010  
101100 1101 101100 0010  
011100 1101 011100 0010  
010111 0010 101000 1101  
011011 0010 100100 1101  
100011 1101 100011 0010  
010011 1101 010011 0010  
110010 1101 110010 0010  
001011 1101 001011 0010  
101010 1101 101010 0010  
011010 1101 011010 0010  
111010 0010 000101 1101  
110011 0010 001100 1101  
100110 1101 100110 0010  
010110 1101 010110 0010  
110110 0010 001001 1101  
001110 1101 001110 0010  
101110 0010 010001 1101  
011110 0010 100001 1101  
101011 0010 010100 1101  
D0.5  
D1.5  
101 00000  
101 00001  
101 00010  
101 00011  
101 00100  
101 00101  
101 00110  
101 00111  
101 01000  
101 01001  
101 01010  
101 01011  
101 01100  
101 01101  
101 01110  
101 01111  
101 10000  
101 10001  
101 10010  
101 10011  
101 10100  
101 10101  
101 10110  
101 10111  
101 11000  
101 11001  
101 11010  
101 11011  
101 11100  
101 11101  
101 11110  
101 11111  
100111 1010 011000 1010  
011101 1010 100010 1010  
101101 1010 010010 1010  
110001 1010 110001 1010  
110101 1010 001010 1010  
101001 1010 101001 1010  
011001 1010 011001 1010  
111000 1010 000111 1010  
111001 1010 000110 1010  
100101 1010 100101 1010  
010101 1010 010101 1010  
110100 1010 110100 1010  
001101 1010 001101 1010  
101100 1010 101100 1010  
011100 1010 011100 1010  
010111 1010 101000 1010  
011011 1010 100100 1010  
100011 1010 100011 1010  
010011 1010 010011 1010  
110010 1010 110010 1010  
001011 1010 001011 1010  
101010 1010 101010 1010  
011010 1010 011010 1010  
111010 1010 000101 1010  
110011 1010 001100 1010  
100110 1010 100110 1010  
010110 1010 010110 1010  
110110 1010 001001 1010  
001110 1010 001110 1010  
101110 1010 010001 1010  
011110 1010 100001 1010  
101011 1010 010100 1010  
D2.4  
D2.5  
D3.4  
D3.5  
D4.4  
D4.5  
D5.4  
D5.5  
D6.4  
D6.5  
D7.4  
D7.5  
D8.4  
D8.5  
D9.4  
D9.5  
D10.4  
D11.4  
D12.4  
D13.4  
D14.4  
D15.4  
D16.4  
D17.4  
D18.4  
D19.4  
D20.4  
D21.4  
D22.4  
D23.4  
D24.4  
D25.4  
D26.4  
D27.4  
D28.4  
D29.4  
D30.4  
D31.4  
D10.5  
D11.5  
D12.5  
D13.5  
D14.5  
D15.5  
D16.5  
D17.5  
D18.5  
D19.5  
D20.5  
D21.5  
D22.5  
D23.5  
D24.5  
D25.5  
D26.5  
D27.5  
D28.5  
D29.5  
D30.5  
D31.5  
Document #: 38-02019 Rev. *C  
Page 30 of 34  
PRELIMINARY  
CYP32G0401DX  
Table 11. Valid Data Characters (MODE 1 and MODE 3) (continued)  
Data  
Byte  
Data  
Byte  
Bits  
Current RD−  
Current RD+  
abcdei fghj  
Bits  
Current RD−  
abcdei fghj  
Current RD+  
abcdei fghj  
Name HGF EDCBA  
abcdei fghj  
Name HGF EDCBA  
D0.6  
D1.6  
110 00000  
110 00001  
110 00010  
110 00011  
110 00100  
110 00101  
110 00110  
110 00111  
110 01000  
110 01001  
110 01010  
110 01011  
110 01100  
110 01101  
110 01110  
110 01111  
110 10000  
110 10001  
110 10010  
110 10011  
110 10100  
110 10101  
110 10110  
110 10111  
110 11000  
110 11001  
110 11010  
110 11011  
110 11100  
110 11101  
110 11110  
110 11111  
100111 0110 011000 0110  
011101 0110 100010 0110  
101101 0110 010010 0110  
110001 0110 110001 0110  
110101 0110 001010 0110  
101001 0110 101001 0110  
011001 0110 011001 0110  
111000 0110 000111 0110  
111001 0110 000110 0110  
100101 0110 100101 0110  
010101 0110 010101 0110  
110100 0110 110100 0110  
001101 0110 001101 0110  
101100 0110 101100 0110  
011100 0110 011100 0110  
010111 0110 101000 0110  
011011 0110 100100 0110  
100011 0110 100011 0110  
010011 0110 010011 0110  
110010 0110 110010 0110  
001011 0110 001011 0110  
101010 0110 101010 0110  
011010 0110 011010 0110  
111010 0110 000101 0110  
110011 0110 001100 0110  
100110 0110 100110 0110  
010110 0110 010110 0110  
110110 0110 001001 0110  
001110 0110 001110 0110  
101110 0110 010001 0110  
011110 0110 100001 0110  
101011 0110 010100 0110  
D0.7  
D1.7  
111 00000  
111 00001  
111 00010  
111 00011  
111 00100  
111 00101  
111 00110  
111 00111  
111 01000  
111 01001  
111 01010  
111 01011  
111 01100  
111 01101  
111 01110  
111 01111  
111 10000  
111 10001  
111 10010  
111 10011  
111 10100  
111 10101  
111 10110  
111 10111  
111 11000  
111 11001  
111 11010  
111 11011  
111 11100  
111 11101  
111 11110  
111 11111  
100111 0001 011000 1110  
011101 0001 100010 1110  
101101 0001 010010 1110  
110001 1110 110001 0001  
110101 0001 001010 1110  
101001 1110 101001 0001  
011001 1110 011001 0001  
111000 1110 000111 0001  
111001 0001 000110 1110  
100101 1110 100101 0001  
010101 1110 010101 0001  
110100 1110 110100 1000  
001101 1110 001101 0001  
101100 1110 101100 1000  
011100 1110 011100 1000  
010111 0001 101000 1110  
011011 0001 100100 1110  
100011 0111 100011 0001  
010011 0111 010011 0001  
110010 1110 110010 0001  
001011 0111 001011 0001  
101010 1110 101010 0001  
011010 1110 011010 0001  
111010 0001 000101 1110  
110011 0001 001100 1110  
100110 1110 100110 0001  
010110 1110 010110 0001  
110110 0001 001001 1110  
001110 1110 001110 0001  
101110 0001 010001 1110  
011110 0001 100001 1110  
101011 0001 010100 1110  
D2.6  
D2.7  
D3.6  
D3.7  
D4.6  
D4.7  
D5.6  
D5.7  
D6.6  
D6.7  
D7.6  
D7.7  
D8.6  
D8.7  
D9.6  
D9.7  
D10.6  
D11.6  
D12.6  
D13.6  
D14.6  
D15.6  
D16.6  
D17.6  
D18.6  
D19.6  
D20.6  
D21.6  
D22.6  
D23.6  
D24.6  
D25.6  
D26.6  
D27.6  
D28.6  
D29.6  
D30.6  
D31.6  
D10.7  
D11.7  
D12.7  
D13.7  
D14.7  
D15.7  
D16.7  
D17.7  
D18.7  
D19.7  
D20.7  
D21.7  
D22.7  
D23.7  
D24.7  
D25.7  
D26.7  
D27.7  
D28.7  
D29.7  
D30.7  
D31.7  
Document #: 38-02019 Rev. *C  
Page 31 of 34  
PRELIMINARY  
CYP32G0401DX  
Table 12. Valid Special Code-Groups (MODE 1 and MODE 3)  
Current RD -  
Current RD +  
Code Group Name  
Octet Value  
Octet Bits  
Notes  
HGF EDCBA  
abcdei fghj  
001111 0100  
001111 1001  
001111 0101  
001111 0011  
001111 0010  
001111 1010  
001111 0110  
001111 1000  
111010 1000  
110110 1000  
101110 1000  
011110 1000  
abcdei fghj  
110000 1011  
110000 0110  
110000 1010  
110000 1100  
110000 1101  
110000 0101  
110000 1001  
110000 0111  
000101 0111  
001001 0111  
010001 0111  
100001 0111  
K28.0  
K28.1  
K28.2  
K28.3  
K28.4  
K28.5  
K28.6  
K28.7  
K23.7  
K27.7  
K29.7  
1C  
3C  
5C  
7C  
9C  
BC  
DC  
FC  
F7  
000 11100  
001 11100  
010 11100  
011 11100  
100 11100  
101 11100  
110 11100  
111 11100  
111 10111  
111 11011  
111 11101  
111 11110  
15  
15, 16  
15  
15  
15  
16  
15  
15, 16  
FB  
FD  
FE  
K30.7  
Notes:  
15. Reserved.  
16. Contains a COMMA.  
Document #: 38-02019 Rev. *C  
Page 32 of 34  
PRELIMINARY  
CYP32G0401DX  
Ordering Information  
Operating  
Range  
Speed  
Standard  
Standard  
Ordering Code  
Package Name  
Package Type  
CYP32G0401DX-BGC  
CYP32G0401DX-BGI  
256 L2BGA  
256 L2BGA  
256-Ball Thermally Enhanced Ball Grid Array  
256-Ball Thermally Enhanced Ball Grid Array  
Commercial  
Industrial  
HOTLink is a registered trademark and HOTLink-III is a trademark of Cypress Semiconductor Corporation.  
InfiniBand is a trademark of the InfiniBand Trade Association.  
IBM and ESCON are registered trademarks and FICON is a trademark of International Business Machines.  
Package Diagram  
256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256  
51-85123-*C  
Document #: 38-02019 Rev. *C  
Page 33 of 34  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
PRELIMINARY  
CYP32G0401DX  
Document Title: CYP32G0401DX Multi-Gigabit Multi-Mode Quad HOTLink-III (TM) Transceiver (Preliminary)  
Document Number: 38-02019  
Issue  
Date  
Orig. of  
Change  
REV.  
**  
ECN NO.  
107382  
108153  
Description of Change  
06/19/01  
07/17/01  
KBN  
KBN  
New Data Sheet  
*A  
Changed 256 BGA package diagram to 256 L2BGA (#51-85123)  
Minor rewording of Features section  
*B  
*C  
110119  
111408  
09/26/01  
11/09/01  
GHW  
EK  
Added Functional Description, Block Level Diagram, Pin Descriptions, Elec-  
trical Parameters, Waveforms, 8B/10B Codes, Switching Parameters  
Advance to Preliminary  
Reduced Static Discharge Voltage maximum rating to 500V  
Document #: 38-02019 Rev. *C  
Page 34 of 34  
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CYP-0201TC [ PIANO SWITCHES (FULL PITCH) ] 5 页

NIDEC

CYP-0202MB [ PIANO SWITCHES (FULL PITCH) ] 5 页

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