QST608KT6,PDF,QST608KT6 PDF资料,Datasheet,下载QST608KT6技术资料

QST608

Capacitive touch sensor device

with rotor or slider plus five extra keys and I2C interface

Preliminary Data

Features

■ Patented charge-transfer design

■ Rotor (or slider) plus five extra keys

■ Up to five general-purpose outputs

LQFP32 (7x7 mm)

2

■ I C interface

■ Fully “debounced” results

Description

■ Patented AKS™ Adjacent Key Suppression

■ Self-calibration and auto drift compensation

■ Spread-spectrum bursts to reduce EMI

■ ECOPACK® (RoHS compliant) packages

The QST608 is the ideal solution for the design of

capacitive touch sensing user interfaces.

Touch-sensitive controls are increasingly

replacing electromechanical switches in home

appliances, consumer and mobile electronics,

and in computers and peripherals. Capacitive

touch controls allow designers to create stylish,

functional, and economical designs which are

highly valued by consumers, often at lower cost

than the electromechanical solutions they

replace.

Applications

This device specifically targets human interfaces

and front panels for a wide range of applications

such as PC peripherals, home entertainment

systems, gaming devices, lighting and appliance

controls, remote controls, etc.

The QST608 QTouch™ sensor IC is a pure digital

solution based on Quantum's patented charge-

transfer (QProx™) capacitive technology.

QST devices are designed to replace mechanical

switching/control devices and the reduced

number of moving parts in the end product

provides the following advantages:

QTouch™ and QProx™ are trademarks of the

Quantum Research Group.

■ Lower customer service costs

■ Reduced manufacturing costs

■ Increased product lifetime

Table 1.

Device summary

Feature

Order code

QST608KT6

Operating supply voltage

Supported interface

Operating temperature

Package

2.4V to 5.5V

I²C

–40° to +85° C

LQFP32 (7x7)

December 2007

Rev 1

1/44

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

1

Contents

QST608

Contents

1

2

3

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

QST touch sensing technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Spread-spectrum operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Faulty and unused keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Detection threshold levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Detection integrator filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Fast positive recalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Forced key recalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Max On-Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.10 Drift compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.11 Adjacent key suppression (AKS™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4

Device operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset and power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

General-purpose outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Communication packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

I2C address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5

Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1

5.2

C_Ssense capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Sensitivity tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2.1

Increasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/44

QST608

Contents

5.2.2

5.2.3

Decreasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Key balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3

5.4

5.5

5.6

5.7

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Crosstalk precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PCB layout and construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Slider and rotor layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2

6.3

6.4

6.5

6.6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Capacitive sensing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

GPOn pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.6.1

6.6.2

General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Output pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.7

6.8

RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

I2C control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7

8

9

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Device revision information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.1

9.2

Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Device revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2.1

Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3/44

Device overview

QST608

1

Device overview

The QST608 capacitive touch sensor IC is a pure digital solution based on Quantum's

patented charge-transfer (QProx™) capacitive technology.

This technology allows users to create simple touch panel sensing electrode interfaces for

conventional or flexible printed circuit boards (PCB/FPCB). Sensing electrodes are part of

the PCB layout (copper pattern or printed conductive ink) and may be used in various

shapes (circle, rectangular, etc.).

By implementing the QProx™ charge-transfer algorithm, the QST608 detects finger

presence (human touch) near electrodes behind a dielectric (glass, plastic, wood, etc.). Only

one external sampling capacitor by channel is used in the measuring circuitry to control the

detection.

QST technology also incorporates advanced processing techniques such as drift

compensation, auto-calibration, noise filtering, and Quantum's patented Adjacent Key

Suppression™ (AKS™) to ensure maximum usability and control integrity.

In order to meet environmental requirements, ST offers this device in ECOPACK®

packages. These packages have a lead-free second level interconnect. The category of

second level interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

4/44

QST608

Pin description

2

Pin description

Figure 1.

32-pin package pinout

32 31 30 29 28 27 26 25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

GPO4 (HS)

SNS_SCK2

SNSK_SCK1

SNS_SCK1

SNSK_SCK5

SNS_SCK5

SNSKC_MCK1

SNSC_MCK1

SNSKB_MCK1

GPO5 (HS)

IRQ (HS)

I2C_SDA (HS)

I2C_SCL (HS)

RESET

QST608KT6

NC

V_{DD_1}

9 10 11 12 13 14 15 16

(HS) 20mA high sink capability (on N-buffer only)

Table 2.

Device pin description

Pin name

Type ⁽¹⁾

Function

If unused

1

2

3

4

5

GPO4 ⁽²⁾

GPO5 ⁽²⁾

PP (HS) General purpose output 4

PP (HS) General purpose output 5

OD (HS) Interrupt line (active low)

TOD (HS) I²C serial data

Open

IRQ

I2C_SDA ⁽³⁾

I2C_SCL ⁽³⁾

TOD (HS) I²C serial clock

10nF capacitor

to ground

6

RESET

BD

Reset (active low)

7

8

9

NC

Not connected

Supply voltage

Ground voltage

Supply voltage

V_{DD_1}

V_{SS_1}

S

10 V_{SS_2}

11 V_{SS_3}

12 V_{SS_4}

13 V_{DD_2}

5/44

Pin description

QST608

Table 2.

Device pin description (continued)

Pin name

Type ⁽¹⁾

Function

If unused

14 SNSA_MCK1

15 SNSKA_MCK1

16 SNSB_MCK1

17 SNSKB_MCK1

18 SNSC_MCK1

19 SNSKC_MCK1

SNS

Rotor/slider 1 electrode A sense pin to Cs Open

Rotor/slider 1 electrode A sense pin to

Cs/Rs

SNS

Open

Rotor/slider 1 electrode B sense pin to Cs Open

Rotor/slider 1 electrode B sense pin to

Cs/Rs

Open

Rotor/slider 1 electrode C sense pin to Cs Open

Rotor/slider 1 electrode C sense pin to

Cs/Rs

Open

20 SNS_SCK5

21 SNSK_SCK5

22 SNS_SCK1

23 SNSK_SCK1

24 SNS_SCK2

25 SNSK_SCK2

26 SNS_SCK3

27 SNSK_SCK3

28 SNS_SCK4

29 SNSK_SCK4

SNS

Key 5 sense pin to Cs

Key 5 sense pin to Cs/Rs

Key 1 sense pin to Cs

Key 1 sense pin to Cs/Rs

Key 2 sense pin to Cs

Key 2 sense pin to Cs/Rs

Key 3 sense pin to Cs

Key 3 sense pin to Cs/Rs

Key 4 sense pin to Cs

Key 4 sense pin to Cs/Rs

Open

General purpose output 1 and

I²C address bit 0 option resistor

30 GPO1/ADD0 ⁽²⁾

31 GPO2/ADD1 ⁽²⁾

32 GPO3/ADD2 ⁽²⁾

PP (HS)

Option resistor

General purpose output 2 and

I²C address bit 1 option resistor

General purpose output 3 and

I²C address bit 2 option resistor

1. S: supply pin, BD: bidirectional pin, SNS: capacitive sensing pin, PP: Output push-pull, OD: Output open-

drain, TOD: Output true open-drain and HS: 20mA high sink output (on N-buffer only).

2. During reset phase, these pins are floating and their state depends on the option resistor when available.

3. An external pull-up of 4.7 kOhm (typical) is required on these pins.

6/44

QST608

QST touch sensing technology

3

QST touch sensing technology

3.1

Functional description

QST devices employ bursts of charge-transfer cycles to acquire signals. Burst mode permits

low power operation, dramatically reduces RF emissions, lowers susceptibility to RF fields,

and yet permits excellent speed. Signals are processed using algorithms pioneered by

Quantum which are specifically designed to provide reliable, trouble-free operation over the

life of the product.

The QST switches and charge measurement hardware functions are all internal to the

device. An external C capacitor accumulates the charge from sense-plate C , which is

S

X

then measured. Larger values of C cause the charge transferred into C to rise more

X

S

rapidly, reducing available resolution. As a minimum resolution is required for proper

operation, this can result in dramatically reduced gain. Larger values of C reduce the rise

S

of differential voltage across it, increasing available resolution by permitting longer QST

bursts. The value of C can thus be increased to allow larger values of C to be tolerated.

S

X

The device is responsive to both C and C , and changes in either can result in substantial

X

S

changes in sensor gain.

Figure 2. QTouch™ measuring circuitry

C

T

(~5 pF)

Earth

SNSK_SCKn

Sense capacitor

(a few nF)

C

S

SNS_SCKn

C (~20 pF)

x

Ai12569

3.2

Spread-spectrum operation

The bursts operate over a spread of frequencies, so that external fields will have minimal

effect on key operation and emissions are very weak. Spread-spectrum operation works

with the Detection Integrator mechanism (DI) to dramatically reduce the probability of false

detection due to noise.

7/44

QST touch sensing technology

QST608

3.3

Faulty and unused keys

Any sensing channel that does not have its sense capacitor (C ) fitted is assumed to be

S

either faulty or unused. This channel takes no further part in operation unless a Master-

commanded recalibration operation shows it to have an in-range burst count again. Faulty,

unused or disabled keys are still bursted but not processed to avoid modifying the sensitivity

of active keys.

This is important for sensing channels that have an open or short circuit fault across C .

S

Such channels would otherwise cause very long acquire bursts, and in consequence would

slow the operation of the entire QST device.

To optimize touch response time and device power consumption, if some keys are not used,

we recommend to try suppressing the ones which belong to the same burst. Bursts which

do not have any keys implemented will then not be processed.

3.4

3.5

Detection threshold levels

The key capacitance change induced by the presence of a finger is sensed by the variation

in the number of charge transfer pulses to load the capacitor. The difference in the pulse

count number is compared to a threshold in order to detect the key as pressed or not.

Two different thresholds, one for detection and one for the end of detection, create an

hysteresis in order to prevent erratic behavior.

The default threshold levels and hysteresis values are described in Section 6.5: Capacitive

sensing characteristics on page 32.

Detection integrator filter

Detect Integrator (DI) filter mechanism works together with spread spectrum operation to

dramatically reduce the effects of noise on key states. The DI mechanism requires a

specified number of measurements that qualify as detections (and these must occur in a

row) or the detection will not be reported.

In a similar manner, the end of a touch (loss of signal) also has to be confirmed over several

measurements. This process acts as a type of “debounce” mechanism against noise.

The default DI value for confirming start of touch and end of touch is described in

Section 6.5: Capacitive sensing characteristics on page 32.

3.6

Self-calibration

On power-up, all keys are self-calibrated to provide reliable operation under almost any

conditions. The calibration phase is used to compute a reference value per key which is then

used by the process determining if a key is touched or not. The reference is an average of 8

single acquisitions. As a result, the calibration time of the system can be simply calculated

using the following formula: t

= 8 * Burst_Period. The methodology used to measure the

CAL

burst period is described in application note AN2547. For a maximum calibration duration

(t ), please refer to Section 6.5: Capacitive sensing characteristics on page 32.

CAL

8/44

QST608

QST touch sensing technology

3.7

Fast positive recalibration

The device autorecalibrates a key when its signal reflects a decrease in capacitance higher

than a fixed threshold (PosRecalTh) for a defined number of acquisitions (PoseRecalI).

3.8

3.9

Forced key recalibration

A recalibration of the device may be issued at any time by sending to the QST device the

2

appropriate I C command or by tying the RESET pin to ground.

2

It is possible to recalibrate independently any individual key using an I C command.

Max On-Duration

The device can time out and automatically recalibrate each key independently after a fixed

duration of continuous touch detection. This prevents the keys from becoming ‘stuck on’ due

to foreign objects or other sudden influences. This is known as the Max On-Duration feature.

After recalibration, the key will continue to operate normally, even if partially or fully

obstructed. Max On-Duration works independently per channel: a timeout on one channel

has no effect on another channel.

Infinite timeout is useful in applications where a prolonged detection can occur and where

the output must reflect the detection no matter how long. In infinite timeout mode, the

designer should take care to ensure that drift in C , C , and V do not cause the device to

S

X

DD

remain “stuck on” inadvertently even when the touching object is removed from the sense

field. Timeout durations are not accurate and can vary substantially depending on V and

DD

temperature values, and should not be relied upon for critical functions.

3.10

Drift compensation

Signal drift can occur because of changes in C , C , and V over time. Depending on the

X

S

DD

C type and quality, the signal may vary substantially with temperature and veiling. If keys

S

are subject to extremes of temperature or humidity, the signal can also drift. It is crucial that

drift be compensated, otherwise false detections, non detections, and sensitivity shifts will

follow.

Drift compensation slowly corrects the reference level of each key while no detection is in

effect. The rate of reference adjustment must be performed slowly or else legitimate

detections can also be ignored. The device compensates drift on each channel

independently using a maximum compensation rate to the reference level.

Once a touch is sensed, the drift compensation mechanism ceases since the signal is

legitimately high, and therefore should not cause the reference level to change.

The signal drift compensation is “asymmetric”: the reference level compensates drift in one

direction faster than it does in the other. Specifically, it compensates faster for increasing

signals than for decreasing signals. Decreasing signals should not be compensated for

quickly, since an approaching finger could be compensated for partially or entirely while

approaching the sense electrode. However, an obstruction over the sense pad, for which the

sensor has already made full allowance, could suddenly be removed leaving the sensor with

an artificially elevated reference level and thus become insensitive to touch. In this latter

case, the sensor will compensate for the object's removal very quickly, usually in only a few

seconds.

9/44

QST touch sensing technology

QST608

Caution:

When only one key is enabled or if keys are very close together, the common drift

compensation must be disabled or its rate must be reduced to ensure correct device

operation.

3.11

Adjacent key suppression (AKS™)

Adjacent key suppression (AKS™) is a Quantum-patented feature which prevents multiple

keys from responding to a single touch. This can happen with closely spaced keys, or a

scroll wheel that has buttons very near it.

The QST608 supports two AKS modes:

●

Locking AKS

Once a key is considered as “touched”, all other keys are locked in an untouched state.

To unlock these keys, the touched key must return to an untouched state. Then, the key

having the lowest key ID number is declared as the “touched” one.

●

Unlocking AKS

On each acquisition, the signal strengths from each key are compared and the key with

the highest signal level is declared as the “touched” one.

2

In I C mode, up to 8 AKS groups can be specified.

Note:

All keys belonging to the same AKS group must have the same AKS mode.

If a rotor/slider belonging to an AKS group is touched, it locks others keys even if the AKS

group mode is unlocking.

10/44

QST608

Device operating mode

4

Device operating mode

2

The QST608 only supports one operating mode featuring an I C interface. This interface

offers a large range of device configurations.

4.1

Main features

●

5 general-purpose outputs

Configuration of up to 8 AKS groups

Large range of low power modes

Accessible internal capacitive sensing parameters

Continuous range of Max On-Duration

11/44

Device operating mode

Figure 3.

QST608

Typical application schematic

V_DD

2.4 to 5.5V

Volt. Reg.

V_UNREG

4.7µF

100nF

V_DD

8

13

Keep these parts close to IC

V_{DD_1}V_{DD_2}

5

4

3

21

I2C_SCL

I2C_SDA

IRQ

Key5

Key4

Key3

Key2

Key1

Pos. 0

SNSK_SCK5

10kΩ

R_S4

10kΩ

R_S3

10kΩ

R_S2

10kΩ

R_S1

10kΩ

To Host

C_S5

C_S4

C_S3

C_S2

C_S1

20

29

28

27

26

25

24

23

22

SNS_SCK5

SNSK_SCK4

SNS_SCK4

SNSK_SCK3

SNS_SCK3

SNSK_SCK2

SNS_SCK2

SNSK_SCK1

2

GPO5

GPO4

GPO5

GPO4

1

32

ADD2/GPO3

ADD1/GPO2

GPO3

V_DD

V_SS

SNS_SCK1

R_SR3

1MΩ

19

18

31

30

SNSKC_MCK1

SNSC_MCK1

10kΩ

C_SR3

R_SR1

10kΩ

GPO2

V_DD

V_SS

15

14

See Note 1

SNSKA_MCK1

SNSA_MCK1

ADD0/GPO1

RESET

GPO1

V_DD

V_SS

C_SR1

1MΩ

R_SR2

17

16

SNSKB_MCK1

SNSB_MCK1

10kΩ

C_SR2

6

10 nF

V_{SS_1}

V_{SS_2}

10

V_{SS_3}

11

V_{SS_4}

12

9

Ai12575

Note:

1

If you decide to use a rotor with a center dome button, Key 5 must be used.

12/44

QST608

Device operating mode

4.2

Reset and power-up

At power-up, the device configures itself according to the ADD[2:0] option resistors. The

device start-up and configuration may take up to t

.

Setup

When the power is established, it is possible to force a new device configuration by applying

a negative pulse on the RESET pin.

The RESET pin is a bidirectional pin with an internal pull-up. The line is forced low when the

device resets itself (through an I²C command, for example).

A 10nF capacitor is recommended on the RESET pin to ensure reliable start-up and noise

immunity.

4.3

Burst operation

The device operates in “Burst” mode. Each key touch is acquired using a burst of charge-

transfer sensing pulses whose count varies depending on the value of the sense capacitor

C and the load capacitance C . Key touches are acquired using several successive bursts

S

X

of pulses:

●

Burst A: Keys 1 to 4

Burst B: Keys 5

Burst C: R1, R2 and R3 (for rotor or slider)

Bursts always operate in an A-B-C sequence. If all keys belonging to a same burst are not

implemented, the QST device will not perform the Burst in order to improve the response

time and reduce the power consumption when in Low Power (LP) mode.

In Low Power mode, the device sleeps in an ultra-low current state between bursts to reduce

power consumption.

Note:

1

If you decide to use a rotor with a center dome button, Key 5 must be used.

13/44

Device operating mode

QST608

4.4

Low power mode

In order to reduce the device power consumption, the QST family include scalable low

power modes.

●

Internal device frequency

The internal device frequency can be modified to better adapt to the device low power

2

mode usage and I C speed.

Only two speeds are available: maximum frequency and reduced frequency.

Standard low power mode

●

When the device is in standard low power mode, a window with very low power

consumption is inserted between the acquisition of the last active key and the following

acquisition of the first active key.

This window duration is programmable as the 'sleep duration time'.

Note that the sleep window insertion is cancelled in the following conditions:

–

If a change is detected on a key, in order to speed up the DI process, the sleep

window insertion is skipped until the end of the DI process.

–

When a key change is actually detected and reported with a negative pulse on the

IRQ pin. In this case, the low power mode is disabled until a command is received

from the host.

2

–

Inside an I C command, between the Write and the Read I C frames, the sleep

period is skipped.

●

Free run in detect

The behavior in this mode is the same as in the standard low power mode except that

the sleep window insertion is always skipped if any of the active keys is detected as

touched.

This is useful to improve the wheel response time.

Deep Sleep mode

In deep sleep mode, the device enters a very low power mode indefinitely. The device

2

resumes its operations after receiving an I C frame with the device address or a reset.

2

Caution:

If an I C frame is received while in sleep or deep sleep mode, the device wakes up but does

2

not acknowledge the frame (even if it has an I C frame with the device address). The host

must therefore send again the frame until it is taken in account and acknowledged.

14/44

QST608

Device operating mode

4.5

General-purpose outputs

2

Up to 5 general-purpose outputs can be controlled using the I C interface. These general-

purpose pins are configured in output push pull mode 0 by default. Their state can be

changed using the SET_GPIO_STATE I C command.

2

Figure 4.

Optional LED schematic

V_UNREG

R

GPO

n

C (10 nF)

Ai12570

4.6

4.7

IRQ pin

The IRQ pin is an open drain output with an internal pull-up. It can be used to inform the

Master device about any change in the key status. The IRQ line is pulled low every time the

state of any of the enabled keys changes. This includes any change in the touch state of the

key, position change of the rotor/slider, a faulty key or new calibration of one or more keys.

The reported changes may then be accessed by the Master device by using the

GET_KEY_STATE command.

To improve communication response time, this signal suspends Low Power mode until the

Master device has issued a communication with the QST device.

Communication packet

The communication between the Master device and the QST608 (Slave) consists of two

2

standard I C frames.

The first frame is sent by the Master device using the QST608 device address with the write

bit set. The data bytes consist of the command byte which is eventually followed by the

parameters and a checksum byte.

The second one is sent by the Master device using the QST608 device address with the

write bit reset. The QST608 completes the frame with data according to the command

previously sent by the Master device. The device finishes the frame by sending a checksum

byte for communication integrity verification.

If the read frame is omitted, the command may not be taken into account and the low power

mode (if active) is suspended.

To initiate the communicate with the QST608, the Master device must send the

GET_DEVICE_INFO command in order to unlock access to all the other commands.

15/44

Device operating mode

QST608

4.8

I²C address selection

2

The QST608 offers several different 7-bit I C addresses. The selected I C address is

configured by tying high or low the pins ADD[2:0] (see Table 3).

Table 3.

I²C address versus option resistor

I²C Address

ADD[6:3]

ADD2

ADD1

ADD0

Hex value

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0110

16/44

QST608

Device operating mode

4.9

Supported commands

Table 4 lists the supported I²C commands and available arguments.

2

Note:

For more information on the supported commands and I C protocol, please refer to the QST

standard communication protocol reference manual.

Table 4.

Supported commands

I²C commands

Description

CALIBRATE_KEY (All keys)

Write

Read

0x98

Forces the recalibration of all keys.

ErrCode: Standard Error code (see Table 5)

ErrCode

CALIBRATE_KEY (Single key)

Write

Read

0x9B KeyID Checksum Forces the recalibration of a single key.

KeyId: Binary-coded key number (see Table 8)

ErrCode

ErrCode: Standard Error code (see Table 5)

GET_DEBUG_INFO

Returns the debug info of the single KeyID channel.

Write

0xF7 KeyID Checksum

KeyId: Binary-coded key number (see Table 8)

Answer for single-channel key.

KeyDbgState: Current Key Debug state (see Table 13)

RefMSB: Reference Count MSB

RefLSB: Reference Count LSB

BCMSB: Burst Count MSB

0x0B KeyDbgState

RefMSB RefLSB

(SCKey) BCMSB BCLSB

Checksum

Read

BCLSB: Burst Count LSB

0x1C KeyDbgState

KeyPos RefAMSB

RefALSB BCAMSB

Answer for multi-channel key.

KeyDbgState: Current Key Debug state (see Table 13)

KeyPos: Current key position (8-bit resolution)

RefnMSB: Reference n Count MSB

RefnLSB: Reference n Count LSB

BCnMSB: Burst Count n MSB

Read

BCALSB RefBMSB

(MCKey) RefBLSB BCBMSB

BCBLSB RefCMSB

RefCLSB BCCMSB

BCCLSB Checksum

BCnLSB: Burst Count n LSB

GET_DEVICE_INFO

Write

0x85

Returns the QST608 device version and ASCII-coded device

name. This command must be sent first to enable the

communication flow.

0x15 MainVers SubVers

NbSCkey NbMCkey

MainVers: Device main version

SubVer: Device sub-version

NbSCkey: 0x05 single-channel keys

NbMCkey: 0x01 multi-channel key

Q S T 6 0 8: ASCII-coded device name

Read

‘Q’ ’S’ ‘T’ ‘6’ ‘0’ ‘8’

Checksum

GET_KEY_ERROR

Write

0xC4

Returns the error information on each key.

0x11 KeyError1

KeyError2 ... KeyError8

CheckSum

KeyErrorN: KeyError byte description (see Table 6)

Read

17/44

Device operating mode

Table 4.

QST608

Supported commands (continued)

I²C commands

GET_KEY_STATE

Description

Write

0xC1

Returns the state of all keys.

AllKeyState: Touched/untouched state for all 5 keys and

rotor/slider. Refer to Table 7: AllKeyState.

RotPos: Rotor/slider absolute position

0x07 AllKeyState

RotPos KeyError

Checksum

Read

KeyError: Refer to Table 6: KeyError byte description

GET_PROTOCOL_VERSION

Write

0x80

Returns the QST608 protocol version.

MainVers: Protocol main version

SubVer: Protocol sub-version

0x07 MainVers SubVer

I2CSpeed Checksum

Read

I2CSpeed: 0x00 (100 kHz maximum)

RESET_DEVICE

Write

Read

0xFD

Restarts the device (options Read and Calibration) after

reading the ErrCode (see Table 5).

ErrCode

SET_DETECT_INTEGRATORS

0x03 0x04 0x00 DI EDI Sets the detection, End Of Detection and Positive Recalibration

Write

PosRecalI CheckSum

Integrators for all keys.

DI: Detection Integrator ^{1) 3)}

EDI: End of Detection Integrator ^{1) 3)}

PosRecalI: Positive Recalibration Integrator ^{1) 3)}

ErrCode: Standard Error code (see Table 5)

Read

ErrCode

SET_DRIFT_COMPENSATION

0x04 0x05 0x00

PosDriftI NegDriftI

Sets the positive and negative common and differential drift

rate for all keys.

Write

ComFact DifFact

Checksum

PosDriftI: Positive drift integrator

NegDriftI: Negative drift integrator

ComFact: Common time step factor

DifFact: Differential time step factor

ErrCode: Standard Error code (see Table 5)

Read

ErrCode

SET_GPIO_STATE

0x08 0x01 GPOState

Checksum

Controls the state of the general-purpose outputs.

GPOState: State of general-purpose outputs (see Table 10)

ErrCode: Standard Error code (see Table 5)

Write

Read

ErrCode

SET_KEY_ACTIVATION (See Note 4)

0x97 KeyActivation

Checksum

Enables or disables a single key.

Write

KeyActivation: Byte containing the key number selection and

requested state (seeTable 8).

ErrCode: Standard Error code (see Table 5)

Read

ErrCode

18/44

QST608

Device operating mode

Table 4.

Supported commands (continued)

I²C commands

Description

SET_KEY_GROUP

0x00 0x09

AKSGrpMode Key1Grp

Defines the AKS groups for each key.

Key2Grp Key3Grp

Key4Grp Key5Grp

Key6Grp Key7Grp

Key8Grp CheckSum

AKSGrpMode: AKS mode selection of each group (see

Table 11)

KeynGrp: AKS group selection for key n (see Table 12)

ErrCode: Standard Error code (see Table 5)

Write

Read

ErrCode

SET_LOW_POWER_MODE

0x92 LowPowerMode

Checksum

Selects standard or Low Power mode.

Write

LowPowerMode: Configure Low Power mode (see Table 9)

ErrCode: Standard Error code (see Table 5)

Read

ErrCode

SET_MAX_ON_DURATION

0x8A MaxOnDuration

Checksum

Sets the maximum detected ON time before triggering an

automatic recalibration.

Write

MaxOnDuration: Time, in second (0 for infinite)

ErrCode: Standard Error code (see Table 5)

Read

ErrCode

SET_MCKEY_PARAMETERS

0x02 0x07 0x00 DeTh

EofDeTh PosRecalTh

Resolution DirChI

DirChTh Checksum

Sets the Detection, End Of Detection and Positive

Recalibration Thresholds for all keys.

Write

DeTh: Detection Threshold ^{1) 2)}

EofDeTh: End of Detection Threshold ^{1) 2)}

PosRecalTh: Positive Recalibration Threshold ^{1) 2)}

Resolution: Rotor/slider resolution of the reported position (1

to 7 for 1-bit to 7-bit)

DirChI: Direction Change Integrator ^{1) 3)}

DirChTh: Direction Change Threshold ^{1) 3)}

ErrCode: Standard Error code (see Table 5)

Read

ErrCode

SET_SCKEY_PARAMETERS

0x01 0x04 0x00 DeTh

EofDeTh PosRecalTh

Checksum

Sets the Detection, End Of Detection and Positive

Recalibration Thresholds for all keys.

Write

Read

DeTh: Detection Threshold ^{1) 2)}

EofDeTh: End of Detection Threshold^{1) 2)}

PosRecalTh: Positive Recalibration Threshold^{1) 2)}

ErrCode: Standard Error code (see Table 5)

ErrCode

Note:

1

2

3

4

See Section 6.5: Capacitive sensing characteristics on page 32 for default values.

The value is a signed character (0x80...0x7F <=> -128 ... +128).

The value is an unsigned number (0x00..0xFF <=> 0 ... 255).

Enabling or disabling keys triggers a new calibration of all enabled keys.

19/44

Device operating mode

Error codes

QST608

2

Table 5 lists the I C error codes.

Table 5.

ErrCode

Description

0x01

0x83

0x85

0xA1

0xA3

0xE0

No Error

Command not supported

Parameter not supported

Parity Error

Checksum Error

Initialization process (GET_FIRMWARE_INFO command not received)

KeyError byte description

Table 6.

Bit 7

KeyError byte description

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Key State

0

Key error codes

Key state (Bit 7)

When set to ‘1’, the corresponding key is touched. This bit is always cleared for the

GET_KEY_STATE command.

Key error codes (Bits 2:0)

When answering the GET_KEY_STATE command, the key error code corresponds to

the error codes of all the keys ORed toghether. When answering the

GET_KEY_ERROR command, each key error code describes the errors of one defined

key.

Bit 0: When set to ‘1’, calibration in progress

Bit 1: When set to ‘1’, maximum count reached

Bit 2: When set to ‘1’, minimum count not reached

All key state description

Table 7.

Bit 7

AllKeyState

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Rotor 1

State

0

Key 5 State Key 4 State Key 3 State Key 2 State Key 1 State

Key n state

When set to ‘1’, the corresponding key or rotor is touched.

20/44

QST608

Device operating mode

Key activation description

Table 8.

Bit 7

KeyActivation

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Key

Activation

0

Key ID (binary coded)

Key activation (Bit 7)

0: Key disabled

1: Key enabled

Key identifier (Bits 3:0)

0000: All keys

0001: Key 1

0010: Key 2

0011: Key 3

0100: Key 4

0101: Key 5

0111: Rotor/Slider 1

Low power mode description

Table 9.

Bit 7

SetLowPower

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Free Run

in Detect

Freq

Sleep Duration Factor

Device Frequency (Bit 7)

0: Reduced internal frequency (default)

1: Maximum internal frequency

Free Run in Detect (Bit 6)

0: Low Power mode is always enabled, whatever the state of the keys.

1: Low Power mode is automatically suspended when any key is in Detect state.

Low Power mode is automatically resumed when no key is in Detect state.

Sleep Duration Factor (Bits 5 to 0)

0x00 or 0x20 to 0x3E: Low power mode is disabled.

0x01 to 0x19: Low Power mode. The sleep duration is ‘Sleep Duration Factor’ x 20

milliseconds (20 ms to 500 ms)

2

0x3F: Deep Sleep mode is entered immediately. Only a reset or an I C frame with

the correct device address allows exiting Deep Sleep mode.

2

Note:

1

2

When the device is in Sleep or Deep Sleep, any I C bus activity will wake-up the device.

2

The I C QST device address is not acknowledged but forces the QST device to exit from

Low Power mode. The Master device will have to repeat the command to ensure that it is

taken in account.

21/44

Device operating mode

QST608

Bit 0

GPO state description

Table 10. GPOState

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

GPO 5

state

GPO 4

state

GPO 3

state

GPO 2

state

GPO 1

state

0

GPOState

Defines the state of the selected general-purpose output pin. For more information, see

Section 4.5: General-purpose outputs on page 15.

0: GPO state is ‘0’

1: GPO state is ‘1’

AKS group mode description

Table 11. AKSGrpnMode

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

AKSGrp8 AKSGrp7 AKSGrp6 AKSGrp5 AKSGrp4 AKSGrp3 AKSGrp2 AKSGrp1

Mode Mode Mode Mode Mode Mode Mode Mode

AKSGrpnMode

Defines the type of AKS for the Group n:

0: Locking AKS

First key pressed within the group locks out all other keys.

1: Unlocking AKS

Most heavily pressed key (highest signal level) is selected over all other

keys in the group.

AKS group selection description

Table 12. KeynGrp

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Grp8

Grp7

Grp6

Grp5

Grp4

Grp3

Grp2

Grp1

Grpx

The selected key is a member of AKS Group x.

22/44

QST608

Device operating mode

Key debug state description

Table 13. KeyDbgState

Value

Description

0x01

0x02

0x04

0x08

0x11

0x14

0x24

On-going calibration

Key released

Key touched

Key in error

Key calibration filter triggered (PosRecalI)

Key detection filter triggered (DI)

Key end of detection filter triggered (EDI)

23/44

Design guidelines

QST608

5

Design guidelines

5.1

C_Ssense capacitor

The C sense capacitors accumulate the charge from the key electrodes and determine

S

sensitivity. Higher values of C make the corresponding sensing channel more sensitive.

S

The values of C can differ for each channel, permitting differences in sensitivity from key to

S

key or to balance unequal sensitivities. Unequal sensitivities can occur due to key size and

placement differences and stray wiring capacitances. More stray capacitance on a sense

trace will desensitize the corresponding key. Increasing the C for that key will compensate

S

for the loss of sensitivity.

The C capacitors can be virtually any plastic film or low- to medium-K ceramic capacitor.

S

The normal C range is 1nF to 50nF depending on the sensitivity required: larger values of

S

C require better quality to ensure reliable sensing. In certain circumstances the normal C

range may be exceeded. Acceptable capacitor types for most uses include PPS film,

S

polypropylene film, and NP0 and X5R / X7R ceramics. Lower grades than X5R or X7R are

not recommended.

5.2

Sensitivity tuning

Sensitivity can be altered to suit various applications and situations on a channel-by-

channel basis. The easiest and most direct way to impact sensitivity is to alter the value of

each C : more C yields higher sensitivity. Each channel has its own C value and can

S

therefore be independently adjusted.

5.2.1

5.2.2

Increasing sensitivity

Sensitivity can also be increased by using larger electrode areas, reducing panel thickness,

or using a panel material with a higher dielectric constant.

Decreasing sensitivity

In some cases the circuit may be too sensitive. Gain can be lowered further by a number of

strategies:

●

making the electrode smaller

making the electrode into a sparse mesh using a high space-to-conductor ratio

decreasing the C capacitors

S

5.2.3

Key balance

A number of factors can cause sensitivity imbalances. Notably, SNS wiring to electrodes can

have differing stray amounts of capacitance to ground. Increasing load capacitance will

cause a decrease in gain. Key size differences, and proximity to other metal surfaces can

also impact gain.

The keys may thus require “balancing” to achieve similar sensitivity levels. This can be best

accomplished by trimming the values of the C capacitors to achieve equilibrium. The R

S

resistors have no effect on sensitivity and should not be altered. Load capacitances to

ground can also be added to overly sensitive channels to reduce their gain.

These should be in the order of a few picofarads.

24/44

QST608

Design guidelines

5.3

Power supply

If the power supply fluctuates slowly with temperature, the QST device compensates

automatically for these changes with only minor changes in sensitivity. However, if the

supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep

up, causing sensitivity anomalies or false detections.

The power supply should be locally regulated, using a three-terminal regulator. If the supply

is shared with another electronic system, care should be taken to ensure that the supply is

free of digital spikes, sags and surges which can cause adverse effects. It is not

recommended to include a series inductor in the power supply to the QST device.

For proper operation, a 0.1 µF or greater bypass capacitor must be used between V and

DD

V

. The bypass capacitor should be routed with very short tracks to the device’s V and

pins.

SS

DD

The PCB should, if possible, include a copper pour under and around the device, but not

extensively under the SNS lines.

5.4

5.5

ESD protection

In normal environmental conditions, only one series resistor is required for ESD

suppression. A 10 kOhm R resistor in series with the sense trace is sufficient in most

cases. The dielectric panel (glass or plastic) usually provides a high degree of isolation to

prevent ESD discharge from reaching the circuit. R should be placed close to the chip. If

S

the C load is high, R can prevent total charge and transfer and as a result gain can

X

S

deteriorate. If a reduction in R increases gain noticeably, the lower value should be used.

Conversely, increasing the R can result in added ESD and EMC benefits, provided that the

increase does not decrease sensitivity.

S

Crosstalk precautions

Adjacent sense traces might require intervening ground traces in order to reduce capacitive

cross bleed if high sensitivity is required or high values of delta-C are anticipated (for

X

example, from direct human touch to an electrode connection). In normal touch applications

behind plastic panels, this is rarely a problem regardless of how the electrodes are wired.

Higher values of R will make crosstalk problems worse; try to keep R to 22 kOhm or less

S

if possible. In general try to keep the QST device close to the electrodes and reduce the

adjacency of the sense wiring to ground planes and other signal traces; this will reduce the

C load, reduce interference effects, and increase signal gain. The one and only valid

x

reason to run ground near SNS traces is to provide crosstalk isolation between traces, and

then only on an as-needed basis.

5.6

PCB layout and construction

The PCB traces, wiring, and any components associated with or in contact with either SNS

pin will become touch sensitive and should be treated with caution to limit the touch area to

the desired location.

Multiple touch electrodes connected to any sensing channel can be used, for example, to

create control surfaces on both sides of an object.

25/44

Design guidelines

QST608

It is important to limit the amount of stray capacitance on the SNS terminals, for example by

minimizing trace lengths and widths to allow for higher gain without requiring higher values

of C . Under heavy delta-C loading of one key, cross coupling to another key’s trace can

S

X

cause the other key to trigger. Therefore, electrode traces from adjacent keys should not be

run close to each other over long runs in order to minimize cross-coupling if large values of

delta-C are expected, for example when an electrode is directly touched. This is not a

X

problem when the electrodes are working through a plastic panel with normal touch

sensitivity.

For additional information on PCB layout and construction, please contact your local ST

Sales Office for a list of available application notes.

5.7

Slider and rotor layout

The QST608 can connect to either a rotor or a linear slider element (Figure 5). The basis of

these designs is found in US Patent 4,264,903 (expired).

Figure 5.

Slider and rotor construction

Position 0

SNSC_MCK1

SNSC_MCK1 SNSA_MCK1 SNSB_MCK1 SNSC_MCK1

0

1 to 126

127

Position 43

SNSA_MCK1

Position 85

SNSB_MCK1

Positions 0 to 127 (at 7 bits)

1. Tips of triangles should be spaced ≤ 4mm apart.

The first and last positions of the linear slider have larger touch areas.

Figure 6. Slider layout details

26/44

QST608

Design guidelines

Figure 7.

Rotor layout details

As with touch button electrodes, rotors and sliders can be constructed as etched areas on a

PCB or flex circuit, or from clear conductors such as Indium Tin Oxide (ITO) or screen-

printed Orgacon™ (Agfa) to allow backlighting effects, or for use over an LCD display.

27/44

Electrical characteristics

QST608

6

Electrical characteristics

6.1

Parameter conditions

Unless otherwise specified, all voltages are referred to V

.

SS

6.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25°C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean 3Σ).

6.1.2

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 5 V (for the 4.5V ≤

A

DD

V

≤ 5.5 V voltage range) and V = 3.3 V (for the 3.0 V ≤ V ≤ 3.6 V voltage range).

DD

DD DD

They are given only as design guidelines and are not tested.

6.1.3

6.1.4

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.

Figure 8.

Pin loading conditions

Output pin

28/44

QST608

Electrical characteristics

6.1.5

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.

Figure 9. Pin input voltage

Input pin

V_IN

6.2

Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage

to the device. This is a stress rating only and functional operation of the device under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Table 14. Thermal characteristics

Symbol

Ratings

Storage temperature range

Maximum junction temperature

Value

Unit

T_STG

T_J

−65 to +150

°C

Table 15. Voltage characteristics

Symbol

Ratings

Maximum value

Unit

V_DD− V_SSSupply voltage

7.0

V_SS−0.3 to V_DD+0.3

4000

V_IN

Input voltage on any pin ⁽¹⁾⁽²⁾

V

V_ESD(HBM)Electrostatic discharge voltage (Human Body Model)

V_ESD(CDM)Electrostatic discharge voltage (Charge Device Model)

500

1. Directly connecting the RESET and I/O pins to V_DDor V_SScould damage the device if an unintentional

internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a

corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up

or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os).

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS. For true open-drain

pads, there is no positive injection current, and the corresponding V_INmaximum must always be

respected.

29/44

Electrical characteristics

QST608

Unit

Table 16. Current characteristics

Symbol

Ratings

Maximum value

I_VDD

I_VSS

Total current into V_DDpower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

Output current sunk by RESET pin

75

150

20

40

− 25

5

I_IO

Output current sunk by output pin

mA

Output current source by output pin

Injected current on RESET pin

(2)

I_INJ(PIN)

(3)

Injected current on output pin

5

(2)

ΣI_INJ(PIN)

Total injected current (sum of all I/O and control pins)

20

1. All power (V_DD) and ground (V_SS) lines must always be connected to the external supply.

2. I_INJ(PIN)must never be exceeded. This is implicitly ensured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS. For true open-drain

pads, there is no positive injection current, and the corresponding V_INmaximum must always be

respected.

3. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values). These results are based on

characterisation with ΣI_INJ(PIN)maximum current injection on four I/O port pins of the device.

6.3

Operating conditions

Table 17. Operating conditions

Symbol

Feature

Value

Unit

V_DD

T_A

Operating supply voltage

Operating temperature

2.4 to 5.5

V

C

-40° to +85°

30/44

QST608

Electrical characteristics

6.4

Supply current characteristics

(1)

Table 18. Supply current characteristics

Reduced freq.

mode (Typ.)

Max. frequency

Unit

Symbol

Parameter

Conditions

mode (Typ.)

V_DD= 2.4 V

1.82

2.34

3.60

499

Average suppy current

Free Run mode

I_DD(FR)

V_DD= 3.3 V

3.85

6.11

mA

µA

V_DD= 5 V

V_DD= 2.4 V

I_DD

(Sleep

100ms)

Average suppy current

100ms Sleep mode

V

_DD= 3.3 V

695

645

V_DD= 5 V

1189

130

1189

V_DD= 2.4 V

I_DD

(Sleep

500ms)

Average suppy current

500ms Sleep mode

V_DD= 3.3 V

185

152

287

µA

V_DD= 5 V

328

Average suppy current

Deep sleep mode

I_DDHalt

1

1. The results performed at T = 25°C and based on C_S= 4.7nF for single-channel keys and C_S= 47nF for

multi-channel keys.

Figure 10. IDD Sleep mode current characteristics

31/44

Electrical characteristics

QST608

6.5

Capacitive sensing characteristics

Table 19. External sensing components

Symbol

Parameter

Min.

Typ.

Max.

Unit

C_S

C_X

C_T

R_S

Sense capacitor

100

nF

pF

Equivalent electrode capacitor

Equivalent touch capacitor

Serial resistance

5

pF

10

22

kOhm

Table 20. Capacitive sensing parameters

Symbol

Parameter

Calibration duration

Min. Default Max.

Unit

t_CAL

t_Setup

TBD

100

ms

Setup duration

ms

Res_MCKey

DI

Resolution (MCKey)

1

0

7

2

8

bits

Detection integrator

255

–1

Counts

DeTh_SCKey

DeTh_MCKey

EDI

Default detection threshold (SCKey)

Detection threshold (MCKey)

End of detection integrator

–128

0

–10

–30

2

–1

255

–1

EofDeTh_SCKeyEnd of detection threshold (SCKey)

EofDeTh_MCKeyEnd of detection threshold (MCKey)

–128

0

–8

–20

5

–1

PosRecalI

Positive recalibration integrator

255

128

PosRecalTh_SCKeyPositive recalibration threshold (SCKey)

PosRecalTh_MCKeyPositive recalibration threshold (MCKey)

1

6

1

30

DirChI

Wheel/Slider Direction Change Integrator

Wheel/Slider Direction Change Threshold

0

3

4

255 positions

DirChTh

0

MaxOnDuration Max on-duration delay

s

1

Infinite

1

255

25.5

PosDiffDrift

NegDiffDrift

PosComDrift

NegComDrift

Positive differential drift compensation rate

0.1

s/level

Negative differential drift compensation rate

Positive common drift compensation rate

Negative common drift compensation rate

1

0.2

10

2

PosDriftI

NegDriftI

ComFact

DiffFact

Positive drift integrator

Negative drift integrator

Common time step factor

Differential time step factor

Burst length (SCKey)

0

255

0

Burst_SCKey

Burst_MCKey

20

50

2000 Counts

5000 Counts

Burst length (MCKey)

32/44

QST608

Electrical characteristics

6.6

GPOn pin characteristics

6.6.1

General characteristics

Subject to general operating conditions for V and T unless otherwise specified.

DD

A

Table 21. General characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

V_IL

Input low level voltage ⁽¹⁾

V_SS−0.3

0.3x V_DD

V

V_DD

0.3

+

V_IH

Input high level voltage ⁽¹⁾

0.7x V_DD

V_Hys

I_L

Schmitt trigger voltage hysteresis⁽²⁾

Input leakage current

400

mV

μA

pF

V_SS≤ V_IN≤ V_DD

1

C_IO

I/O pin capacitance

5

C_L= 50 pF

t_f(IO)outOutput high to low level fall time ⁽²⁾Between 10%

and 90%

25

ns

t_r(IO)outOutput low to high level rise time ⁽²⁾

1. Not tested in production, guaranteed by characterization.

2. Data based on validation/design results.

6.6.2

Output pin characteristics

Subject to general operating conditions for V , f

, and T unless otherwise specified.

A

DD CPU

Table 22. Output pin current

Symbol

Parameter

Conditions

I_IO

Min.

Max.

Unit

=

Output low level voltage for a high sink I/O

pin when 4 pins are sunk at same time (see

Figure 16)

1.3

(1)

+20mA

V_OL

I_IO= +8mA

0.75

Output high level voltage for an I/O pin when

4 pins are sourced at same time (see

Figure 21)

I_IO= -5mA V_DD−1.5

_IO= -2mA V_DD−0.8

(2)

V_OH

I

Output low level voltage for a high sink I/O

pin when 4 pins are sunk at same time

(1)(3)

V_OL

I_IO= +8mA

_IO= -2mA V_DD−0.8

0.5

0.6

V

Output high level voltage for an I/O pin when

4 pins are sourced at same time (Figure 19)

(2)(3)

V_OH

I

Output low level voltage for a high sink I/O

pin when 4 pins are sunk at same time

(1)(3)

V_OL

I_IO= +8mA

Output high level voltage for an I/O pin when

4 pins are sourced at same time

(2)(3)

V_OH

I_IO= -2mA V_DD−0.9

1. The I_IOcurrent sunk must always respect the absolute maximum rating specified in Table 16 and the sum

of I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. The I_IOcurrent sourced must always respect the absolute maximum rating specified in Table 16 and the

sum of I_IO(output and RESET pins) must not exceed I_VDD..

3. Not tested in production, based on characterization results.

33/44

Electrical characteristics

QST608

Figure 11.

Typical V_OLat V_DD= 2.4 V

Figure 12.

Typical V_OLvs V_DDat I_load= 2 mA

V_OLvs V_DD@I_load=2 mA HS Pins

V_OLvs I_load@ V_DD= 2.4 V HS pins

120

110

100

90

-40°C

25°C

1200

1000

800

600

400

200

0

-40°C

25°C

85°C

125°C

85°C

125°C

80

70

60

50

40

2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

4

4.2 4.4 4.6 4.8 5 5.2 5.4 5.6

V_DD[V]

0

2

4

6

8

10

12

14

16

I_load[mA]

Figure 13.

Typical V_OLat V_DD= 3 V

Figure 14.

Typical V_OLvs V_DDat I_load= 8 mA

V_OLvs V_DD@I_load= 8 mAHS Pins

V_OLvs I_load@ V_DD= 3 V HS pins

540

490

440

390

340

290

240

190

140

-40°C

25°C

1600

1400

1200

1000

800

600

400

200

0

-40°C

25°C

85°C

125°C

2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6

V_DD[V]

0

2

4

6

8

10

12

14

16

18

20

I_load[mA]

Figure 15.

Typical V_OLat V_DD= 5 V

Figure 16.

Typical V_OLvs V_DDat I_load= 12 mA

V_OLvs V_DD@I_load= 12 mA HS Pins

V_OLvs I_load@ V_DD= 5 V HS pins

1040

940

840

740

640

540

440

340

240

140

-40°C

25°C

900

800

700

600

500

400

300

200

100

0

-40°C

25°C

85°C

125°C

85°C

125°C

2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6

V_DD[V]

0

2

4

6

8

10

12

14

16

18

20

I_load[mA]

34/44

QST608

Electrical characteristics

Figure 17.

Typical V_DD-V_OHvs. I_loadat V_DD= 2.4 V Figure 18.

Typical V_DD-V_OHvs. V_DDat I_load= 2 mA

V_DD-V_OHvs I_load@ V_DD= 2.4 V HS Pins

V_DD-V_OHvs V_DD@I_load= 2 mA HS Pins

800

700

600

500

400

300

200

100

0

800

-40°C

25°C

85°C

125°C

-40°C

25°C

700

600

500

400

300

200

100

0

85°C

125°C

V_DD[V]

2

4

I_load[mA]

Figure 19.

Typical V_DD-V_OHvs. I_loadat V_DD= 3 V

Figure 20.

Typical V_DD-V_OHvs. V_DDat I_load= 4 mA

V_DD-V_OHvs I_load@ V_DD= 3 V HS Pins

V_DD-V_OHvs V_DD@I_load= 4 mA HS Pins

1800

1600

1400

1200

1000

800

1800

1600

1400

1200

1000

800

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

600

400

600

200

400

0

200

0

V_DD[V]

0

2

4

6

I_load[mA]

Figure 21.

Typical V_DD-V_OHvs. I_loadat V_DD= 5 V

V_DD-V_OHvs I_load@ V_DD= 5 V HS Pins

4500

4000

3500

3000

2500

2000

1500

1000

500

-40°C

25°C

85°C

125°C

0

2

4

6

8

10

12

14

I_load[mA]

35/44

Electrical characteristics

QST608

6.7

RESET pin

T = -40°C to 125°C, unless otherwise specified.

A

Table 23. RESET pin characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

V_IL

V_IH

Input low level voltage

Input high level voltage

V_SS− 0.3

0.3x V_DD

V_DD+ 0.3

V

0.7 x V_DD

Schmitt trigger voltage

hysteresis⁽¹⁾

V_hys

V_OL

2

V

Output low level

voltage⁽²⁾

V_DD= 5V I_IO= +2mA

200

mV

V_DD= 5V

V_IN= V_SS

30

20

50

70

Pull-up equivalent

resistor⁽³⁾

R_ON

kΩ

μs

V_DD= 3V

90⁽¹⁾

Generated reset pulse

duration

t_w(RSTL)out

Internal reset sources

90⁽¹⁾

External reset pulse

hold time⁽⁴⁾

t_h(RSTL)in

μs

t_g(RSTL)inFiltered glitch duration

200

ns

1. Data based on characterization results, not tested in production.

2. The I_IOcurrent sunk must always respect the absolute maximum rating specified in Table 16: Current

characteristics on page 30 and the sum of I_IO(I/O ports and control pins) must not exceed I_VSS

.

3. The R_ONpull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin

between V_ILmaxand V_DD

.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses

applied on RESET pin with a duration below t_h(RSTL)incan be ignored.

36/44

QST608

Electrical characteristics

I²C control interface

6.8

Subject to general operating conditions for V , and T unless otherwise specified.

DD

A

2

The QST608 I C interface meets the requirements of the Standard I C communication

protocol described in the following table with the restriction mentioned below:

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (SDA and SCL).

Table 24. I²C characteristics

100 kHz speed

Symbol

Parameter

Unit

Min. ⁽¹⁾

Max. ⁽¹⁾

t_w(SCLL)SCL clock low time

t_w(SCLH)SCL clock high time

t_su(SDA)SDA setup time

4.7

4.0

µs

ns

250

0 ⁽²⁾

t_h(SDA)

SDA data hold time

t_r(SDA)

t_r(SCL)

SDA and SCL rise time

1000

300

ns

µs

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

t_h(STA)

START condition hold time

4.0

4.7

4.0

4.7

t_su(STA)

Repeated START condition setup time

t_su(STO)STOP condition setup time

μs

µs

pF

t_w(STO:STA)STOP to START condition time (bus free)

C_b

Capacitive load for each bus line

400

Data based on standard I2C protocol requirement, not tested in production.

1.

2. The maximum hold time of the START condition has only to be met if the interface does not stretch the low

period of the SCL signal.

(1)

Table 25. IRQ specific pin characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

t_W(IRQ)IRQ pulse width

10

15

µs

V_DD= 5V

V_DD= 3V

100

120

300

140

R_IRQ

IRQ internal pull-up ⁽²⁾

kΩ

1. For additional pin parameters, please use the pin description in Section 6.6: GPOn pin characteristics on

page 33.

2. The IRQ pull-up equivalent resistor is based on a resistive transistor.

37/44

Electrical characteristics

Figure 22.

QST608

2

Typical application with I C bus and timing diagram

V

DD

4.7kΩ

100Ω

SDA

SCL

2

I C BUS

QST device

REPEATED START

START

t

w(STO:STA)

su(STA)

START

SDA

t

r(SDA)

f(SDA)

STOP

t

h(SDA)

su(SDA)

SCL

t

su(STO)

t

h(STA)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

38/44

QST608

Package mechanical data

7

Package mechanical data

Figure 23. 32-pin low profile quad flat package (7x7) outline

Seating

plane

C

A

A2

c

A1

b

0.25 mm

Gage plane

ccc

C

D

K

L

D1

A1

L1

D3

24

17

16

25

E3 E1

E

32

9

Pin 1

identification

1

8

e

5V_ME

39/44

Package mechanical data

QST608

Max.

Table 26. 32-pin low profile quad flat package mechanical data

mm

inches⁽¹⁾

Dim.

Min.

Typ.

Max.

Min.

Typ.

A

A1

A2

b

1.600

0.150

1.450

0.450

0.200

9.200

7.200

0.0630

0.0059

0.0571

0.0177

0.0079

0.3622

0.2835

0.050

1.350

0.300

0.090

8.800

6.800

0.0020

0.0531

0.0118

0.0035

0.3465

0.2677

1.400

0.370

0.0551

0.0146

c

D

9.000

7.000

5.600

9.000

7.000

5.600

0.800

0.600

1.000

3.5°

0.3543

0.2756

D1

D3

E

0.2205

8.800

6.800

9.200

7.200

0.3465

0.2677

0.3543

0.3622

0.2835

E1

E3

e

0.2756

0.2205

0.0315

L

0.450

0.0°

0.750

7.0°

0.0177

0.0°

0.0236

0.0295

7.0°

L1

K

0.0394

3.5°

Tolerance (mm)

0.10

Tolerance (inches)

0.0039

ccc

1. Values in inches are converted from mm and rounded to 4 decimal digits.

40/44

QST608

Part numbering

8

Part numbering

Table 27. Ordering information scheme

Example:

QST

6

08

K

T

6

Device type

QST = Capacitive touch sensor

Device sub-family

1: QTouch (3 to 5 V)

5: QMatrix (3 to 5 V)

6: QSlide/QWheel (3 to 5 V)

11: QTouch (1.8 to 3.6 V)

15: QMatrix (1.8 to 3.6 V)

16: QSlide/QWheel (1.8 to 3.6 V)

Channel count

Number of channels

Pin count

A: 8 pins

Y: 16 pins

K: 32 pins

S: 44 pins

C: 48 pins

M: 80 pins

Package

B: DIP (dual in-line)

H: BGA (ball grid array)

M: SO (small outline)

N: TSSOP (thin-shrink small outline package)

T: LQFP (thin quad flat)

U: QFN (dual quad flat no lead)

Temperature range

0: +25°C

1: 0 to +70°C

5: –10°C to +85°C

6: –40°C to +85°C

7: –40°C to +105°C

9: –40°C to + 125°C

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST Sales Office.

The category of second Level Interconnect is marked on the package and on the inner box

label, in compliance with JEDEC Standard JESD97. The maximum ratings related to

soldering conditions are also marked on the inner box label.

41/44

Device revision information

QST608

9

Device revision information

9.1

Device identification

Figure 24. Device revision identification

LQFP Package

A

QST608KT6

^BQRG

V10

C

D

E

H

F

G

I

K

a

J

Table 28. Device revision identification

Marking

Device revision

V10

First revision

9.2

Device revision identification

The marking on the right side of the second line (Line B) of the package top face identifies

the device revision.

2

The device revision can also be obtained using the GET_DEVICE_INFO I C command. For

more information, refer to Section 4.9: Supported commands on page 16.

This section identifies the device deviations from the present specification for each device

revision.

9.2.1

Revision 1.0

First device revision.

42/44

QST608

Revision history

10

Revision history

Table 29. Document revision history

Date

Revision

Changes

10-Dec-2007

1

First release.

43/44

QST608

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT

RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE

GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

44/44

厂商	型号	描述	页数
SAMTEC	QST-110-01-F-T	[ Board Stacking Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator, Socket, ROHS COMPLIANT ]	1 页
SAMTEC	QST-110-01-G-5-MW	[ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-01-M-T-MW	[ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-01-S-5-MW	[ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-01-S-T-MW	[ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-02-F-T-MW	[ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-02-G-5-MW	[ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-02-G-T-MW	[ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-02-L-5-MW	[ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-02-L-T	[ Board Stacking Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator, Socket, ROHS COMPLIANT ]	1 页