IXF6402 Broadband Access Processor
SECTION 2 - ARCHITECTURAL OVERVIEW
• RFC 1577 (Classical IP and ARP over ATM)
• ATM Forum LANE Specification, Version 1.0
2.1 Hardware Packet
Processing
The IXF6402 performs all relevant Layer 2 functions and
provides extensive hardware assistance to your CPU,
FPGA or ASIC-based higher-layer processing engine.
Because all SAR, traffic shaping, tagging, encapsulation,
buffer management & DMA is handled by the IXF6402, it
enables your higher-layer engine to focus on application
functions layers such as bridging, routing, encryption,
network O/S, management and security.
• ATM Forum LANE Version 2.0 - LUNI Baseline
Document, Draft 5, February 1997
• ATM Forum MPOA Specification, Version 1.0 -
Baseline Document, February 1997
The design incorporates numerous features to maximize
both chip level and system level throughput. The IXF6402
has 128 VC descriptors in its on-chip cache providing
additional bandwidth for the whole system. Adding
external high-speed SSRAM to the 6402's local bus
increases total capacity to 64K VCs.
The IXF6402 is also capable of handling any high-level
application that relies on stateful inspection of packet
headers as they traverse an interface boundary, such as
security, firewalling, or encryption.
The IXF6402 has a sophisticated buffer management
scheme. All pointer structures (128K for transmit and 36K
for receive) are internal to the 6402 and greatly reduces the
number of read/write operations performed during lookup,
segmentation and re-assembly. Multiple buffer sizes and
non-contiguous cell splitting are fully supported in
hardware.The IXF6402 offers support for a PCI Master to
access 256 Mbyte Local Memory. It also supports a 4-
bank-structured SDRAM for Packet Buffer.
The IXF6402 supports a multitude of encapsulation
methods that accelerate packet processing at layers 2 and 3,
and can automate packet header generation using the LEC
ID, ELAN ID, MAC address or any required bit field. It
also performs LLC/SNAP encapsulation, LANE, MPLS,
IP protocols and any custom packet tagging schemes.
Unlike traditional SARs, which only link buffers to VCs
and perform no packet processing, the IXF6402 uses a two-
dimensional link list to first, link packets on a per-VC
basis, and second, link buffers on a per-packet basis with
enqueue/dequeue pointers to control the link list.
2.2 ATM Processing
In addition to features for higher layer processing, the
IXF6402 still comprises a full suite of ATM processing
functions.
Enabling tremendous flexibility to perform extensive
packet processing assist in hardware, as the IXF6402 can
differentiate between packets within a given VC. The
IXF6402 supports multiple packets per VC, with multiple
buffers per p acket. The GigaBlade subsystem uses this
feature to provide complete LANE 1.0 data path processing
in hardware.
It supports ATM AAL-0, 1, 3/4 and 5 and can deliver true
UBR, CBR, VBR and ABR for up to 64K VC's. The design
features full 64-byte VC descriptors and multiple SONET
ports.
In ATM mode, the IXF6402 provides all of the necessary
termination functions currently established by the ATM
Forum and IETF including:
• ATM Forum UNI 3.1 ATM Adaptation Layer and
ATM Layer Specifications
• ATM Forum Traffic Management Specifications,
Rev. 4.0
• RFC 1483 (Multi Protocol Encapsulation Over ATM
Adaptation Layer 5)
• RFC 1626 (Default IP MTU for Use Over ATM
AAL 5)
4
CD00032
