Features
Benefits
n
n
Integrated ATM OC-12 SAR, multi-chip OC-48
Full-duplex line rate operation for 64-byte packets
64-bit state machine architecture
Hardware encapsulation and tagging
Hardware packet formatting
100MHz Local Memory Operation
Highest performance
n
n
n
n
n
n
n
Up to 64K VC/VPs per transmit and receive
Traffic shaping resources for CBR, VBR
Granularity rates down to 1Kbps
Time wheel scheduling for ABR and other traffic types
Automates FRM cell generation and MCR support for ABR
UBR support
Dual GCRA policing per VC or VP
Weighted fair queuing and dynamic priority arbitration
Extensive traffic shaping and policing
n
n
n
n
n
n
n
n
UBR fill-in cells for maximum bandwidth utilization
n
n
LEC ID, ELAN ID, LLC/SNAP, MPOA, IP encapsulations
64-byte header
Programmable header encapsulation and tagging
LANE, MPOA, MPLS, and IP protocol assist
Support for both packet and VC tagging
Support for per-packet tagging in receive
Support for 32-bit cell-or-packet counters for receive
Ability to report the LSB 16-bit of the 32-bit cell-or-packet
Upper Layer Assist
n
n
n
n
n
n
n
counter in the receive buffer report, removing need for an
additional read operation
Support for transmit per packet offset up to 256 bytes
n
n
Support for receive start-of-packet offset for per-packet and/or
per-buffer
n
n
AAL types 0, 1, and 3/4, 5
TM 4.0 compliant
Flow control: UBR-H, UBR, CBR, VBR, VBR-rt, ABR
Full 64-byte VC descriptors
Scalable to OC-48
ATM/POS UTOPIA support
Support for multi-port POS
Feature rich
n
n
n
n
n
n
n
n
Single-port OC-12 or quad OC-3
Glueless 64-bit SSRAM and SDRAM interface
PCI 2.1 compliant 33/66MHz, 32/64-bit operations
UTOPIA levels 1, 2, and via mux
Multiple interfaces for flexible options
n
n
n
n
n
Full scatter/gather DMA for SAR
Extensive transmit and receive buffering
Two-dimensional link-list packet queuing
164K internal packet and descriptor pools
Multiple buffer sizes and cell splitting
Support for four-bank structured SDRAM
Sophisticated buffer management
n
n
n
n
n
n
n
0.35 micron, 3.1V/3.3V
3.3V/5.0V tolerant I/Os
0.35 µm CMOS design
352-pin EBGA/ABGA package
Power consumption 4.3W @ 66MHz, 8.0W @ 100MHz
Pin compatible with IXF6400 and IXF6401
State-of-the-art process technology
n
n
n
n
n
®
™
Intel Internet Exchange Architecture: A New Approach to Development
Intel is addressing today’s market challenges with a range of
development tools. Its growing suite of silicon and software
new solutions in a cohesive set of standard building blocks for
building blocks were designed to offer you:
®
network systems—the Intel Internet Exchange™ IX
(
)
n
Cost effectiveness
architecture.
n
Development efficiencies
The unique silicon and software components that comprise
the Intel® IX architecture facilitate your development of
relevant solution platforms—with scalable performance,
flexible handling of multiple protocols, and world-class
n
Seamless interoperability
The Intel IX architecture is helping to provide a comprehensive
solution now and for the future of your business.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products,
Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products
including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or
other intellectual property right. Intel products are not intended for use in medical, life-saving, or life-sustaining applications. Intel may
make changes to specifications and product descriptions at any time, without notice. Intel and Intel logo are registered and Internet
Exchange is a trademark of Intel Corporation. *All other brands and names are the property of their respective owners.
General Information Hotline +1 800.628.8686 or +1 916.356.3104 5 a.m. to 5 p.m. PST
For more information, visit the Intel Web site at: www.intel.com/IXA
Copyright © 2000 Intel Corporation
Order Number: PB-1010 Printed in USA/0600/4K/ASI/CR
