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LZ93B53

型号:

LZ93B53

描述:

同步信号发生器,用于CCD[ Synchronous Signal Generator for CCD ]

品牌:

SHARP[ SHARP ELECTRIONIC COMPONENTS ]

页数:

6 页

PDF大小:

130 K

Synchronous Signal Generator for CCD  
PIN CONNECTIONS  
DESCRIPTION  
The LZ93B53 is a CMOS synchronous signal  
generator LSI which provides B/W TV synchro-  
nous pulses and video signal processing pulses,  
in combination with the timing signal generator  
LSI (LZ93N61, LZ95F50, or LZ93F33).  
TOP VIEW  
18-PIN MFP  
CLKI 1  
0
CLKO  
2
3
4
5
17  
FEATURES  
16 VD2  
15  
.
between 270000 pixels B/W  
and 320000 pixels B/W CCD  
between EIA and CCIR systems  
CPMD  
CKMD  
14 HD2  
13 CBLK  
12 HBLK  
11 CSYN  
10  
.
VRI 6  
TSTI 7  
TST2 8  
Single + 5 V power supply  
. External synchronization is possible  
. Package : 8-pin MFP(MFPOI 8-P)  
BLOCK DIAGRAM  
BCP  
VD2  
HBLK  
CSYN  
CBLK  
7-BIT  
COUNTER  
GATE  
CONTROL  
I
TST2  
CLKO  
TVMD  
CPMD  
CKMD  
VRI  
TST  
GND  
CLKI  
ABSOLUTE MAXIMUM RATINGS  
SYMBOL  
RATING  
Power  
v
v
– 0.3 to 7.0  
VI  
Vo  
-0.3  
to  
to  
v
voltage  
Output voltage  
+ 0.3  
temperature  
–20 to +70  
Tstg  
Storage temperature  
–55 to +150  
Ta=–20 to  
MAX.  
UNIT NOTE  
DC CHARACTERISTICS  
MIN.  
3.5  
TYP.  
SYMBOL  
CONDITIONS  
v
v
Low level input voltage  
1 , 5  
1
High level input voltage  
Schmitt buffer  
Schmitt buffer  
Schmitt buffer  
=4  
level threshold voltage  
-
Low level threshold voltage  
1,0  
v
v
v
v
2
– V T -  
Hysteresis  
Low level output voltage  
High level output voltage  
0.4  
3
4
4.0  
v
v
Low level  
LOW level  
current  
current  
1.0  
High level input current  
High level input current  
VI = Vc c  
VI =  
1. 0  
6
7
60  
NOTES :  
1. Applied to inputs (IC, ICU,  
2. Applied to input  
Applied to all outputs (0).  
4. Applied to inputs  
Applied to input (lCD).  
6. Applied to inputs  
7. Applied to inputs  
) .  
2 5 1  
PIN FUNCTION  
10.  
This is a pin to input the clock which is used as  
the reference of the horizontal and vertical pulses.  
This pin should be connected to DO on the timing  
The frequency varies depending on CKMD (pin  
5) as follows.  
system  
Main clock  
1
270000 pixels fck  
360000 pixels fck  
system  
:
:
9.534964 MHz(606 fH)  
12.713285  
fH)  
.
320000 pixels fck  
:
9,656250 MHz(6I 8  
fH)  
420  
pixels  
: 12.875000 MHz(824 fH)  
This is an inverted output pin for CLKI (pin 1).  
Clock out  
o
CLKO  
2
3
This is a pin to select TV systems.  
L o w  
level  
system  
system  
TV mode select  
ICD  
High level  
:
This is  
BCPI (pin 10) within the vertical blanking period.  
High level BCPI outputs continuous pulses.  
a pin to control stop and continuance of  
Clamp pulse mode  
select  
:
CPMD  
4
Low level : BCP I stops outputting composite  
pulses while there is no effective  
pixel within the V blanking period.  
This is an input pin to switch the frequency devision  
in accordance with the area sensor as follows.  
Frequency division  
1/4  
1/3  
Clock mode select  
CKMD  
5
output  
Low  
High  
CKMD  
360000  
270000  
Number of pixels  
This is an input pin for the external V reset pulse  
which is used to apply vertical synchronization to  
the counter (2 fck counter) on the synchronization.  
This resetting takes priority over the internal reset-  
ting. Since the rise of input at  
is taken at the  
horizontal synchronous frequency (2 fH) which is two  
times as high as the internal frequency, when the  
vertical pulses which were separated in terms of  
frequency from the composite synchronous signal  
from other equipment are used, the fall must have  
VRI  
u
6
Vertical reset  
a
phase difference of less than 1/2  
with the start timing of the vertical synchronous  
signal. When the synchronization is obtained,  
the High level should be selected. The input is de-  
signed as a trigger buffer.  
compared  
This is an input pin for tests, Typically, this pin  
should be open or at the Low level.  
Test  
1
7
FUNCTION  
PIN NAME  
2
SYMBOL  
GND  
This is an input pin for tests. Typically, this pin  
should be open or at the Low level.  
Test  
This is a grounding pin.  
Ground  
9
This pin output pulse which is used to clamp opti-  
cal black on each line of the sensor output, Typi-  
cally, these are horizontal synchronization continuous  
Optical block clamp  
pulse  
o
pulses. However,  
CPMD (pin 4) to the Low  
10  
BCP I  
level allows the composite output which becomes  
the Low level while there is no effective pixel within  
the vertical blanking period.  
This pin outputs  
and  
standard composite  
Composite synchronous  
signal  
synchronous signals.  
o
o
o
11  
CSYN  
HBLK  
CBLK  
system  
system  
:
Compatible with RS-170  
.
: Compatible with  
This pin outputs a pulse to stop  
horizontal trans-  
Horizontal blanking  
pulse  
fer pulses which drive the horizontal register in the  
area sensor.  
12  
13  
This pin outputs pulses which are used for video  
blanking in the encoder.  
Composite blanking  
pulse  
.
.
system  
: 11.01  
:
V20 H is cleared.  
V25 H is cleared.  
CCIR system  
This pin outputs pulses which are synchronous with  
the start of each line and used as the H reference  
of the timing  
HD2  
HDI  
VD2  
o
o
o
0
Horizontal drive pulse 2  
Horizontal drive pulse  
Vertical drive pulse 2  
14  
15  
16  
17  
This pin outputs pulses which are synchronous with  
the start of each line and used as the H reference  
of external equipment.  
This pin outputs pulses which are obtained at the  
start of each field and used as the V reference of  
the timing  
n
This pin outputs pulses which are obtained at the  
start of each field and used as the V reference of  
external equipment.  
VDI  
Vertical drive pulse  
Power supply  
Vcc  
supply +5 V power  
:
Din (C MO S le ve l).  
ICU : In p u t p in (C MO S le ve l w ith p u ll-u p re sisto r).  
IC D  
IC SU  
o
:
In p u t p in (C MO S le ve l w ith p u ll-d o w n re sisto r).  
in p u t p in (C MO S le ve l w ith  
Outp ut p in  
:
re sisto r)  
:
TIMING DIAGRAM  
VERTICAL TIMING < EIA >  
(ODD FIELD)  
523524525  
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2 2  
n
n
n
n
n
n
H D  
VD  
CBLK  
CSYN  
n
n
u
n
I
u
n
u
u
n
u
u
u
u
u
u
u
u
n
u
u
n
u
u
n
u
n
n
u
n
u
HBLK  
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
= L  
(EVEN FIELD)  
260261 262  
265266267269269270271 272273274275276277278 279280281 282283284  
n
n
n
n
n
n
n
n
n
HD  
VD  
I
n
u
n
n
u
n
n
u
n
CBLK  
CSYN  
BCPI  
u
u
u
u
u
u
u
u
u
n
u
n
u
n
u
n
u
n
u
HBLK  
u
u
u
u
u
u
u
u
u
u
u
u
u
CPMD=L  
VERTICAL TIMING <  
>
3rd FIELD)  
622623624625  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16  
21 22 23 24  
n
n
n
n
n
n
n
n
n
n
n
u
n
n
u
n
n
n
n
n
n
u
n
n
n
HD  
VD  
CBLK  
CSYN  
u
u
u
u
u
u
u
u
u
n
u
u
n
u
u
n
u
n
n
n
HBLK  
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
CPMD=L  
(2nd, 4th FIELD)  
310311 312313314315316317318 319  
321 322323324325326327328 329  
HD  
CSYN  
BCPI  
HBLK  
u
u
u
u
11  
u
u
u
u
u
u
u
u
L1  
u
u
= L  
HORIZONTAL TIMING < EIA  
Unit  
:
HD  
CBLK  
CSYN  
(EQ)  
1.57  
–3.15  
(SAW)  
072 2,05  
BCPI  
HBLK  
1 ’  
NOTES :  
. Applied to the  
Applied to the CCD of 726 horizontal pixels  
of 542 horizontal pixels  
=
H)  
:
A= 3.88,  
B
= 2.94, C = 8 . 6 0  
= L) : A=3.93, B =2.91, C =8.57  
HORIZONTAL TIMING <  
Unit :  
HD  
CBLK  
1.55  
155  
6,21  
CSYN  
(EQ)  
–3.1  
(SAW)  
078 2.02  
HBLK  
NOTES :  
Applied to the  
of 542 horizontal pixels  
= H) : A =3.83, B =2.90, C= 9.73  
Applied to the CCD of 726 horizontal pixels  
=
L)  
:
A
B =2.87,  
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