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OZ6812B

型号:

OZ6812B

描述:

ACPI CardBus控制器[ ACPI CardBus Controller ]

品牌:

ETC[ ETC ]

页数:

13 页

PDF大小:

108 K

OZ6812  
ACPI CardBus Controller  
1998 PC Card Standard. This standard incorporates the  
new 32-bit CardBus while retaining the 16-bit PC Card  
specification as defined by PCMCIA release 2.1. CardBus  
is intended to support “temporal” add-in functions on PC  
Cards, such as Memory cards, Network interfaces,  
FAX/Modems and other wireless communication cards, etc.  
The high performance and capability of the CardBus  
interface will enable the development of many new  
functions and applications.  
FEATURES  
The OZ6812 is a PCMCIA R2/CardBus controller, providing  
the most advanced design flexibility for PC Cards that  
interface with advanced notebook designs.  
ACPI-PCI Bus Power Management Interface  
Specification Rev 1.1 Compliant  
Supports OnNow LAN wakeup, OnNow Ring Indicate,  
PCI CLKRUN#, PME#, and CardBus CCLKRUN#  
Compliant with PCI specification V2.2, 1998 PC Card  
Standard 7.0  
The OZ6812 CardBus controller is compliant with the latest  
ACPI-PCI Bus Power Management Interface Specification.  
It supports all four power states and the PME# function for  
maximum power savings and ACPI compliance. The device  
also provides a power-down mode to allow host software to  
reduce power consumption further by stopping internal  
clock distribution as well as the PC Card socket clock. In  
addition, an advanced CMOS process is utilized to  
minimize system power consumption.  
Yenta™ PCI to PCMCIA CardBus Bridge register  
compatible  
ExCA (Exchangeable Card Architecture) compatible  
registers mappable in memory and I/O space  
IntelTM 82365SL PCIC Register Compatible  
Supports PCMCIA_ATA Specification  
Supports 5V/3.3V PC Cards and 3.3V CardBus cards  
Supports single PC Card or CardBus slot with hot  
insertion and removal  
The OZ6812 single PCMCIA socket supports 3.3V/5V 8/16-  
bit PC Card R2 card or 32-bit CardBus R3 card. The R2  
card support is compatible with the Intel 82365SL PCIC  
controller, and the R3 card support is fully compliant with  
the 1998 PC Card Standard CardBus specification. The  
OZ6812 is a stand alone device, which means that it does  
not require an additional buffer chip for the PC Card socket  
interface. In addition, the OZ6812 supports dynamic PC  
Card hot insertion and removal, with auto configuration  
capabilities.  
Supports multiple FIFOs for PCI/CardBus data transfer  
Supports Direct Memory Access for PC/PCI and  
PCI/Way on PC Card socket  
Programmable interrupt protocol: PCI, PCI+ISA,  
PCI/Way, or PC/PCI interrupt signaling modes  
Win’98 IRQ and PC-98/99 compliant  
Parallel or Serial interface for socket power control  
devices including Micrel and TI  
Zoomed Video Support  
Integrated PC 98/99 -Subsystem Vendor ID support,  
with auto lock bit  
The OZ6812 is fully compliant with the 33Mhz PCI Bus  
specification, V2.2. It supports a master device with  
internal CardBus direct data transfer.  
The OZ6812  
LED Activity Pins  
implements a FIFO data buffer architecture between the  
PCI bus and CardBus socket interface to enhance data  
transfers to CardBus devices. The bi-directional FIFO  
buffer (composed of 16 double words) permits the OZ6812  
to accept data from a target bus (PCI or CardBus interface)  
while simultaneously transferring data. This architecture  
not only speeds up data transfers but also prevents system  
deadlocks.  
ORDERING INFORMATION  
OZ6812T - 144pin LQFP  
OZ6812B - 144pin Mini-BGA  
GENERAL DESCRIPTION  
The OZ6812 is an ACPI and PC98/99 logo certified, high  
performance, single slot PC Card controller with  
a
synchronous 32-bit bus master/target PCI interface. This  
PC Card to PCI bridge host controller is compliant with the  
04/25/00  
Copyright 2000 by O2Micro  
OZ6812-SF-1.5  
All Rights Reserved  
Page 1  
Patent Pending  
OZ6812  
Functional Block Diagram  
PCI Interface  
PCI  
Arbiter  
PCI Configuration/  
ACPI/ OnNow  
Power Management  
Function Control Registers  
CardBus FIFO  
Power Switch  
Interrupt  
Data Buffering  
Control  
Subsystem  
CardBus  
PCCard  
8/16  
-
a
B
it  
Machine  
PCC  
rd  
and  
Machine  
Arbiter  
Power  
Switch  
Single PC Card Interface  
Interface  
e
OZ6812-SF-1.5  
Page 2  
OZ6812  
PIN DIAGRAM - 144 Pin LQFP  
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1  
1
A16 / CCLK  
A21 / CDEVSEL#  
WE# / CGNT#  
A20 / CSTOP#  
A14 / CPERR#  
A19 / CBLOCK#  
CORE_VCC  
A13 / CPAR  
REQ#  
GNT#  
AD31  
AD30  
AD29  
GND  
AD28  
AD27  
1
1
4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 0108  
107  
2
0
4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1  
9
106  
105  
104  
103  
102  
101  
100  
99  
3
4
5
6
7
8
AD26  
A18 / RFU  
9
A8 / CCBE1#  
A17 / CAD16  
A9 / CAD14  
IOW# / CAD15  
A11 / CAD12  
GND  
AD25  
10  
11  
12  
13  
14  
15  
16  
AD24  
98  
C/BE3#  
IDSEL  
97  
96  
CORE_VCC  
AD23  
95  
94  
IORD# / CAD13  
OE# / CAD11  
CE2# / CAD10  
SOCKET_VCC  
A10 / CAD9  
AD22  
AD21  
93  
92  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
O2Micro, Inc.  
PCI_VCC  
AD20  
91  
90  
OZ6812  
RST#  
89  
PCI_CLK  
GND  
CE1# / CCBE0#  
88  
D15 / CAD8  
87  
CORE_VCC  
AD19  
86  
AD18  
D7 / CAD7  
D14 / RFU  
85  
AD17  
84  
AD16  
83  
D6 / CAD5  
C/BE2#  
FRAME#  
IRDY#  
82  
D13 / CAD6  
D5 / CAD3  
81  
80  
D12 / CAD4  
D4 / CAD1  
79  
PCI_VCC  
TRDY#  
DEVSEL#  
STOP#  
PERR#  
SERR#  
GND  
78  
D11 / CAD2  
D3 / CAD0  
77  
76  
CD1/ CCD1#  
VCCD1# / SCLK  
VCCD0# / SDATA  
75  
74  
PAR  
73  
3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7  
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2  
OZ6812-SF-1.5  
Page 3  
OZ6812  
Pin List  
Bold Text = Normal Default Pin Name  
PCI Bus Interface Pins  
Pin Number  
Power  
Rail  
PCI_Vcc  
Pin Name  
Description  
Input  
Type  
I/O  
Drive  
LQFP  
BGA  
TTL  
PCI  
Spec  
AD[31:0]  
PCI Bus Address Input / Data: These pins 3-5, 7-11, 15-  
connect to PCI bus signals AD[31:0]. A Bus 17, 19, 23-26,  
transaction consists of an address phase followed 38-41, 43, 45-  
D4, B1, C2-1,  
D2, E4, D1, E3,  
F3, F1, F2, G1,  
H2-3, J1, H4,  
M2, K4, N2,  
by one or more data phases.  
47, 49, 51-57  
M3, N3, K5,  
N4, L5, N5, L6,  
N6, M6, L7, N7,  
M7, K7  
C/BE[3:0]#  
12, 27, 37, 48  
E2, J2, N1, M5  
TTL  
I/O  
PCI_Vcc  
PCI  
PCI Bus Command  
/
Byte Enable: The  
Spec  
command signaling and byte enables are  
multiplexed on the same pins. During the address  
phase of a transaction, C/BE[3:0]# are interpreted  
as the bus commands. During the data phase,  
C/BE[3:0]# are interpreted as byte enables. The  
byte enables are to be valid for the entirety of  
each data phase, and they indicate which bytes in  
the 32-bit data path are to carry meaningful data  
for the current data phase.  
FRAME#  
Cycle Frame: This input indicates to the OZ6812  
28  
K1  
TTL  
I/O  
PCI_Vcc  
PCI  
that  
a
bus transaction is beginning.  
While  
Spec  
FRAME# is asserted, data transfers continue.  
When FRAME# is de-asserted, the transaction is  
in its final phase.  
IRDY#  
29  
31  
J3  
L1  
TTL  
TTL  
I/O  
I/O  
PCI_Vcc  
PCI_Vcc  
PCI  
Spec  
Initiator Ready: This input indicates the initiating  
agents ability to complete the current data phase  
of the transaction. IRDY# is used in conjunction  
with TRDY#.  
Target Ready: This output indicates target  
Agent's the OZ6812s ability to complete the  
current data phase of the transaction. TRDY# is  
used in conjunction with IRDY#.  
PCI  
Spec  
TRDY#  
STOP#  
IDSEL  
33  
13  
K3  
E1  
TTL  
TTL  
I/O  
I
PCI_Vcc  
PCI_Vcc  
PCI  
Spec  
Stop: This output indicates the current target is  
requesting the master to stop the current  
transaction.  
Initialization Device Select: This input is used as  
a chip select during configuration read and write  
PCI  
Spec  
transactions.  
This is a point-to-point signal.  
IDSEL can be used as a chip select during  
configuration read and write transactions.  
32  
J4  
TTL  
I/O  
PCI_Vcc  
PCI  
Spec  
DEVSEL#  
Device Select: This output is driven active LOW  
when the PCI address is recognized as  
supported, thereby acting as the target for the  
current PCI cycle. The Target must respond  
before timeout occurs or the cycle will terminate.  
PERR#  
SERR#  
34  
35  
M1  
L2  
-
-
TO  
TO  
PCI_Vcc  
PCI_Vcc  
PCI  
Spec  
Parity Error: The output is driven active LOW  
when a data parity error is detected during a write  
phase.  
System Error: This output is driven active LOW  
to indicate an address parity error.  
PCI  
Spec  
OZ6812-SF-1.5  
Page 4  
OZ6812  
Pin Number  
Power  
Pin Name  
Description  
Input  
Type  
Drive  
Rail  
LQFP  
BGA  
PAR  
Parity: This pin generates PCI parity and ensures  
even parity across AD[31:0] and C/BE[3:0]#.  
During the address phase, PAR is valid after one  
clock. With data phases, PAR is stable one clock  
after a write or read transaction.  
36  
L3  
TTL  
I/O  
PCI_Vcc  
PCI  
Spec  
21  
20  
G4  
G2  
-
-
I
PCI_Vcc  
AUX_Vcc  
-
-
PCI_CLK  
RST#  
PCI Clock: This input provides timing for all  
transactions on the PCI bus to and from the  
OZ6812. All PCI bus signals, except RST#, are  
sampled and driven on the rising edge of  
PCI_CLK. This input can be operated at  
frequencies from 0 to 33 MHz.  
I
I
Device Reset: This input is used to initialize all  
registers and internal logic to their reset states  
and place most OZ6812 pins in  
impedance state.  
a HIGH-  
2
1
B2  
A1  
TTL  
-
PCI_Vcc  
PCI_Vcc  
PCI  
Spec  
PCI  
GNT#  
REQ#  
Grant: This signal indicates that access to the bus  
has been granted.  
Request: This signal indicates to the arbiter that  
TO  
Spec  
the OZ6812 requests use of the bus.  
Power Control and General Interface Pins  
Pin Number  
LQFP  
Power  
Rail  
Pin Name  
Description  
Input  
Type  
Drive  
BGA  
59  
M8  
-
TO  
Aux_Vcc  
4mA  
RI_OUT/  
PME#  
Ring Indicate Out: This pin is Ring Indicate  
when the following occurs while O2 Mode Control  
B Register (index 2Eh) bit 7 is set to 1:  
1) Power Control (Index+02h) bit 7 set to 1  
2) Interrupt and General Control (Index+03h)  
bit 7 set to 1  
3) PCI O2Micro Control 2 (Offset: D4h) bit X =  
0
Power  
Management  
Event:  
A
power  
management event is the process by which the  
OZ6812 can request a change of its power  
consumption state. Usually,  
a PME occurs  
during a request to change from a power saving  
state to the fully operational state.  
SPKR_OUT# Speaker Output: This output can be used to  
support PC Card audio output. See O2 Mode E  
Register (Index + 3Eh), bit 1.  
62  
K8  
TTL  
I/O  
Aux_Vcc  
12mA  
MF[6:0]  
Multifunction Terminal [6:0]: See PCI  
Multifunction MUX Register (Offset:08h).  
Suspend: This signal is used to protect the  
internal registers from clearing when the PCI  
RST# signal is asserted. When low, this signal is  
used to mask the PCI RESET during suspend.  
This pin can be used during suspend to prevent  
controller reset.  
69-67, 65-64,  
61-60  
L10, K9, N11,  
L9, N10-9, L8  
N12  
TTL  
TTL  
I/O  
I
Aux_Vcc  
Aux_Vcc  
12mA  
-
SUSPEND#  
70  
OZ6812-SF-1.5  
Page 5  
OZ6812  
Pin Number  
LQFP  
Power  
Pin Name  
Description  
Input  
Type  
Drive  
Rail  
BGA  
VPPD0/  
VPPD0: This power input is used with parallel  
71  
M11  
TTL  
I/O  
Aux_Vcc  
12mA  
SLATCH  
power control chip  
SLATCH: This output controls a serial interface  
power control chip.  
VPPD1  
VPPD1: This power input is used a parallel  
power interface chip.  
VCCD0#: Rail power inputs for use with a  
parallel power control chip.  
72  
73  
L11  
-
TO  
I/O  
Aux_Vcc  
Aux_Vcc  
12mA  
12mA  
VCCD0#/  
SDATA  
N13  
TTL  
Serial Data: This pin serves as output DATA pin  
when used with a serial interface of serial power  
control chip.  
VCCD1#/  
SCLK  
VCCD1#: Rail power inputs for use with a  
parallel power control chip.  
74  
M12  
TTL  
I/O  
Aux_Vcc  
12mA  
Serial Clock: The input is used as a reference  
clock (10-100kHz, usually 32kHz) to control a  
serial power control chips. By setting PCI  
O2Micro Control 2 register (Offset:D4h) bit 13 to  
1, SCLK is an output. Default is input mode.  
OZ6812-SF-1.5  
Page 6  
OZ6812  
PC Card Socket Interface Pins  
Refer to PCI Bus Interface pin descriptions for details on CardBus function.  
EXCEPTIONS: CCD[2:1]#, CAUDIO, CSTSCHG, CVS[2:1]  
Pin Number  
Power  
Rail  
Pin Name  
Description  
Input  
Type  
Drive  
LQFP  
BGA  
REG#/  
CCBE3#  
Register Access: During PC Card memory cycles,  
this output chooses between Attribute and Common  
Memory. During I/O cycles for non-DMA transfers,  
this signal is active (low). During ATA mode, this  
signal is always inactive. For DMA cycles on the  
OZ6812 to a DMA-capable card, REG# becomes  
DACK to the PCMCIA card.  
125  
B8  
TTL  
I/O  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Command Byte Enable: In CardBus  
mode, this pin is the CCBE3#.  
A[25:24]/  
CAD[19, 17]  
Address: PC Card socket address 25:24 outputs.  
116, 113  
111  
B10, B11  
D10  
TTL  
TTL  
TTL  
TTL  
TTL  
TTL  
TTL  
TTL  
TTL  
I/O  
I/O  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Address/Data: CardBus mode, these pins  
are the CAD bits 19 and 17.  
Address: PC Card socket address 23 output.  
A23/  
CFRAME#  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Frame: In CardBus mode, this pin is the  
CFRAME# signal.  
Address: PC Card socket address 22 output.  
A22/  
CTRDY#  
109  
A13  
I/O-  
PU  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Target Ready: In CardBus mode, this pin  
is the CTRDY# signal.  
Address: PC Card socket address 21 output.  
A21/  
CDEVSEL#  
107  
C12  
I/O-  
PU  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Device Select: In CardBus mode, this pin  
is the CDEVSEL# signal.  
Address: PC Card socket address 20 output.  
A20/  
CSTOP#  
105  
D11  
I/O-  
PU  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Stop: In CardBus mode, this pin is the  
CSTOP# signal.  
Address: PC Card socket address 19 output.  
A19/  
CBLOCK#  
103  
C13  
I/O-  
PU  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Lock: In CardBus mode, this signal is the  
CBLOCK# signal used for locked transactions.  
Address: PC Card socket address 18 output.  
A18/  
RFU  
100  
D13  
TO  
I/O  
I/O  
Socket  
_Vcc  
CardBus  
spec.  
Reserved: In CardBus mode, this pin is reserved for  
future use.  
Address: PC Card socket address 17 output.  
A17/  
CAD16  
98  
F10  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Address/Data: In CardBus mode, this pin  
is the CAD bit 16.  
Address: PC Card socket address 16 output.  
A16/  
CCLK#  
108  
C11  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Clock: In CardBus mode, this pin supplies  
the clock to the inserted card.  
OZ6812-SF-1.5  
Page 7  
OZ6812  
Pin Number  
Power  
Pin Name  
A15/  
Description  
Input  
Type  
Drive  
Rail  
LQFP  
BGA  
Address: PC Card socket address 15 output.  
110  
B12  
TTL  
I/O-  
PU  
Socket  
_Vcc  
CardBus  
spec.  
CIRDY#  
CardBus Initiator Ready: In CardBus mode, this  
pin is the CIRDY# signal.  
A14/  
CPERR#  
Address: PC Card socket address 14 output.  
104  
E10  
E11  
A12  
TTL  
TTL  
TTL  
TTL  
TTL  
TTL  
TTL  
TTL  
TTL  
I/O-  
PU  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Parity Error: CardBus mode, this pin is  
the CPERR# signal.  
Address: PC Card socket address 13 output.  
A13/  
CPAR  
101  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Parity: In CardBus mode, this pin is the  
CPAR signal.  
Address: PC Card socket address 12 output.  
A12/  
CCBE2#  
112  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Command/Byte Enable: In CardBus  
mode, this pin is the CCBE2# signal.  
Address: PC Card socket address 11:9 output.  
A[11:9]/  
CAD  
[12,9,14]  
95, 89, 97  
99  
F12, H12,  
E13  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Address/Data: In CardBus mode, these  
pins are the CAD bits 12, 9 and 14.  
Address: PC Card socket address 8 output.  
A8/  
CCBE1#  
E12  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Command/Byte Enable: In CardBus  
mode, this pin is the CCBE1# signal.  
Address: PC Card socket address 7:0 outputs.  
A[7:0]/  
CAD[18]  
[20:26]  
115, 118,  
120, 121,  
124, 127,  
128, 129  
87  
A11-10, B9,  
A9-7, B7,  
D7  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Address/Data: In CardBus mode, these  
pins are the CAD bits 18 and 20:26.  
Data: PC Card socket I/O data bit 15.  
D15/  
CAD8  
H11  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Address/Data: In CardBus mode, this pin  
is the CAD bit 8.  
Data: PC Card socket I/O data bit 14.  
D14/  
RFU  
84  
J12  
Socket  
_Vcc  
CardBus  
spec.  
Reserved: In CardBus mode, this pin is reserved for  
future use.  
Data: PC Card socket I/O data bits 13:3.  
D[13:3]/  
CAD[6, 4, 2,  
82, 80, 77,  
144, 142,  
140, 85, 83,  
81, 79, 76  
K13-12,  
L12, C3,  
A2, D5,  
J13, J11,  
J10, L13,  
M13  
Socket  
_Vcc  
CardBus  
spec.  
31, 30, 28, 7, CardBus Address/Data: In CardBus mode, this pin  
5, 3, 1, 0]  
is the CAD bit 6 4, 2, 31, 30, 28, 7, 5, 3, 1, and 0,  
respectively.  
D2/  
RFU  
Data: PC Card socket I/O data bit 2.  
143  
141, 139  
92  
B3  
TTL  
TTL  
TTL  
I/O  
I/O  
I/O  
Socket  
_Vcc  
CardBus  
spec.  
Reserved: In CardBus mode, this pin is reserved for  
future use.  
Data: PC Card socket I/O data bits 1:0.  
D[1:0]/  
CAD[29,27]  
C4, A3  
G12  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Address/Data: In CardBus mode, these  
pins are the CAD bits 29 and 27, respectively.  
Output Enable: This output goes active (low) to  
indicate a memory read from the OZ6812 to PC  
Card.  
OE#/  
CAD11  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Address/Data: In CardBus mode, this pin  
is the CAD bit 11.  
WE#/  
CGNT#  
Write Enable: This output goes active (low) to  
indicate a memory write from the OZ6812 to the PC  
Card socket.  
106  
B13  
TTL  
TO  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Grant: In CardBus mode, this pin is the  
CGNT# signal.  
OZ6812-SF-1.5  
Page 8  
OZ6812  
Pin Number  
Power  
Drive  
Rail  
Pin Name  
Description  
Input  
Type  
LQFP  
BGA  
IORD#/  
CAD13  
I/O Read: This output goes active (low) for I/O  
reads from the OZ6812 to the socket.  
93  
G10  
TTL  
I/O  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Address/Data: In CardBus mode, this  
pin is the CAD bit 13.  
IOW#/  
CAD15  
I/O Write: This output goes active (low) for I/O  
writes from the OZ6812 to the socket.  
96  
F11  
A4  
TTL  
TTL  
I/O  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Address/Data: In CardBus mode, this  
pin is the CAD bit 15.  
WP/  
IOIS16#/  
CCLKRUN#  
Write Protect / I/O is 16-Bit: In Memory mode,  
this input is indicates the status of the write  
protect switch on the PC Card. In I/O mode, this  
input indicates the size of current data transfer on  
the PC Card.  
136  
I/O-PU  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Clock Run: In CardBus mode, this pin  
is the CCLKRUN# signal, which starts and stops  
the CardBus CCLK. To enable the CLKRUN#  
signal, ExCA register 3Bh bit[3:2] must be  
enabled.  
INPACK#/  
CREQ#  
Input Acknowledge: The INPACK# function is  
not applicable in PCI bus environments. This pin  
is provided for Legacy card compatibility.  
123  
132  
C8  
C6  
-
-
I-PU  
I-PU  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Request: In CardBus mode, this pin is  
the CREQ# signal.  
Ready / Interrupt Request: In Memory mode,  
this input indicates that the card is ready or busy.  
In I/O mode, this input indicates a card interrupt  
request.  
RDY/IREQ#/  
CINT#  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Interrupt: In CardBus mode, this pin is  
the CINT# signal. This signal is active-low and  
level-sensitive.  
WAIT#/  
CSERR#  
Wait: This pin is driven by the PC Card to delay  
completion of the current cycle.  
133  
A5  
TTL  
TTL  
I-PU  
Socket  
_Vcc  
CardBus  
spec.  
CardBus System Error: In CardBus mode, this  
pin is the CSERR# signal.  
Card Detect: These inputs indicate a card is  
present in the socket. They are internally pulled  
high to AUX_VCC.  
CD[2:1]/  
CCD[2:1]#  
137, 75  
C5, K10  
I-PU-  
Schmitt  
Aux_Vcc  
CardBus  
spec.  
CardBus Card Detect: In CardBus mode, these  
inputs are used with CVS[2:1] to detect presence  
and type of card.  
CE2#/  
CAD10  
Card Enable 2: This pin is driven low to control  
byte/word card access. CE2# enables odd-  
numbered address bytes.  
91  
88  
G13  
H13  
TTL  
TTL  
I/O  
I/O  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Address/Data: In CardBus mode, this  
pin is the CAD bit 10.  
CE1#/  
CCBE0#  
Card Enable 1: This pin is driven low to control  
byte/word card access. CE1# enables even-  
numbered address bytes. When configured for 8-  
bit cards, CE1# is active and A0 is used to  
indicate access of odd- or even-numbered bytes.  
Socket  
_Vcc  
CardBus  
spec.  
CardBus Command/Byte Enable: In CardBus  
mode, this pin is the CCBEO# signal.  
OZ6812-SF-1.5  
Page 9  
OZ6812  
Pin Number  
Power  
Drive  
Rail  
Pin Name  
RESET/  
Description  
Input  
Type  
TO  
LQFP  
BGA  
Reset: This active high output resets the card.  
To prevent reset glitches, this signal is high-  
impedance unless a card is seated in the  
socket, card power is applied, and the cards  
interface signals are enabled.  
119  
134  
135  
C9  
TTL  
Socket  
_Vcc  
CardBus  
spec.  
CRST#  
CardBus Reset: In CardBus mode, this pin is  
the CRST# output.  
BVD2/SPKR#/  
LED / CAUDIO  
Battery Voltage Detect 2 / Speaker / LED: In  
Memory mode, this input serves as the BVD2  
(battery warning status) input. In I/O mode, this  
input can be configured as the cards SPKR#  
audio input or drive-active LED input.  
D6  
B5  
-
-
I-PU  
I-PU  
Socket  
_Vcc  
-
-
CardBus Audio: In CardBus mode, this pin is  
the CAUDIO input.  
BVD1/  
STSCHG#/RI#/  
CSTSCHG  
Battery Voltage Detect 1 / Status Change /  
Ring Indicate: In Memory mode, this is the  
BVD1 (battery-dead status) input. In I/O mode,  
this is the STSCHG# input indicating that the  
cards internal status has changed, or the ring  
indicates input for wakeup-on-ring system  
power management support. See bit 7 of the  
Interrupt and General Control register (03h).  
Socket  
_Vcc  
CardBus Status Change: In CardBus mode,  
this pin is the CSTSCHG. This pin can be used  
to generate PME#.  
VS[2:1]/  
CVS[2:1]  
Voltage Sense: These pins are used in  
conjunction with CD[2:1] to determine the type  
and voltage of a card. These pins are internally  
pulled high to AUX_VCC. See Table 1.  
117, 131  
90, 126  
D9, B6  
TTL  
I/O-PU  
PWR  
Aux_Vcc  
CardBus  
spec.  
CardBus Voltage Sense: In CardBus mode,  
these pins are the CVS[2:1] pins.  
SOCKET_VCC  
Socket Power: These pins are the power rail  
input for the socket interface control logic.  
These pins can be 0, 3.3, or 5 V,. The socket  
interface outputs will operate at the voltage  
applied to these pins.  
G11, C7  
-
-
-
OZ6812-SF-1.5  
Page 10  
OZ6812  
Power, Ground, and Reserved Pins  
Pin Number  
Power  
Drive  
Rail  
Pin Name  
Aux_VCC  
Description  
Input  
Type  
LQFP  
BGA  
Auxiliary VCC: This pin is connected to the  
systems 3.3/5V power supply. For the device  
to 5V tolerant, connect to +5V power.  
CORE_VCC: This pin provides power to the  
core circuitry of the OZ6812. It must be  
connected to a 3.3V power supply.  
PCI Bus VCC: These pins can be connected to  
either a 3.3V or5V power supply. The PCI bus  
interface will operate at the voltage applied to  
these pins, independent of the voltage applied  
to other OZ6812 pin groups.  
63  
M9  
-
PWR  
-
-
-
-
CORE_VCC  
PCI_VCC  
14, 66, 86,  
102, 122,  
138  
F4, M10,  
H10, D12,  
D8, B4  
-
-
PWR  
PWR  
-
18, 30, 44,  
50  
G3, K2,  
M4, K6  
-
GND  
System Ground  
6, 22, 42,  
58, 78, 94,  
114, 130  
D3, H1,  
L4, N8,  
K11, F13,  
C10, A6  
-
GND  
-
-
Legend  
I/O Type  
Description  
Power Rail  
Source of Output’s Power  
I
Input Pin  
Input pin with internal pull-up  
1
2
3
AUX_VCC: outputs powered from AUX_VCC  
SOCKET_VCC: outputs powered from the socket  
PCI_VCC: outputs powered from PCI bus power  
supply  
I-PU  
I-PU Schmitt Input pin with internal pull-up and Schmitt  
trigger  
O
Output  
OD  
Open-drain  
4
CORE_VCC: outputs powered from the CORE_VCC  
TO  
Tri-state output  
TO-PU  
OD-PU  
PWR  
Tri-state output with internal pull-up  
Open-drain output with internal pull-up  
Power pin  
OZ6812-SF-1.5  
Page 11  
OZ6812  
Package Information - 144 Pin LQFP  
He  
E
2
A
1
A
Y
Hd  
D
1
L
M
0.08(0.003)  
c
e
b
MILLIMETER  
INCH  
SYMBOL  
MIN. NOM. MAX.  
MIN. NOM. MAX.  
0.05  
1.35  
0.17  
0.090  
0.10  
1.40  
0.22  
0.15  
1.45  
0.27  
0.002 0.004 0.006  
0.053 0.055 0.057  
0.007 0.009 0.011  
A1  
A2  
b
GAGE  
PLANE  
0.200 0.004  
0.008  
0.25  
c
20.00  
20.00  
0.50  
0.787  
0.787  
0.020  
0.866  
0.866  
D
L
E
e
22.00  
22.00  
0.60  
Hd  
He  
L
0.45  
0.75  
0.018 0.024 0.030  
1.00  
0.039  
L1  
Y
0.08  
7
0.003  
0
0
7
OZ6812-SF-1.5  
Page 12  
OZ6812  
144 Pin Mini - BGA  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.  
2. "e" REPRESENTS THE SOLDER BALL GRID PITCH.  
3. "N" REPRESENTS THE MAXIMUM NUMBER OF SOLDER BALLS FOR MATRIX SIZE  
M1 AND M2.  
4. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER AFTER  
REFLOW AND PARALLEL TO PRIMARY DATUM Z, THE ORIGINAL SOLDER BALL  
DIAMETER IS 0.45 mm.  
5. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL  
CROWNS OF THE SOLDER BALLS.  
6. A1 CORNER MUST BE IDENTIFIED BY INK MARK, METALLIZED MARKINGS,  
IDENTATION OR OTHER FEATURE OF PACKAGE BODY, LID OR INTEGRAL  
HEATSLUG, ON THE TOP SURFACE OF THE PACKAGE.  
7. SOLDER BALL DEPOPULATION IS ALLOWED. DEPOPULATION IS THE OMISSION OF  
BALLS FROM A FULL MATRIX (M1 OR M2).  
8. BALL PAD A1 CORNER INDICATOR (NC) SOLDER BALL  
OZ6812-SF-1.5  
Page 13  
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