LYTSwitch-6
provides current path for the charging of the bulk capacitor C4 −
especially at low-line, which improves efficiency. Free-wheel diodes
D1 and D17 provide a current path for the energy stored in the PFC
inductor that must be transferred to the secondary-side during
MOSFET off-time. The series connection of D1 and D17 are able to
withstand the resonant voltage ring from the PFC inductor when the
MOSFET turns off.
2. Efficiency assumptions depend on power level. Smallest device-
power levels assume efficiency >84% increasing to >89% for the
largest device.
3. Transformer primary inductance tolerance is ±10%.
4. Reflected output voltage (VOR) is set to maintain KP = 0.8 at
minimum input voltage for universal line, and KP = 1 for high
input line (only) designs.
5. Maximum conduction loss for adapters is limited to 0.6 W and to
During a no-load or light load condition (<10% load) the energy
stored in the PFC inductor is greater than required by the secondary
load. The excess energy from the PFC inductor is therefore recycled
to the bulk capacitor C4 boosting the voltage level. A Zener-resistor
clamp comprising of VR1 and VR2 in series with R47 is connected
across the bulk capacitor C4 to clamp this voltage below the
voltage-rating of C4. This Zener clamp voltage should be ≤450 V
(the maximum voltage rating of bulk capacitor C4). In the event of
an input line surge or transient event, the primary switching MOSFET
is protected from overvoltage by the INPUT VOLTAGE pin sense
resistors which trigger a line overvoltage shutdown at 460 V.
0.8 W for open frame designs.
6. Increased current limit is selected for peak and open-frame power
columns, while standard current limit is used for adapter columns.
7. The part is board-mounted with SOURCE pins soldered to a
sufficient area of copper and/or a heat sink to keep the SOURCE-
pin temperature ≤110 °C.
8. Ambient temperature limit is 50 °C for open frame designs and
40 °C for sealed adapters.
9. Below a value of 1, KP is the ratio of ripple to peak primary
current. To prevent reduced power delivery, due to premature
termination of switching cycles, a transient KP limit of ≥0.6 is
specified. This prevents the initial current limit (IINT) from being
exceeded at MOSFET turn-on.
10.LYTSwitch-6 parts are unique in that the designer can set the
switching frequency between 25 kHz to 95 kHz by adjusting
transformer design. One way to lower device temperature is to
design the transformer to reduce switching frequency; a good
starting point is 50 kHz.
Secondary Stage
The secondary-side control of the LYTSwitch-6 IC provides constant
output voltage and constant output current. The voltage produced
on the secondary winding of transformer T2 is rectified by D10 and
filtered by the output capacitors C16 and C18. Adding an RC snubber
(R48 and C14) across the output diode reduces voltage stress. In this
design, the SYNCHRONOUS RECTIFIER DRIVE pin is connected to
the SECONDARY GROUND pin to allow the use of a low-cost ultrafast
output diode instead of an SR FET.
Primary-Side Overvoltage Protection
Primary-side output overvoltage protection provided by the
LYTSwitch-6 IC uses an internal latch that is triggered by a threshold
current of ISD into the PRIMARY BYPASS pin. For the bypass capacitor
to be effective as a high frequency filter, the capacitor should be
located as close as possible to the SOURCE and PRIMARY BYPASS
pins of the device.
The IC secondary is self-powered from either the secondary winding
forward voltage via the FORWARD pin, or the output voltage via the
OUTPUT VOLTAGE pin. Decoupling capacitor C13 is connected to the
SECONDARY BYPASS pin. In order to meet the maximum voltage
limits of OUTPUT VOLTAGE pin in this design, the secondary-side of
the IC needs to be powered from a low voltage auxiliary supply
(winding FL3 and FL4). The FORWARD pin has to be connected to
the same output to insure good regulation and high efficiency. This
auxiliary supply is rectified and filtered by D11 and C15 respectively.
The primary sensed OVP function can be realized by connecting a
series combination of a Zener diode, a resistor and a blocking diode
from the rectified and filtered bias-winding-voltage supply to the
PRIMARY BYPASS pin (see Figure 11-a). The rectified and filtered bias
winding output voltage may be higher than anticipated (up to
2 times the desired value) and is dependent on the coupling of the
bias winding to the output winding and the resultant ringing of the
bias winding voltage waveform. It is recommended that the rectified
bias winding voltage be measured. Ideally this measurement should
be made at the lowest input voltage and with maximum load applied
the output. This measured voltage should be used to select the
components required to achieve primary sensed OVP. It is
During constant voltage operation, output voltage regulation is
achieved by sensing the output voltage via a resistor network
comprising R29 and R30. The voltage across R30 is monitored at
the FEEDBACK pin and compared to an internal reference voltage
threshold of 1.265 V. Bypass capacitor C19 is placed across the
FEEDBACK and SECONDARY GROUND pins to attenuate high
frequency noise that would otherwise couple to the feedback signal
and cause unwanted behavior such as pulse bunching.
recommended that a Zener diode is selected with a clamping voltage
approximately 6 V lower than the rectified bias winding voltage at
which OVP is expected to be triggered. A forward voltage drop of 1 V
can be assumed for the blocking diode. A small-signal standard
recovery diode is recommended for this task. The blocking diode
prevents any reverse current from charging the bias capacitor during
start-up. Finally, the value of the series resistor required can be
calculated such that a current higher than ISD will flow into the
PRIMARY BYPASS pin during an output overvoltage event.
During constant current operation, the maximum output current is set
by the sense resistors R43 and R24. The voltage across the sense
resistor is applied to the ISENSE pin internal reference threshold
of 35 mV to maintain constant current regulation. Diode D13 in
parallel with the current sense resistors clamps the voltage across the
ISENSE and SECONDARY GROUND pin. This shunts the high current
surge from the output capacitor seen during an output short-circuit
and prevents damage.
Key Applications Design Considerations
Secondary-Side Overvoltage Protection
Output Power Table
Secondary-side output overvoltage protection is provided by the
LYTSwitch-6 IC which uses an internal auto-restart circuit triggered
by an input current into the SECONDARY BYPASS pin exceeding a
threshold of IBPS(SD). The direct sensed output OVP function can
be realized by connecting a Zener diode from the output to the
SECONDARY BYPASS pin. The Zener diode voltage needs to be the
absolute value of (1.25 x VOUT) – (4.4 V − SECONDARY BYPASS pin
The output power table (Table 1) represents the maximum
continuous output power level that can be obtained under the
following conditions:
1. Minimum DC input voltage is ≥90 V for 85 VAC input and ≥220 V
for 230 VAC input (or 115 VAC with a voltage doubler). The
voltage rating of the input capacitor should be set to meet these
criteria.
10
Rev. E 06/18
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