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LY62W51216GL-70LLIT

型号：

LY62W51216GL-70LLIT

品牌：

LYONTEK[ Lyontek Inc. ]

页数：

13 页

PDF大小：

465 K

下载PDF手册
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
REVISION HISTORY  
Revision  
Rev. 1.0  
Rev. 1.1  
Rev. 1.2  
Description  
Initial Issue  
Added ISB Spec.  
Revised ICC1/ISB1/VDR/IDR Spec.  
Issue Date  
Oct.14.2007  
Feb.1.2008  
Mar.2.2009  
Revised typos in Page 1(ICC TYP.)  
Rev. 1.3  
May.7.2010  
FEATURES ORDERING INFORMATION  
Revised  
&
Lead free and green package available to Green package  
available  
ORDERING INFORMATION  
Added packing type in  
ABSOLUTE MAXIMUN RATINGS  
Deleted TSOLDER in  
PACKAGE OUTLINE DIMENSION  
Revised  
Revised VIH to 0.7*Vcc  
in page 10  
Rev. 1.4  
Rev. 1.5  
Aug.25.2010  
Apr.25.2011  
ORDERING INFORMATION  
Revised  
Deleted E grade  
in page 11  
Added SL grade  
Revised VIH in page 3  
Revised TEST CONDITION of VIH in page 3  
Rev. 1.6  
Rev. 1.7  
May.13.2011  
Jul.27.2011  
PACKAGE OUTLINE DIMENSION  
Revised  
in page 10  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
FEATURES  
GENERAL DESCRIPTION  
The LY62W51216 is a 8,388,608-bit low power  
CMOS static random access memory organized as  
524,288 words by 16 bits. It is fabricated using very  
high performance, high reliability CMOS technology.  
Its standby current is stable within the range of  
operating temperature.  
Fast access time : 55/70ns  
Low power consumption:  
Operating current : 30/20mA (TYP.)  
Standby current : 6A (TYP.) LL-version  
3A (TYP.) SL-version  
Single 2.7V ~ 5.5V power supply  
All inputs and outputs TTL compatible  
Fully static operation  
Tri-state output  
Data byte control : LB# (DQ0 ~ DQ7)  
UB# (DQ8 ~ DQ15)  
Data retention voltage : 1.5V (MIN.)  
Green package available  
Package : 44-pin 400 mil TSOP-II  
48-ball 6mm x 8mm TFBGA  
The LY62W51216 is well designed for low power  
application, and particularly well suited for battery  
back-up nonvolatile memory application.  
The LY62W51216 operates from a single power  
supply of 2.7V ~ 5.5V and all inputs and outputs are  
fully TTL compatible  
PRODUCT FAMILY  
Power Dissipation  
Speed  
Product  
Family  
Operating  
Temperature  
Vcc Range  
Standby(ISB1,TYP.) Operating(Icc,TYP.)  
0 ~ 70℃  
LY62W51216  
2.7 ~ 5.5V  
2.7 ~ 5.5V  
55/70ns  
55/70ns  
6µA(LL)/3µA(SL)  
6µA(LL)/3µA(SL)  
30/20mA  
30/20mA  
-40 ~ 85℃  
LY62W51216(I)  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
SYMBOL  
DESCRIPTION  
Address Inputs  
A0 - A18  
Vcc  
Vss  
DQ0 – DQ15 Data Inputs/Outputs  
CE#  
WE#  
OE#  
LB#  
UB#  
VCC  
Chip Enable Input  
Write Enable Input  
Output Enable Input  
Lower Byte Control  
Upper Byte Control  
Power Supply  
512Kx16  
MEMORY ARRAY  
A0-A18  
DECODER  
VSS  
Ground  
DQ0-DQ7  
Lower Byte  
I/O DATA  
CIRCUIT  
COLUMN I/O  
DQ8-DQ15  
Upper Byte  
CE#  
WE#  
OE#  
LB#  
CONTROL  
CIRCUIT  
UB#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
PIN CONFIGURATION  
A4  
A3  
1
2
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A5  
A6  
A2  
3
A7  
A1  
4
OE#  
UB#  
LB#  
DQ15  
DQ14  
DQ13  
DQ12  
Vss  
A0  
5
CE#  
DQ0  
DQ1  
DQ2  
DQ3  
Vcc  
Vss  
DQ4  
DQ5  
DQ6  
DQ7  
WE#  
A18  
A17  
A16  
A15  
A14  
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
Vcc  
LB# OE# A0  
DQ8 UB# A3  
DQ9 DQ10 A5  
A1  
A2  
NC  
A
B
C
D
E
F
DQ11  
DQ10  
DQ9  
DQ8  
A8  
A4 CE# DQ0  
A6 DQ1 DQ2  
Vss DQ11 A17 A7 DQ3 Vcc  
Vcc DQ12 NC A16 DQ4 Vss  
DQ14 DQ13 A14 A15 DQ5 DQ6  
DQ15 NC A12 A13 WE# DQ7  
A9  
A10  
A11  
A12  
A13  
G
H
A18 A8  
A9 A10 A11 NC  
1
2
3
4
5
6
TSOP II  
TFBGA  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
-0.5 to 6.5  
VT2  
-0.5 to VCC+0.5  
0 to 70(C grade)  
-40 to 85(I grade)  
-65 to 150  
1
V
℃
Operating Temperature  
TA  
℃
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this  
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
TRUTH TABLE  
I/O OPERATION  
MODE  
CE# OE# WE# LB# UB#  
SUPPLY CURRENT  
DQ0-DQ7  
DQ8-DQ15  
H
X
X
X
H
H
L
L
L
X
X
X
X
X
X
H
L
X
L
H
L
L
X
H
X
L
H
L
L
H
L
L
High – Z  
High – Z  
High – Z  
High – Z  
DOUT  
High – Z  
DOUT  
DIN  
High – Z  
DIN  
High – Z  
High – Z  
High – Z  
High – Z  
High – Z  
DOUT  
DOUT  
High – Z  
DIN  
Standby  
ISB,ISB1  
ICC,ICC1  
ICC,ICC1  
L
L
L
L
L
L
L
L
H
H
H
H
H
L
Output Disable  
Read  
Write  
L
L
H
L
ICC,ICC1  
DIN  
Note: H = VIH, L = VIL, X = Don't care.  
DC ELECTRICAL CHARACTERISTICS  
SYMBOL  
TEST CONDITION  
MIN.  
2.7  
2.2  
2.4  
- 0.2  
- 1  
TYP. *4  
3.0  
MAX.  
5.5  
VCC+0.5  
VCC+0.5  
0.6  
UNIT  
PARAMETER  
Supply Voltage  
VCC  
V
V
V
V
VCC = 2.7 ~ 3.6V  
VCC = 4.5 ~ 5.5V  
-
-
-
-
*1  
Input High Voltage  
VIH  
*2  
Input Low Voltage  
Input Leakage Current  
Output Leakage  
Current  
Output High Voltage  
Output Low Voltage  
VIL  
ILI  
V
V
CC ≧ VIN ≧ VSS  
CC ≧ VOUT ≧ VSS,  
Output Disabled  
IOL = 2mA  
1
A
µ
ILO  
- 1  
-
1
A
µ
VOH IOH = -1mA  
VOL  
2.4  
-
2.7  
-
-
V
V
0.4  
Cycle time = Min.  
CE# = VIL , II/O = 0mA  
Other pins at VIL or VIH  
30  
20  
60  
50  
- 55  
- 70  
-
-
mA  
ICC  
mA  
Average Operating  
Power supply Current  
Cycle time = 1 s  
µ
ICC1  
ISB  
-
4
12  
mA  
mA  
CE# = 0.2V , II/O = 0mA  
Other pins at 0.2V or VCC - 0.2V  
CE# = VIH, Other pins at VIL or VIH  
LL  
-
-
-
-
-
-
-
0.15  
6
6
3
3
2
30  
50  
10  
10  
20  
25  
A
A
A
A
A
A
µ
µ
µ
µ
µ
µ
LLI  
Standby Power  
Supply Current  
CE# ≧VCC - 0.2V  
Others at 0.2V or  
VCC - 0.2V  
SL*5  
℃
25  
ISB1  
SLI*5  
℃
40  
SL  
3
3
SLI  
Notes:  
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.  
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.  
3. Over/Undershoot specifications are characterized, not 100% tested.  
4. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical values are measured at VCC = VCC(TYP.) and TA = 25  
5. This parameter is measured at VCC = 3.0V  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
CAPACITANCE (TA = 25℃, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
MIN.  
-
-
MAX  
6
8
UNIT  
pF  
pF  
CIN  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
PARAMETER  
SYM.  
tRC  
UNIT  
LY62W51216-55  
LY62W51216-70  
MIN.  
MAX.  
MIN.  
MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
LB#, UB# Access Time  
55  
-
-
-
70  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
55  
55  
30  
-
70  
70  
35  
-
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
-
-
*
*
*
10  
5
-
-
10  
-
10  
5
-
-
10  
-
-
-
20  
20  
-
55  
25  
-
25  
25  
-
70  
30  
-
tOHZ  
tOH  
tBA  
*
LB#, UB# to High-Z Output  
LB#, UB# to Low-Z Output  
tBHZ  
*
-
10  
-
10  
tBLZ  
*
(2) WRITE CYCLE  
PARAMETER  
SYM.  
tWC  
tAW  
tCW  
tAS  
UNIT  
LY62W51216-55  
LY62W51216-70  
MIN.  
55  
50  
50  
0
MAX.  
MIN.  
70  
60  
60  
0
MAX.  
Write Cycle Time  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
LB#, UB# Valid to End of Write  
-
-
tWP  
tWR  
tDW  
tDH  
tOW  
45  
0
-
-
55  
0
-
-
25  
0
-
-
30  
0
-
-
*
5
-
5
-
tWHZ  
*
-
45  
20  
-
-
60  
25  
-
tBW  
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
LB#,UB#  
tBA  
OE#  
tOE  
tOH  
tOLZ  
tBLZ  
tCLZ  
tOHZ  
tBHZ  
tCHZ  
High-Z  
Dout  
High-Z  
Data Valid  
Notes :  
1.WE#is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.  
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.  
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)  
tWC  
Address  
tAW  
CE#  
tCW  
tBW  
LB#,UB#  
WE#  
tAS  
tWP  
tWR  
tWHZ  
TOW  
High-Z  
Dout  
(4)  
(4)  
tDW  
tDH  
Din  
Data Valid  
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)  
tWC  
Address  
tAW  
CE#  
tAS  
tWR  
tCW  
tBW  
LB#,UB#  
tWP  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
WRITE CYCLE 3 (LB#,UB# Controlled)  
(1,2,5,6)  
tWC  
Address  
tAW  
tWR  
CE#  
tAS  
tCW  
tBW  
LB#,UB#  
WE#  
tWP  
tWHZ  
High-Z  
Dout  
Din  
(4)  
tDW  
tDH  
Data Valid  
Notes :  
1.WE#,CE#, LB#, UB# must be high during all address transitions.  
2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.  
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be  
placed on the bus.  
4.During this period, I/O pins are in the output state, and input signals must not be applied.  
5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance  
state.  
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
for Data Retention  
SYMBOL  
TEST CONDITION  
CE# ≧ VCC - 0.2V  
MIN.  
1.5  
TYP. MAX. UNIT  
V
CC  
VDR  
-
5.5  
30  
50  
10  
10  
20  
25  
V
LL  
LLI  
-
-
-
-
-
-
4
4
3
3
3
3
A
µ
µ
µ
µ
µ
µ
A
A
A
A
A
VCC = 1.5V  
CE# ≧ VCC - 0.2V  
Other pins at 0.2V or VCC-0.2V  
℃
℃
25  
40  
SL  
SLI  
Data Retention Current  
IDR  
SL  
SLI  
Chip Disable to Data  
Retention Time  
Recovery Time  
See Data Retention  
Waveforms (below)  
tCDR  
tR  
0
-
-
-
-
ns  
ns  
tRC  
*
tRC = Read Cycle Time  
*
DATA RETENTION WAVEFORM  
Low Vcc Data Retention Waveform (1) (CE# controlled)  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
CE# ≧ Vcc-0.2V  
VIH  
CE#  
Low Vcc Data Retention Waveform (2) (LB#, UB# controlled)  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
LB#,UB# ≧ Vcc-0.2V  
VIH  
LB#,UB#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
PACKAGE OUTLINE DIMENSION  
Ⅱ
44-pin 400mil TSOP-  
Package Outline Dimension  
DIMENSIONS IN MILLMETERS  
DIMENSIONS IN MILS  
SYMBOLS  
MIN.  
-
NOM.  
-
MAX.  
1.20  
0.15  
1.05  
0.45  
0.21  
18.618  
12.014  
10.363  
-
MIN.  
NOM.  
-
MAX.  
A
A1  
A2  
b
-
47.2  
5.9  
41.3  
17.7  
8.3  
733  
473  
408  
-
0.05  
0.95  
0.30  
0.12  
18.212  
11.506  
9.957  
-
0.10  
1.00  
-
2.0  
37.4  
11.8  
4.7  
717  
453  
392  
-
3.9  
39.4  
-
c
-
-
D
18.415  
11.760  
10.160  
0.800  
0.50  
0.805  
-
725  
463  
400  
31.5  
19.7  
31.7  
-
E
E1  
e
L
0.40  
-
0.60  
-
15.7  
-
23.6  
-
ZD  
y
Θ
-
0.076  
6o  
-
3
0o  
3o  
0o  
3o  
6o  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
48-ball 6mm × 8mm TFBGA Package Outline Dimension  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
ORDERING INFORMATION  
LY62W51216 U V - WW XX Y Z  
Z : Packing Type  
Blank : Tube or Tray  
Tray : 44-pin 400 mil TSOP-II  
48-ball 6 mm x 8 mm TFBGA  
T : Tape Reel  
Y : Temperature Range  
Blank : (Commercial) 0°C ~ 70°C  
I : (Industrial) -40°C ~ +85°C  
XX : Power Type  
LL : Ultra Low Power  
SL : Special Ultra Low Power  
WW : Access Time(Speed)  
V : Lead Information  
L : Green Package  
U : Package Type  
M : 44-pin 400 mil TSOP-II  
G : 48-ball 6 mm x 8 mm TFBGA  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
11  
LY62W51216  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.7  
THIS PAGE IS LEFT BLANK INTENTIONALLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
12  
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