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LY61L12816AML-8IT

型号：

LY61L12816AML-8IT

品牌：

LYONTEK[ Lyontek Inc. ]

页数：

12 页

PDF大小：

265 K

下载PDF手册
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
REVISION HISTORY  
Revision  
Rev. 1.0  
Description  
Initial Issue  
Issue Date  
March. 07. 2013  
Revise “TEST CONDITION” for VOH, VOL on page 3  
OH = -8mA revised as -4mA  
IOL =4mA revised as 8mA  
Rev. 1.1  
June. 04. 2013  
I
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
GENERAL DESCRIPTION  
FEATURES  
The LY61L12816A is a 2,087,152-bit high speed  
CMOS static random access memory organized as  
131,072 words by 16 bits. It is fabricated using very  
high performance, high reliability CMOS technology.  
Its standby current is stable within the range of  
operating temperature.  
„ Fast access time : 8/10ns  
„ Low power consumption:  
Operating current:  
50/40mA(TYP.)  
Standby current:  
2mA(TYP.)  
„ Single 3.3V power supply  
„ All inputs and outputs TTL compatible  
„ Fully static operation  
The LY61L12816A operates from a single power  
supply of 3.3V and all inputs and outputs are fully  
TTL compatible  
„ Tri-state output  
„ Data byte control : LB# (DQ0 ~ DQ7)  
UB# (DQ8 ~ DQ15)  
„ Data retention voltage : 1.5V (MIN.)  
„ Green package available  
„ Package : 44-pin 400 mil TSOP-II  
PRODUCT FAMILY  
Power Dissipation  
Speed  
Product  
Family  
Operating  
Temperature  
Vcc Range  
Standby(ISB1,TYP.) Operating(ICC1,TYP.)  
2.7 ~ 3.6V  
3.0 ~ 3.6V  
2.7 ~ 3.6V  
3.0 ~ 3.6V  
10ns  
8ns  
10ns  
8ns  
2mA  
2mA  
2mA  
2mA  
40mA  
50mA  
40mA  
50mA  
0 ~ 70℃  
LY61L12816A  
-40 ~ 85℃  
LY61L12816A(I)  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
SYMBOL  
A0 - A16  
DQ0 – D15  
CE#  
DESCRIPTION  
Vcc  
Vss  
Address Inputs  
Data Inputs/Outputs  
Chip Enable Inputs  
Write Enable Input  
Output Enable Input  
Lower Byte Control  
Upper Byte Control  
Power Supply  
128Kx16  
MEMORY ARRAY  
A0-A16  
DECODER  
WE#  
OE#  
LB#  
UB#  
DQ0-DQ7  
Lower Byte  
VCC  
I/O DATA  
CIRCUIT  
COLUMN I/O  
DQ8-DQ15  
Upper Byte  
VSS  
Ground  
NC  
No Connection  
CE#  
WE#  
OE#  
LB#  
CONTROL  
CIRCUIT  
UB#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
PIN CONFIGURATION  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
-0.5 to 4.6  
VT2  
-0.5 to VCC+0.5  
0 to 70(C grade)  
-40 to 85(I grade)  
-65 to 150  
V
℃
Operating Temperature  
TA  
℃
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
1
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this  
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
TRUTH TABLE  
I/O OPERATION  
MODE  
Standby  
CE# OE# WE# LB# UB#  
SUPPLY CURRENT  
DQ0-DQ7  
High – Z  
High – Z  
High – Z  
DOUT  
DQ8-DQ15  
High – Z  
High – Z  
High – Z  
High – Z  
DOUT  
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
X
X
X
X
H
X
H
H
H
L
X
X
H
L
H
L
L
H
L
X
X
H
H
L
L
H
L
ISB,ISB1  
ICC,ICC1  
Output Disable  
Read  
High – Z  
DOUT  
ICC,ICC1  
DOUT  
DIN  
High – Z  
DIN  
High – Z  
DIN  
Write  
L
L
ICC,ICC1  
L
DIN  
Note: H = VIH, L = VIL, X = Don't care  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
DC ELECTRICAL CHARACTERISTICS  
SYMBOL  
TEST CONDITION  
MIN.  
3.0  
2.7  
2.2  
- 0.3  
- 1  
TYP. *4  
3.3  
MAX.  
3.6  
3.6  
VCC+0.3  
0.8  
UNIT  
PARAMETER  
Supply Voltage  
-8  
-10  
V
V
V
V
VCC  
3.3  
*1  
Input High Voltage  
Input Low Voltage  
Input Leakage Current  
Output Leakage  
Current  
VIH  
VIL  
-
-
-
*2  
ILI  
V
V
CC ≧ VIN ≧ VSS  
CC ≧ VOUT ≧ VSS,  
Output Disabled  
IOL = 8mA  
1
A
µ
ILO  
- 1  
-
1
A
µ
Output High Voltage  
Output Low Voltage  
VOH IOH = -4mA  
VOL  
2.4  
-
-
-
-
V
V
0.4  
Cycle time = Min.  
CE# = VIL, II/O = 0mA,  
Others at VIL or VIH  
-8  
-
65  
80  
mA  
Average Operating  
Power supply Current  
ICC  
-10  
-
50  
70  
mA  
mA  
≦
CE# 0.2,  
Others at 0.2V or Vcc-0.2V  
-8  
-
50  
60  
Average Operating  
Power supply Current  
ICC1  
-10  
-
-
40  
-
55  
30  
mA  
mA  
II/O = 0mA;f=max  
ISB  
CE# =VIH, Others at VIL or VIH  
Standby Power  
Supply Current  
≧
CE# VCC - 0.2V,  
ISB1  
-
2
10  
mA  
Others at 0.2V or VCC - 0.2V  
Notes:  
1. VIH(max) = VCC + 2.0V for pulse width less than 6ns.  
2. VIL(min) = VSS - 2.0V for pulse width less than 6ns.  
3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test.  
4. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical valued are measured at VCC = VCC(TYP.) and TA = 25  
Typical valued are measured at VCC = VCC(TYP.) and TA = 25  
℃
CAPACITANCE (TA = 25℃, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
MIN.  
-
-
MAX  
8
10  
UNIT  
pF  
pF  
CIN  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Speed  
8/10ns  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
LY61L12816A-8  
LY61L12816A-10  
PARAMETER  
SYM.  
tRC  
tAA  
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
UNIT  
MIN.  
MAX.  
MIN.  
MAX.  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
LB#, UB# Access Time  
8
-
-
8
10  
-
-
-
10  
10  
4.5  
-
-
8
-
4.5  
-
-
-
*
*
*
2
0
-
2
0
-
-
4
3
tOHZ  
tOH  
tBA  
*
-
3
-
4
2
-
-
-
2
-
-
-
4.5  
3
4.5  
4
LB#, UB# to High-Z Output  
tBHZ  
*
LB#, UB# to Low-Z Output  
tBLZ  
*
0
-
0
-
(2) WRITE CYCLE  
PARAMETER  
LY61L12816A-8  
LY61L12816A-10  
SYM.  
tWC  
UNIT  
MIN.  
8
MAX.  
MIN.  
10  
8
MAX.  
Write Cycle Time  
-
-
-
-
-
-
-
-
-
3
-
-
-
-
-
-
-
-
-
-
4
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAW  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
LB#, UB# Valid to End of Write  
6.5  
6.5  
0
tCW  
tAS  
8
0
8
0
tWP  
tWR  
tDW  
tDH  
tOW  
6.5  
0
5
6
0
2
-
0
2
-
*
tWHZ  
*
tBW  
6.5  
8
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
LB#,UB#  
tBA  
OE#  
tOE  
tOH  
tOLZ  
tBLZ  
tCLZ  
tOHZ  
tBHZ  
tCHZ  
High-Z  
Dout  
High-Z  
Data Valid  
Notes :  
1.WE# is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low.  
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.  
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)  
tWC  
Address  
tAW  
CE#  
tCW  
tBW  
LB#,UB#  
WE#  
tAS  
tWP  
tWR  
tWHZ  
TOW  
High-Z  
Dout  
(4)  
(4)  
tDW  
tDH  
Din  
Data Valid  
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)  
tWC  
Address  
tAW  
CE#  
tAS  
tWR  
tCW  
tBW  
LB#,UB#  
tWP  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
WRITE CYCLE 3 (LB#,UB# Controlled)  
(1,2,5,6)  
tWC  
Address  
tAW  
tWR  
CE#  
tAS  
tCW  
tBW  
LB#,UB#  
WE#  
tWP  
tWHZ  
High-Z  
Dout  
Din  
(4)  
tDW  
tDH  
Data Valid  
Notes :  
1.WE#, CE# must be high during all address transitions.  
2.A write occurs during the overlap of a low CE#, low WE#.  
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be  
placed on the bus.  
4.During this period, I/O pins are in the output state, and input signals must not be applied.  
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.  
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
VCC for Data Retention  
SYMBOL TEST CONDITION  
VDR CE# ≧ VCC - 0.2V  
VCC = 1.5V  
MIN.  
1.5  
TYP.  
-
MAX.  
3.6  
UNIT  
V
Data Retention Current  
IDR  
CE# ≧ VCC - 0.2V  
-
2
10  
mA  
Others at 0.2V or Vcc – 0.2V  
Chip Disable to Data  
Retention Time  
Recovery Time  
See Data Retention  
Waveforms (below)  
tCDR  
tR  
0
-
-
-
-
ns  
ns  
tRC  
*
tRC = Read Cycle Time  
*
DATA RETENTION WAVEFORM  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
PACKAGE OUTLINE DIMENSION  
Ⅱ
44-pin 400mil TSOP-  
Package Outline Dimension  
DIMENSIONS IN MILLMETERS  
DIMENSIONS IN MILS  
SYMBOLS  
MIN.  
-
NOM.  
-
MAX.  
1.20  
0.15  
1.05  
0.45  
0.21  
18.618  
12.014  
10.363  
-
MIN.  
NOM.  
-
MAX.  
A
A1  
A2  
b
-
47.2  
5.9  
41.3  
17.7  
8.3  
733  
473  
408  
-
0.05  
0.95  
0.30  
0.12  
18.212  
11.506  
9.957  
-
0.10  
1.00  
-
2.0  
37.4  
11.8  
4.7  
717  
453  
392  
-
3.9  
39.4  
-
c
-
-
D
18.415  
11.760  
10.160  
0.800  
0.50  
0.805  
-
725  
463  
400  
31.5  
19.7  
31.7  
-
E
E1  
e
L
0.40  
-
0.60  
-
15.7  
-
23.6  
-
ZD  
y
-
0o  
0.076  
6o  
-
0o  
3
6o  
3o  
3o  
Θ
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
ORDERING INFORMATION  
Package Type  
Access Time  
(Speed)(ns)  
Temperature  
Packing  
Type  
Lyontek Item No.  
Range(℃)  
44Pin(400mil)  
TSOP-II  
8
Tray  
LY61L12816AML-8  
LY61L12816AML-8T  
LY61L12816AML-8I  
LY61L12816AML-8IT  
LY61L12816AML-10  
LY61L12816AML-10T  
LY61L12816AML-10I  
℃
℃
~70  
0
Tape Reel  
Tray  
℃
℃
-40 ~85  
Tape Reel  
Tray  
10  
℃
℃
~70  
0
Tape Reel  
Tray  
℃
℃
-40 ~85  
Tape Reel  
LY61L12816AML-10IT  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
®
LY61L12816A  
128K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.1  
THIS PAGE IS LEFT BLANK INTENTIONALLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
11  
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