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LY62L204916A_16

型号：

LY62L204916A_16

品牌：

LYONTEK[ Lyontek Inc. ]

页数：

12 页

PDF大小：

369 K

下载PDF手册
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
REVISION HISTORY  
Revision  
Rev. 1.0  
Rev. 1.1  
Description  
Initial Issue  
Typo error on page 9, revised as 8mmx10mm.  
Issue Date  
Nov. 06. 2012  
Dec.18. 2012  
Rev. 1.2  
1. Revise ISB1 on page 4 & IDR on page 8  
Jun. 10. 2013  
2.Revise VIH(max) & VIL(min) note on page 4  
VIH(max) = VCC + 2.0V for pulse width less than 6ns.  
VIL(min) = VSS - 2.0V for pulse width less than 6ns.  
Rev. 1.3  
Deleted WRITE CYCLE Notes :  
1.WE#,CE#, LB#, UB# must be high or CE2 must be low during  
all address transitions.  
Jun. 29. 2016  
In page 7  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
FEATURE  
GENERAL DESCRIPTION  
„ Fast access time : 55/70ns  
„ Low power consumption:  
The LY62L204916A is a 33,554,432-bit low power  
CMOS static random access memory organized as  
2,097,152 words by 16 bits. It is fabricated using very  
high performance, high reliability CMOS technology.  
Its standby current is stable within the range of  
operating temperature.  
Operating current : 45/30mA (TYP.)  
Standby current : 6μA (TYP.) SL-version  
„ Single 2.7V ~ 3.6V power supply  
„ All inputs and outputs TTL compatible  
„ Fully static operation  
„ Tri-state output  
„ Data byte control : LB# (DQ0 ~ DQ7)  
UB# (DQ8 ~ DQ15)  
The LY62L204916A is well designed for low power  
application, and particularly well suited for battery  
back-up nonvolatile memory application.  
The LY62L204916A operates from a single power  
supply of 2.7V ~ 3.6V and all inputs and outputs are  
fully TTL compatible  
„ Data retention voltage : 1.2V (MIN.)  
„ Green package available  
„ Package : 48-ball 8mm x 10mm TFBGA  
PRODUCT FAMILY  
Operating  
Product  
Power Dissipation  
Temperatur Vcc Range  
Speed  
Family  
Standby(ISB1,TYP.) Operating(Icc,TYP.)  
e
0 ~ 70℃  
LY62L204916A  
2.7 ~ 3.6V  
2.7 ~ 3.6V  
55/70ns  
55/70ns  
6µA(SL)  
6µA(SL)  
45/30mA  
45/30mA  
-40 ~ 85℃  
LY62L204916A(I)  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
SYMBOL  
DESCRIPTION  
Address Inputs  
A0 – A20  
Vcc  
Vss  
DQ0 – DQ15 Data Inputs/Outputs  
CE#, CE2  
WE#  
OE#  
Chip Enable Input  
Write Enable Input  
Output Enable Input  
Lower Byte Control  
Upper Byte Control  
Power Supply  
2048Kx16  
MEMORY ARRAY  
A0-A20  
DECODER  
LB#  
UB#  
VCC  
VSS  
Ground  
DQ0-DQ7  
Lower Byte  
I/O DATA  
CIRCUIT  
COLUMN I/O  
DQ8-DQ15  
Upper Byte  
CE#  
CE2  
WE#  
OE#  
LB#  
CONTROL  
CIRCUIT  
UB#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
PIN CONFIGURATION  
LB# OE# A0  
DQ8 UB# A3  
DQ9 DQ10 A5  
A1  
A2 CE2  
A
B
C
D
E
F
A4 CE# DQ0  
A6 DQ1 DQ2  
Vss DQ11 A17 A7 DQ3 Vcc  
Vcc DQ12 NC A16 DQ4 Vss  
DQ14 DQ13 A14 A15 DQ5 DQ6  
DQ15 A19 A12 A13 WE# DQ7  
G
H
A18 A8  
A9 A10 A11 A20  
1
2
3
4
5
6
TFBGA(See through with Top View)  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
-0.5 to 4.6  
-0.5 to VCC+0.5  
0 to 70(C grade)  
-40 to 85(I grade)  
-65 to 150  
1
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
VT2  
V
℃
Operating Temperature  
TA  
℃
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating  
only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is  
not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
TRUTH TABLE  
I/O OPERATION  
DQ0-DQ7 DQ8-DQ15  
MODE  
CE# CE2 OE# WE# LB#  
UB#  
SUPPLY CURRENT  
H
X
X
L
L
L
L
L
L
L
L
X
X
X
H
H
L
L
L
X
X
X
X
X
X
H
H
H
H
H
L
X
X
H
L
X
L
H
L
L
H
L
X
X
H
X
L
H
L
L
High – Z  
High – Z  
High – Z  
High – Z  
High – Z  
DOUT  
High – Z  
DOUT  
DIN  
High – Z  
DIN  
High – Z  
High – Z  
High – Z  
High – Z  
High – Z  
High – Z  
DOUT  
DOUT  
High – Z  
DIN  
X
L
ISB,ISB1  
ICC,ICC1  
Standby  
X
H
H
H
H
H
H
H
H
Output Disable  
Read  
ICC,ICC1  
H
L
L
Write  
L
L
ICC,ICC1  
DIN  
Note: H = VIH, L = VIL, X = Don't care.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
DC ELECTRICAL CHARACTERISTICS  
SYMBOL  
TEST CONDITION  
MIN.  
2.7  
2.2  
- 0.2  
- 1  
TYP. *4 MAX.  
UNIT  
PARAMETER  
Supply Voltage  
Input High Voltage  
Input Low Voltage  
Input Leakage Current  
VCC  
3.0  
3.6  
VCC+0.3  
0.6  
V
V
V
*1  
VIH  
VIL  
-
-
-
*2  
ILI  
≧
≧
≧
1
A
µ
VCC  
VCC  
VIN  
VSS  
Output Leakage  
Current  
≧
VSS  
VOUT  
ILO  
- 1  
-
1
A
µ
Output Disabled  
Output High Voltage  
Output Low Voltage  
VOH IOH = -1mA  
2.2  
-
2.7  
-
-
V
V
VOL  
IOL = 2mA  
0.4  
45  
80  
- 55  
- 70  
-
mA  
Cycle time = Min.  
CE# = VIL and CE2 = VIH  
I/O = 0mA  
Other pins at VIL or VIH  
ICC  
I
Average Operating  
Power supply Current  
-
-
30  
10  
60  
20  
mA  
mA  
Cycle time = 1 s  
µ
≦
≧
CE# 0.2V and CE2 VCC-0.2V  
ICC1  
II/O = 0mA  
Other pins at 0.2V or VCC-0.2V  
CE# = VIH or CE2 = VIL  
Other pins at VIL or VIH  
mA  
ISB  
-
0.3  
2
25℃  
40℃  
-
-
-
-
6
6
6
6
16  
16  
60  
80  
A
µ
A
µ
A
µ
A
µ
- SL  
- SLI  
Standby Power  
Supply Current  
CE# ≧VCC-0.2V  
≦
ISB1  
or CE2 0.2V  
Other pins at 0.2V  
or VCC-0.2V  
-SL  
-SLI  
Notes:  
1. VIH(max) = VCC + 2.0V for pulse width less than 6ns.  
2. VIL(min) = VSS - 2.0V for pulse width less than 6ns.  
3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test.  
4. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical values are measured at VCC = VCC(TYP.) and TA = 25  
CAPACITANCE (TA = 25℃, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
MIN.  
-
-
MAX  
6
8
UNIT  
pF  
pF  
CIN  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
PARAMETER  
SYM.  
tRC  
UNIT  
LY62L204916A-55  
LY62L204916A-70  
MIN.  
MAX.  
MIN.  
MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
LB#, UB# Access Time  
55  
-
-
-
70  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
55  
55  
30  
-
70  
70  
35  
-
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
-
-
*
*
*
10  
5
-
-
10  
-
10  
5
-
-
10  
-
-
-
20  
20  
-
55  
25  
-
25  
25  
-
70  
30  
-
tOHZ  
tOH  
tBA  
*
LB#, UB# to High-Z Output  
LB#, UB# to Low-Z Output  
tBHZ  
*
-
10  
-
10  
tBLZ  
*
(2) WRITE CYCLE  
PARAMETER  
SYM.  
tWC  
tAW  
tCW  
tAS  
UNIT  
LY62L204916A-55  
LY62L204916A-70  
MIN.  
55  
50  
50  
0
MAX.  
MIN.  
70  
60  
60  
0
MAX.  
Write Cycle Time  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
LB#, UB# Valid to End of Write  
-
-
tWP  
tWR  
tDW  
tDH  
tOW  
45  
0
-
-
55  
0
-
-
25  
0
-
-
30  
0
-
-
*
5
-
5
-
tWHZ  
*
-
20  
-
60  
25  
-
tBW  
45  
-
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
CE2  
LB#,UB#  
tBA  
OE#  
tOE  
tOH  
tOHZ  
tBHZ  
tCHZ  
tOLZ  
tBLZ  
tCLZ  
High-Z  
High-Z  
Dout  
Data Valid  
Notes :  
1.WE#is high for read cycle.  
2.Device is continuouSLy selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low.  
3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting  
parameter.  
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
WRITE CYCLE 1 (WE# Controlled) (1,2,4,5)  
tWC  
Address  
tAW  
CE#  
tCW  
CE2  
tBW  
tWP  
LB#,UB#  
tAS  
tWR  
WE#  
tWHZ  
TOW  
High-Z  
Dout  
Din  
(4)  
(4)  
tDW  
tDH  
Data Valid  
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,4,5)  
tWC  
Address  
tAW  
CE#  
CE2  
tAS  
tWR  
tCW  
tBW  
LB#,UB#  
tWP  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
WRITE CYCLE 3 (LB#,UB# Controlled)  
(1,4,5)  
tWC  
tWR  
tCW  
tBW  
tWP  
Address  
tAW  
CE#  
tAS  
CE2  
LB#,UB#  
WE#  
tWHZ  
High-Z  
Dout  
Din  
(4)  
tDW  
tDH  
Data Valid  
Notes :  
1.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low.  
2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed  
on the bus.  
3.During this period, I/O pins are in the output state, and input signals must not be applied.  
4.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a  
high impedance state.  
5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
SYMBOL  
TEST CONDITION  
MIN. TYP. MAX. UNIT  
VCC for Data Retention  
VDR  
≧
≦
1.2  
-
3.6  
16  
16  
60  
80  
V
CE# VCC - 0.2V or CE2 0.2V  
25℃  
40℃  
-
-
-
-
6
6
6
6
A
-SL  
-SLI  
-SL  
-SLI  
µ
µ
µ
µ
VCC = 1.2V  
CE# ≧VCC-0.2V or CE2 0.2V  
other pins at 0.2V or VCC-0.2V  
A
A
A
Data Retention Current  
IDR  
≦
Chip Disable to Data  
Retention Time  
Recovery Time  
See Data Retention  
Waveforms (below)  
tCDR  
tR  
0
-
-
-
-
ns  
ns  
tRC  
*
tRC = Read Cycle Time  
*
DATA RETENTION WAVEFORM  
Low Vcc Data Retention Waveform (1) (CE# controlled)  
VDR ≧ 1.2V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
CE# ≧ Vcc-0.2V  
VIH  
CE#  
Low Vcc Data Retention Waveform (2) (CE2 controlled)  
VDR ≧ 1.2V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
CE2 ≦ 0.2V  
CE2  
VIL  
VIL  
Low Vcc Data Retention Waveform (3) (LB#, UB# controlled)  
VDR ≧ 1.2V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
LB#,UB# ≧ Vcc-0.2V  
VIH  
LB#,UB#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
PACKAGE OUTLINE DIMENSION  
48-ball 8mm × 10mm TFBGA Package Outline Dimension  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
ORDERING INFORMATION  
Package  
Type  
Access Time  
(Speed)(ns)  
Power Type  
Temperature Packing  
Type  
Lyontek Item No.  
Range(℃)  
48-ball  
55  
Special Ultra Low  
Power  
Tray  
LY62L204916AGL-55SL  
℃
℃
~70  
0
8mmx10mm  
TFBGA  
Tape Reel LY62L204916AGL-55SLT  
Tray LY62L204916AGL-55SLI  
Tape Reel LY62L204916AGL-55SLIT  
Tray LY62L204916AGL-70SL  
Tape Reel LY62L204916AGL-70SLT  
Tray LY62L204916AGL-70SLI  
Tape Reel LY62L204916AGL-70SLIT  
℃
℃
-40 ~85  
70  
Special Ultra Low  
Power  
℃
℃
~70  
0
℃
℃
-40 ~85  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
®
LY62L204916A  
2048K X 16 BIT LOW POWER CMOS SRAM  
Rev.1.3  
THIS PAGE IS LEFT BLANK INTENTIONASLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
11  
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 		LY611024JL-12LL 128K ×8位高速CMOS SRAM[ 128K X 8 BIT HIGH SPEED CMOS SRAM ] 13 页

LYONTEK

 		LY611024JL-12LLE 128K ×8位高速CMOS SRAM[ 128K X 8 BIT HIGH SPEED CMOS SRAM ] 13 页

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