256Kb EEPROM
MYXX28HC256
Write Operation Status Bits
Device Operation
The MYXX28HC256 provides the user two write operation status
bits. These can be used to optimize a system write cycle time. The
status bits are mapped onto the I/O bus as shown in Figure 3.
Read
Read operations are initiated by both OE# and CE# LOW. The read
operation is terminated by either CE# or OE# returning HIGH. This
two line control architecture eliminates bus contention in a system
environment. The data bus will be in a high impedance state when
either OE# or CE# is HIGH.
Figure 3 - Status Bit Assignment
I/O DP TB
5
4
3
2
1
0
Write
RESERVED
TOGGLE BIT
Write operations are initiated when both CE# and WE# are LOW and
OE# is HIGH. The MYXX28HC256 supports both a CE# and WE#
controlled write cycle. That is, the address is latched by the falling
edge of either CE# or WE#, whichever occurs last. Similarly, the
data is latched internally by the rising edge of either CE# or WE#,
whichever occurs first. A byte write operation, once initiated, will
automatically continue to completion, typically within 3ms.
DATA POLLING
DATA Polling (I/O7)
The MYXX28HC256 features DATA Polling as a method to indicate to
the host system that the byte write or page write cycle has completed.
DATA Polling allows a simple bit test operation to determine the
status of the MYXX28HC256, eliminating additional interrupt inputs
or external hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the complement of
Page Write Operation
The page write feature of the MYXX28HC256 allows the entire
memory to be written in typically 0.8 seconds. Page write allows
up to one hundred twenty-eight bytes of data to be consecutively
written to the MYXX28HC256 prior to the commencement of the
internal programming
that data on I/O (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx).
7
Once the programming cycle is complete, I/O will reflect true data.
7
Toggle Bit (I/O6)
cycle. The host can fetch data from another device within the
system during a page write operation (change the source address),
but the page address (A7 through A14) for each subsequent valid
write cycle to the part during this operation must be the same as the
initial page address.
The MYXX28HC256 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle I/O will toggle from HIGH to LOW and LOW to
6
HIGH on subsequent attempts to read the device. When the internal
cycle is complete the toggling will cease and the device will be
accessible for additional read and write operations.
The page write mode can be initiated during any write operation.
Following the initial byte write cycle, the host can write an additional
one to one hundred twentyseven bytes in the same manner as the
first byte was written. Each successive byte load cycle, started by
the WE# HIGH to LOW transition, must begin within 100ms of the
falling edge of the preceding WE#. If a subsequent WE# HIGH to
LOW transition is not detected within 100ms, the internal automatic
programming cycle will commence. There is no page write window
limitation. Effectively the page write window is infinitely wide, so
long as the host continues to access the device within the byte load
cycle time of 100ms.
MYXX28HC256
Revision 1.4 - 02/13
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