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6V49205BNLGI

型号：

6V49205BNLGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

16 页

PDF大小：

275 K

下载PDF手册
Freescale P10XX and P20XX System Clock  
w/Selectable DDR Frequency  
6V49205B  
DATASHEET  
General Description  
Recommended Application  
System Clock for Freescale P10xx and P20xx-based designs  
The 6V49205B is a main clock for Freescale P10xx and  
P20xx-based systems. It has a selectable System CCB clock  
and 2 DDRCLK speeds – 100M or 66.66M. The 6V49205B  
also provides LP-HCSL PCIe outputs for low power and  
reduced board space.  
Features  
• Replaces 11 crystals, 2 oscillators and 3 clock generators;  
lowers cost, power and area  
• Integrated terminations on LP-HCSL PCIe outputs;  
Output Features  
• 1 - Sys_CCB 3.3V LVCMOS output @ 100M/83.33M/  
80M/66.66M  
2
eliminate 24 resistors, saving 41mm of board area  
• Industrial temperature range operation; supports  
demanding environmental conditions  
1
• 1 - DDRCLK 3.3V LVCMOS output @ 100M or 66.66M  
• 1 - 125M 3.3V LVCMOS output  
• Advanced 3.3V CMOS process; high-performance,  
low-power  
• 6 - LP-HCSL PCIe pairs selectable @ 100M or 125M  
• 6 - 25MHz 3.3V LVCMOS outputs  
• Supports independent spread spectrum on  
Sys_CCB/DDRCLK and PCIe outputs  
• 2 - 2.048M 3.3V LVCMOS outputs  
• 2 - USB 3.3V LVCMOS outputs @12M or 24M  
• Available in space-saving 7x7mm 48-pin VFQFPN with  
0.5mm pad pitch; reduced board space without the need for  
fine-pitch assembly techniques  
Key Specifications  
• PCIe Gen1-2-3 compliant  
• <3p rms phase noise on REF outputs  
Block Diagram  
Sys_CCB  
PLL1  
SCLK  
(SS)  
DDRCLK  
SDATA  
Control  
Logic  
^FS0  
^FS1  
100MHz  
^SEL100#_66  
PLL4  
PCIe_L(5:0)  
(SS)  
^SELPCIE125#_100  
PLL3  
(non-  
USB_CLK(2:1)  
X1  
2.048M(1:0)  
SS)  
Crystal  
Oscillator  
25MHz  
Crystal  
PLL2  
(non-  
SS)  
125M  
X2  
REF(5:0)  
GND  
Note 1: For DDR Clock: Processor core and I/O supply rails must be ramped with VDD3P3 or earlier. Clock signal will be  
clamped LOW and output clock will be 100MHz if this is not followed (see diagram below).  
VDD3P3  
R40  
10K  
DDRCLK  
R39  
10K  
6V49205B REVISION R 11/23/16  
1
©2016 Integrated Device Technology, Inc.  
6V49205B DATASHEET  
Pin Assignments  
X2_25 1  
X1_25 2  
48 VDDREF  
47 SDATA  
GNDREF 3  
46 SCLK  
REF5 4  
45 GndDDR  
REF4 5  
REF3 6  
44 ^SEL100#_66/DDRCLK  
43 VddDDR  
VDDREF 7  
GNDREF 8  
42 AVDDSYS  
41 Sys_CCB  
40 GNDSYS  
REF2 9  
REF1 10  
39 GNDPCIe  
38 PCIeT_LR5  
37 PCIeC_LR5  
36 PCIeT_LR4  
35 PCIeC_LR4  
34 GNDPCIe  
33 AVDDPCIe  
32 PCIeT_LR3  
31 PCIeC_LR3  
30 PCIeT_LR2  
29 PCIeC_LR2  
28 GNDPCIe  
27 VDDPCIe  
26 PCIeT_LR1  
25 PCIeC_LR1  
^SELPCIE125#_100/REF0 11  
AVDD12_24 12  
^FS0/USB_CLK1 13  
^FS1/USB_CLK2 14  
GND12_24 15  
GND2.048 16  
CK2.048_0 17  
CK2.048_1 18  
VDD2.048 19  
AVDD125 20  
125M 21  
GND125M 22  
PCIeT_LR0 23  
PCIeC_LR0 24  
48-Pin TSSOP  
^ Indicates Internal 100kohm pull up resistor  
48 47 46 45 44 43 42 41 40 39 38 37  
X2_25 1  
36 PCIeT_LR4  
35 PCIeC_LR4  
34 GNDPCIe  
33 AVDDPCIe  
32 PCIeT_LR3  
31 PCIeC_LR3  
30 PCIeT_LR2  
29 PCIeC_LR2  
28 GNDPCIe  
27 VDDPCIe  
X1_25 2  
GNDREF 3  
REF5 4  
REF4 5  
REF3 6  
6V49205B  
VDDREF 7  
GNDREF 8  
REF2 9  
REF1 10  
^SELPCIE125#_100/REF0 11  
AVDD12_24 12  
26 PCIeT_LR1  
25 PCIeC_LR1  
13 14 15 16 17 18 19 20 21 22 23 24  
48-Pin VFQFPN  
^ Indicates Internal 100kohm pull up resistor  
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
2
REVISION R 11/23/16  
6V49205B DATASHEET  
Pin Descriptions  
PIN #  
1
2
3
4
5
6
7
8
PIN NAME  
PIN TYPE  
OUT  
IN  
DESCRIPTION  
X2_25  
X1_25  
Crystal output, Nominally 25.00MHz.  
Crystal input, Nominally 25.00MHz.  
Ground pin for the REF outputs.  
Copy of crystal input  
Copy of crystal input  
Copy of crystal input  
Ref, XTAL power supply, nominal 3.3V  
Ground pin for the REF outputs.  
Copy of crystal input  
GNDREF  
REF5  
PWR  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
REF4  
REF3  
VDDREF  
GNDREF  
REF2  
9
10  
REF1  
Copy of crystal input  
Latched input to select the PCIe output frequency/REF0 output.  
0 = 125M  
1 = 100M  
^SELPCIE125#_100/RE  
F0  
11  
I/O  
12  
13  
AVDD12_24  
PWR  
I/O  
Power for 12_24MHz PLL core, and outputs. Nominal 3.3V  
Frequency select latch for Sys_CCB / 12 or 24MHz USB clock output. 3.3V. This pin has an  
internal pull up resistor.  
^FS0/USB_CLK1  
Frequency select latch for Sys_CCB / 12 or 24MHz USB clock output. 3.3V. This pin has an  
internal pull up resistor.  
14  
^FS1/USB_CLK2  
I/O  
15  
16  
17  
18  
19  
20  
21  
22  
23  
GND12_24  
GND2.048  
CK2.048_0  
CK2.048_1  
VDD2.048  
AVDD125  
125M  
PWR  
PWR  
OUT  
OUT  
PWR  
PWR  
OUT  
PWR  
OUT  
Ground pin for 12_24M outputs.  
Ground pin for 2.048M outputs.  
2.048M output, nominal 3.3V.  
2.048M output, nominal 3.3V.  
Power supply for 2.048M outputs, nominal 3.3V.  
Power for 125MHz PLL core and output, nominal 3.3V  
125M output, nominal 3.3V.  
Ground pin for 125M outputs.  
GND125M  
PCIeT_LR0  
True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor  
Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series  
resistor  
Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series  
resistor  
24  
25  
PCIeC_LR0  
PCIeC_LR1  
OUT  
OUT  
26  
27  
28  
PCIeT_LR1  
VDDPCIe  
GNDPCIe  
OUT  
PWR  
PWR  
True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor  
Power supply for PCI Express outputs, nominal 3.3V  
Ground pin for the PCIe outputs.  
Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series  
resistor  
True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor  
Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series  
29  
30  
31  
PCIeC_LR2  
PCIeT_LR2  
PCIeC_LR3  
OUT  
OUT  
OUT  
resistor  
32  
33  
34  
PCIeT_LR3  
AVDDPCIe  
GNDPCIe  
OUT  
PWR  
PWR  
True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor  
Analog Power supply for PCI Express clocks, nominal 3.3V  
Ground pin for the PCIe outputs.  
Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series  
resistor  
True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor  
Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series  
35  
36  
37  
PCIeC_LR4  
PCIeT_LR4  
PCIeC_LR5  
OUT  
OUT  
OUT  
resistor  
38  
39  
40  
41  
42  
43  
PCIeT_LR5  
GNDPCIe  
GNDSYS  
Sys_CCB  
AVDDSYS  
VddDDR  
OUT  
PWR  
PWR  
OUT  
PWR  
PWR  
True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor  
Ground pin for the PCIe outputs.  
Ground pin for the Sys_CCB output  
System CCB clock output  
Analog Power supply for Sys_CCB clock and outputs, nominal 3.3V  
Power supply for DDR Clock output, nominal 3.3V  
Latched input to select the DDR output frequency/DDRCLK output. See note regarding system  
power sequencing.  
44  
^SEL100#_66/DDRCLK  
I/O  
0 = 100M  
1 = 66.666M  
45  
46  
47  
48  
GndDDR  
SCLK  
SDATA  
VDDREF  
PWR  
IN  
I/O  
Ground pin for the DDR outputs.  
Clock pin of SMBus circuitry.  
Data pin for SMbus circuitry.  
Ref, XTAL power supply, nominal 3.3V  
PWR  
REVISION R 11/23/16  
3
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
6V49205B DATASHEET  
Table 1: PCIEX Spread Table (selectable via SMBUS)  
SELPCIE125#_100  
B0b4  
B0b3  
Spread %  
B6b4  
0 (125MHz)  
1 (100MHz)  
1 (100MHz)  
1 (100MHz)  
1 (100MHz)  
x
0
0
1
1
x
0
1
0
1
No Spread  
No Spread (default)  
Down -0.5%  
Down -0.75%  
No Spread  
*Once in spread mode, do not return to non spread without reset  
Table 2: Sys_CCB and DDR Spread Table (selectable via SMBUS)  
B0b7  
B0b6  
B0b5  
Spread %  
No Spread (default)  
Down -0.5%  
Down -0.75%  
Down -0.25%  
Down -1%  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Down -1.25%  
Down -1.5%  
Down -2%  
Table 3: Sys_CCB Frequency Select Table (Latched and selectable via SMBUS)  
FS1 /  
B4b3  
FS0 /  
B4b2  
Sys_CCB (MHz)  
0
0
0
0
0
0
1
1
66.66  
100  
80  
83.33  
Table 4: PCI Express Amplitude Control  
B6b7  
B6b6  
PCIe Amplitude  
700mV  
0
0
1
1
0
1
0
1
800mV  
900mV  
1000mV  
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
4
REVISION R 11/23/16  
6V49205B DATASHEET  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 6V49205B. These ratings, which are standard  
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other  
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the  
recommended operating temperature range.  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Notes  
Maximum Supply Voltage  
VDDxxx  
Supply Voltage  
4.6  
V
1
Maximum Input Voltage  
Minimum Input Voltage  
Storage Temperature  
VIH  
VIL  
Ts  
Referenced to GND  
VDD + 0.5  
V
1
1
Referenced to GND  
-
GND - 0.5  
-65  
V
°C  
°C  
V
150  
125  
JunctionTemperature  
Input ESD protection  
Tj  
-
1
1
ESD prot  
Human Body Model  
2000  
NOTES on Absolute Max Parameters  
1 Operation under these conditions is neither implied, nor guaranteed.  
Electrical Characteristics - Input/Supply/Common Output DC Parameters  
TAMB = -40 to +85°C; VDD = 3.3 V +/-5%, All outputs driving test loads (unless noted otherwise).  
PARAMETER  
Ambient Operating Temp  
Supply Voltage  
SYMBOL  
TAMB  
CONDITIONS  
MIN  
-40  
TYP  
25  
MAX  
85  
UNITS  
°C  
Notes  
-
VDDxxx  
TPWRRMP  
Supply Voltage  
3.135  
3.3  
3.465  
4
V
Power supply Ramp Time  
Power supply ramp must be montonic  
ms  
Latched Input High Voltage  
VIH_LI  
Single-ended Latched Inputs  
2.1  
VSS - 0.3  
-5  
VDD + 0.3  
V
Latched Input Low Voltage  
Input Leakage Current  
Operating Supply Current  
Input Frequency  
VIL_LI  
IIN  
IDDOP3.3  
Fi  
Single-ended Latched Inputs  
VIN = VDD , VIN = GND  
0.8  
5
V
uA  
2
3
All outputs loaded and running  
155  
27  
mA  
MHz  
119  
23  
25  
Pin Inductance  
Lpin  
5
7
nH  
CIN  
COUT  
CINX  
Logic Inputs  
Output pin capacitance  
X1 & X2 pins  
1.5  
3
5
5
5
6
6
pF  
pF  
pF  
Input Capacitance  
Clk Stabilization  
From VDD Power-Up or de-assertion of PD  
to 1st clock  
TSTAB  
3.2  
5
ms  
Tfall_SE  
Trise_SE  
TFALL  
TRISE  
VDD  
10  
10  
ns  
ns  
V
1
1
Fall/rise time of all 3.3V control inputs from  
20-80%  
SMBus Voltage  
2.7  
4
3.3  
0.4  
Low-level Output Voltage  
Current sinking at  
VOLSMB  
@ IPULLUP  
V
IPULLUP  
TRI2C  
SMB Data Pin  
mA  
ns  
V
OLSMB = 0.4 V  
SCLK/SDATA  
Clock/Data Rise Time  
SCLK/SDATA  
(Max VIL - 0.15) to  
(Min VIH + 0.15)  
(Min VIH + 0.15) to  
(Max VIL - 0.15)  
1000  
TFI2C  
300  
400  
ns  
Clock/Data Fall Time  
SMBus Operating Frequency  
FSMBUS  
kHz  
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).  
1 Signal is required to be monotonic in this region.  
2 Input leakage current does not include inputs with pull-up or pull-down resistors  
3 For margining purposes only. Normal operation should have Fin =25MHz  
REVISION R 11/23/16  
5
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
6V49205B DATASHEET  
AC Electrical Characteristics - Low Power HCSL-Compatible PCIe Outputs  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
100.00  
125.00  
0
MAX  
UNITS  
MHz  
MHz  
NOTES  
2,3  
2,3  
Clock Frequency  
f
Spread off  
ppmSSof f  
ppmSSon  
tSLEW  
PCIe 100MHz or 125MHz  
PCIe @ -0.5% spread, 100MHz only  
Differential Measurement  
Single-ended Measurement  
Includes overshoot  
ppm  
ppm  
V/ns  
%
1,2  
1,2  
Synthesis error  
+/-100  
4.1  
Rising/Falling Edge Slew Rate  
Slew Rate Variation  
2.2  
5.7  
20  
1,3,6  
1,6  
tSLVAR  
1
Maximum Output Voltage  
Minimum Output Voltage  
Differential Voltage Swing  
Crossing Point Voltage  
Crossing Point Variation  
Duty Cycle  
VHIGH  
793  
-22  
1150  
mV  
mV  
mV  
mV  
mV  
%
6,7  
VLOW  
Includes undershoot  
-300  
300  
300  
6,7  
VSWING  
VXABS  
VXABSVAR  
DCYC  
Differential Measurement  
Single-ended Measurement  
Single-ended Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
1,6  
419  
115  
50.1  
36  
550  
140  
55  
1,4,6  
1,4,5  
1
45  
30  
PCIe Jitter - Cycle to Cycle  
PCIe[5:0] Skew  
PCIeJC2C  
TSKEwPCIe50  
125  
1500  
ps  
1
1172  
ps  
1,6,8  
Spread Spectrum Modulation  
Frequency  
fSSMOD  
Triangular Modulation  
31.5  
33  
kHz  
Notes for PCIe Clocks:  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Clock Frequency specifications are guaranteed assuming that REF is at 25MHz  
3 Slew rate measured through V_swing voltage range centered about differential zero  
4 Vcross is defined at the voltage where Clock = Clock#.  
5 Only applies to the differential rising edge (Clock rising, Clock# falling.)  
6 At default SMBus settings.  
7 The Freescale P-series CPU's have internal terminations on their SerDes Reference Clock inputs. The resulting amplitude at these inputs will be 1/2 of the  
values listed, which are well within the 800mV Freescale specification for these inputs.  
8 This value includes an intentional output-to-output skew of approximately 250ps.  
Electrical Characteristics - Phase Jitter, PCIe Outputs at 100MHz  
INDUSTRY  
TYP  
PARAMETER  
SYMBOL  
tjphPCIe1  
CONDITIONS  
PCIe Gen 1 phase jitter  
PCIe Gen 2 phase jitter  
Lo-band content  
PCIe Gen 2 phase jitter  
Hi-band content  
MIN  
MAX  
56  
SPEC LIMIT UNITS NOTES  
35  
86  
ps  
ps  
(RMS)  
ps  
1,2,3  
tjphPCIe2Lo  
tjphPCIe2Hi  
tjphPCIe3  
1.6  
1.9  
0.5  
2.4  
2.8  
3
1,2,3  
Jitter, Phase  
3.1  
1
1,2,3  
1,2,3  
(RMS)  
ps  
PCIe Gen 3 phase jitter  
0.83  
(RMS)  
Notes on Phase Jitter:  
1 See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production.  
2 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12  
3 Applies to PCIe outputs @ default amplitude and 100MHz with spread off or at -0.5%.  
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
6
REVISION R 11/23/16  
6V49205B DATASHEET  
Electrical Characteristics - DDR Clock  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
NOTES  
66.666  
fDDR66.66  
SEL100#_66 = 1, VT = OVDD/2 V  
MHz  
2,3,6  
DDR Clock Frequency  
100.00  
0
fDDR100  
ppmSSof f  
ppmSSon  
VOH  
SEL100#_66 = 0, VT = OVDD/2 V  
Spread off  
MHz  
ppm  
ppm  
V
2,3,6  
1,2,5  
1,2,5  
1
Synthesis error  
+/-150  
Spread on  
Output High Voltage  
Output Low Voltage  
VOH at the selected operating frequency  
VOL at the selected operating frequency  
'00' = Hi-Z  
2.4  
VOL  
0.4  
V
1
Hi-Z  
1.6  
2.3  
2.7  
51.4  
±96  
10  
tSLEW00  
tSLEW01  
tSLEW10  
tSLEW11  
dt1  
V/ns  
V/ns  
V/ns  
V/ns  
%
'01' Slow Slew Rate (Averaging on)  
'10' Fast Slew Rate (Averaging on)  
'11' Fastest Slew Rate (Averaging on)  
VT = OVDD/2 V  
1.1  
1.6  
1.8  
40  
2.3  
3.2  
1,3,8  
1,3,8  
1,3,8  
1,6  
Slew Rate  
VDDO = 3.3V  
3.7  
Duty Cycle  
Jitter, Peak period jitter  
Phase Noise  
60  
tjpeak  
VT = OVDD/2 V  
±150  
500  
ps  
1,6  
tphasenoise  
-56dBc  
kHz  
1,7  
AC Input Swing Limits @ 3.3V  
OVDD  
This is the difference between VOL and  
VOH at the selected operating frequency.  
V
1.9  
30  
3.4  
V
1
ꢀ
AC  
Spread Spectrum Modulation  
Frequency  
fSSMOD  
Triangular Modulation  
32.3  
60  
kHz  
Electrical Characteristics - Sys_CCB  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
66.666  
100.00  
80.00  
83.333  
0
MAX  
UNITS  
MHz  
MHz  
MHz  
MHz  
NOTES  
2,3,6  
2,3,6  
2,3,6  
2,3,6  
FS(1:0) = 00, VT = OVDD/2 V  
FS(1:0) = 01, VT = OVDD/2 V  
FS(1:0) = 10, VT = OVDD/2 V  
FS(1:0) = 11, VT = OVDD/2 V  
Clock Frequency  
fSys_CCB  
ppmSSof f  
ppmSSon  
VOH  
Spread off  
Spread on  
ppm  
ppm  
V
1,2,5  
1,2,5  
1
Synthesis error  
+/-150  
Output High Voltage  
Output Low Voltage  
VOH at the selected operating frequency  
VOL at the selected operating frequency  
'00' = Hi-Z  
2.4  
VOL  
0.4  
V
1
Hi-Z  
1.4  
tSLEW00  
tSLEW01  
tSLEW10  
tSLEW11  
dt1  
V/ns  
V/ns  
V/ns  
V/ns  
%
'01' Slow Slew Rate (Averaging on)  
'10' Fast Slew Rate (Averaging on)  
'11' Fastest Slew Rate (Averaging on)  
VT = OVDD/2 V  
0.8  
0.9  
1.1  
40  
2.1  
2.5  
3.1  
60  
1,3,8  
1,3,8  
1,3,8  
1,6  
Slew Rate  
VDDO = 3.3V  
1.6  
1.9  
Duty Cycle  
Jitter, Peak period jitter  
Phase Noise  
51.4  
±116  
10  
tjpeak  
VT = OVDD/2 V, SSC < 0.75%  
-56dBc  
150  
ps  
1
±
tphasenoise  
500  
kHz  
1,7  
AC Input Swing Limits @ 3.3V  
OVDD  
This is the difference between VOL and  
VOH at the selected operating frequency.  
V
1.9  
0
V
1
ꢁ
AC  
Spread Spectrum Modulation  
Frequency  
fSSMOD  
Triangular Modulation  
31.5  
60  
kHz  
Electrical Characteristics - 125M  
PARAMETER  
Clock frequency  
Synthesis error  
SYMBOL  
CONDITIONS  
MIN  
TYP  
125.00  
MAX  
UNITS  
ns  
NOTES  
2,3,6  
1,2,5  
1
f125M  
VT = OVDD/2 V  
ppm  
0
ppm  
V
Output High Voltage  
VOH  
VOH at the selected operating frequency  
VOL at the selected operating frequency  
2.2  
Output Low Voltage  
VOL  
0.5  
1
V
1
Rise/Fall time  
VDDO = 3.3V  
tRF125M3.3V  
Measured between 0.6V and 2.7V  
0.7  
52  
ns  
1,3  
Duty Cycle  
dt1  
VT = OVDD/2 V  
VT = OVDD/2 V  
47  
53  
%
1
1
Jitter, Peak period jitter  
tjpeak  
150  
ps  
±
REVISION R 11/23/16  
7
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
6V49205B DATASHEET  
Electrical Characteristics - REF(5:0)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
25.00  
MAX  
UNITS  
MHz  
ppm  
V
NOTES  
2,3  
Clock Frequency  
f
VT = OVDD/2 V  
Crystal Frequency Error  
Output High Voltage  
ppm  
VOH  
VOL  
Including all aging and tuning effects  
VOH at the selected operating frequency  
VOL at the selected operating frequency  
-50  
2.2  
50  
1,2  
1
Output Low Voltage  
Slew Rate  
0.4  
2.7  
60  
V
V/ns  
%
1
1,3,4  
1
tSLEW  
dt1  
'00' = Hi-Z  
1.0  
40  
1.7  
51  
Duty Cycle  
VT = OVDD/2 V  
VT = 1.5 V, odd/even outputs have an  
intentional 180degree phase shift.  
VT = OVDD/2 V  
Pin to Pin Skew  
tskew  
N/A  
ps  
1
Jitter, Peak period jitter  
Jitter, Phase  
tjpeak  
±78  
1.7  
±200  
3
ps  
1
1
tjphase  
(12kHz-5MHz), VT = 1.5 V  
ps rms  
Electrical Characteristics - USB_CLK(2:1)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
12.00  
MAX  
UNITS  
MHz  
MHz  
ppm  
NOTES  
2,3  
Clock Frequency  
fUSB_CLK  
VT = OVDD/2 V  
24.00  
0
2,3  
Synthesis error  
Output High Voltage  
Output Low Voltage  
ppm  
VOH  
1,2,5  
VOH at the selected operating frequency  
VOL at the selected operating frequency  
'00' = Hi-Z  
2.2  
V
V
1
1
VOL  
0.4  
Hi-Z  
1.4  
2.0  
2.3  
50.3  
23  
tSLEW00  
tSLEW01  
tSLEW10  
tSLEW11  
dt1  
V/ns  
V/ns  
V/ns  
V/ns  
%
'01' Slow Slew Rate (Averaging on)  
'10' Fast Slew Rate (Averaging on)  
'11' Fastest Slew Rate (Averaging on)  
VT = OVDD/2 V  
1.0  
1.5  
1.8  
45  
1.8  
2.7  
3.1  
55  
1,3,4  
1,3,4  
1,3,4  
1
Slew Rate  
VDDO = 3.3V  
Duty Cycle  
Jitter, RMS  
tjRMS  
12kHz to Nyquist  
120  
350  
ps  
1
Jitter, Cycle to cycle  
tjcyc-cyc  
VT = OVDD/2 V  
142  
ps  
1
Electrical Characteristics - 2.048M(1:0)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
NOTES  
2.048  
Clock Frequency  
fUSB_CLK  
VT = OVDD/2 V  
MHz  
2,3,6  
0
Synthesis error  
Output High Voltage  
Output Low Voltage  
ppm  
VOH  
ppm  
V
1,2,5  
VOH at the selected operating frequency  
VOL at the selected operating frequency  
'00' = Hi-Z  
2.2  
1
1
VOL  
0.4  
V
Hi-Z  
1.7  
tSLEW00  
tSLEW01  
tSLEW10  
tSLEW11  
dt1  
V/ns  
V/ns  
V/ns  
V/ns  
%
'01' Slow Slew Rate (Averaging on)  
'10' Fast Slew Rate (Averaging on)  
'11' Fastest Slew Rate (Averaging on)  
VT = OVDD/2 V  
1.1  
1.6  
1.8  
45  
2.5  
3.2  
3.6  
55  
1,3,4  
Slew Rate  
VDDO = 3.3V  
2.3  
1,3,4  
2.6  
1,3,4  
Duty Cycle  
Pin to Pin Skew  
Jitter, RMS  
46.7  
108  
47  
1
1
1
1
tskew  
VT = OVDD/2 V  
250  
70  
ps  
tjRMS  
12kHz to Nyquist  
ps  
Jitter, Peak period jitter  
tjpeak  
VT = OVDD/2 V  
±170  
±250  
ps  
Notes for single-ended clocks:  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Clock Frequency specifications are guaranteed assuming that REF is at 25MHz  
3 At default SMBus settings  
4 Measured betweeen 20% and 80% of OVDD  
5 This is the frequency error with respect to the crystal frequency.  
6 Measured at the rising and/or falling edge at OVDD/2 V.  
7 Phase noise is calculated as the FFT of the TIE jitter.  
8 Slew rate is measured from ±0.3 VAC at the center of peak to peak voltage at the clock input.  
Δ
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
8
REVISION R 11/23/16  
6V49205B DATASHEET  
General SMBus Serial Interface Information for 6V49205B  
How to Write  
How to Read  
• Controller (host) sends a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) will send a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the byte count = X  
• IDT clock will acknowledge  
• Controller (host) starts sending Byte N through Byte  
N+X-1  
• Controller (host) will send a separate start bit  
• Controller (host) sends the read address  
• IDT clock will acknowledge  
• IDT clock will send the data byte count = X  
• IDT clock sends Byte N+X-1  
• IDT clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• IDT clock sends Byte 0 through Byte X (if X was  
written to Byte 8)  
(H)  
• Controller (host) will need to acknowledge each byte  
• Controller (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Write Operation  
Controller (Host)  
starT bit  
Slave Address D2(H)  
WR WRite  
IDT (Slave/Receiver)  
Index Block Read Operation  
T
Controller (Host)  
IDT (Slave/Receiver)  
T
starT bit  
Slave Address D2(H)  
ACK  
ACK  
ACK  
ACK  
WR  
WRite  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
ACK  
ACK  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address D3(H)  
RD  
ReaD  
O
O
O
ACK  
O
O
O
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
P
stoP bit  
O
O
O
2
Note: I C compatible. Native mode is SMBus Block mode  
O
O
O
2
protocol. To use I C Byte mode set the 2^7 bit in the  
command Byte. No Byte count is used.  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
REVISION R 11/23/16  
9
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
6V49205B DATASHEET  
Byte 0 Frequency and Spread Select Register  
0
1
Bit  
7
6
5
4
3
2
1
Name  
SS4  
SS3  
SS2  
SS1  
SS0  
REF_5_EN  
REF_4_EN  
REF_3_EN  
Description  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Default  
0
0
0
0
0
1
1
1
Sys_CCB and DDRCLK Spread  
Selection Table  
See Table 2: Sys_CCB and DDRCLK  
Spread Table  
PCIE Spread Selection Table  
See Table 1: PCIE Spread Table  
Output enable for REF_5  
Output enable for REF_4  
Output enable for REF_5  
Output Disabled  
Output Disabled  
Output Disabled  
Output Enabled  
Output Enabled  
Output Enabled  
0
Byte 1 Output Enable Register  
0
1
Bit  
7
6
5
4
3
2
1
Name  
REF_2_EN  
REF_1_EN  
REF_0_EN  
USB_CLK1_EN  
USB_CLK2_EN  
CK2.048_0_EN  
CK2.048_1_EN  
DDRCLK_EN  
Description  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Default  
Output enable for REF_2  
Output enable for REF_1  
Output enable for REF_0  
Output enable for USB_CLK1  
Output enable for USB_CLK2  
Output enable for CK2.048_0  
Output enable for CK2.048_1  
Output enable for DDRCLK  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
1
1
1
1
1
1
1
1
0
Byte 2 Output Enable Register  
0
1
Bit  
7
6
5
4
3
2
1
Name  
Sys_CCB_EN  
PCIe5_EN  
PCIe4_EN  
PCIe3_EN  
PCIe2_EN  
PCIe1_EN  
PCIe0_EN  
125M_EN  
Description  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Default  
Output enable for Sys_CCB  
Output enable for PCIe5  
Output enable for PCIe4  
Output enable for PCIe3  
Output enable for PCIe2  
Output enable for PCIe1  
Output enable for PCIe0  
Output enable for 125M  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
1
1
1
1
1
1
1
1
0
Byte 3 Slew Rate Control Register  
0
1
Bit  
7
6
5
4
3
2
1
Name  
Description  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Default  
USB1_SLEW1  
USB1_SLEW0  
USB2_SLEW1  
USB2_SLEW0  
CK2.048_SLEW1  
CK2.048_SLEW0  
Sys_CCB_SLEW1  
Sys_CCB_SLEW0  
0
1
0
1
1
1
0
1
USB_CLK1 Slew Rate Control  
See USB Electrical Tables  
USB_CLK2 Slew Rate Control  
See USB Electrical Tables  
See CK2.048 Electrical Tables  
See Sys_CCB Electrical Tables  
CK2.048_0 and CK2.048_1 Slew Rate  
Control  
Sys_CCB Slew Rate Control  
0
Byte 4 Slew Rate Control Register  
0
1
Bit  
7
6
5
Name  
DDR_Slew1  
DDR_Slew0  
Description  
Type  
RW  
RW  
Default  
0
1
0
DDRCLK Slew Rate Control  
See DDR Electrical Tables  
Reserved  
Reserved  
4
1
3
2
1
FS1  
FS0  
USB1_fSel  
USB2_fSel  
RW  
RW  
RW  
RW  
See Table 3: Sys_CCB Frequency  
Selection  
Latch  
Latch  
0
Sys_CCB Frequency Select Latch  
USB_CLK1 Clock Frequency Select  
USB_CLK2 Clock Frequency Select  
12MHz  
12MHz  
24MHz  
24MHz  
0
1
Byte 5 is Reserved  
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
10  
REVISION R 11/23/16  
6V49205B DATASHEET  
Byte 6 PCI Express Amplitude Control Register  
0
1
Bit  
7
6
5
4
3
2
1
Name  
PCIE_AMP1  
PCIE_AMP0  
SEL100#_66  
SELPCIE125#_100  
Reserved  
Description  
Type  
RW  
RW  
R
Default  
See Table 4: PCIe Amplitude Selection  
Table  
0
PCI Express Amplitude Control  
1
latch  
latch  
0
1
0
DDRCLK latch select  
PCI Express latch select  
Reserved  
100MHz  
125MHz  
66MHz  
100MHz  
R
RW  
RW  
RW  
RW  
-
-
-
-
-
-
-
-
Reserved  
Reserved  
Reserved  
Reserved  
0
Reserved  
Reserved  
1
Byte 7 Revision and Vendor ID Register  
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
Bit  
7
6
5
4
3
2
1
Name  
REV ID  
REV ID  
REV ID  
Description  
Type  
R
R
R
R
R
R
R
Default  
0
0
0
1
0
0
0
1
Revision ID  
REV ID  
Vendor ID  
Vendor ID  
Vendor ID  
Vendor ID  
Vendor ID  
0
R
Byte 8 Byte Count Register  
0
1
Bit  
7
6
5
4
3
2
1
Name  
BC7  
BC6  
BC5  
BC4  
BC3  
BC2  
BC1  
BC0  
Description  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Default  
0
0
0
0
0
1
0
1
Writing to this register will configure how  
many bytes will be read back.  
Byte Count Programming b(7:0)  
0
Recommended Crystal Characteristics  
PARAMETER  
VALUE  
UNITS  
NOTES  
Frequency  
Resonance Mode  
25  
MHz  
-
1
1
1
Fundamental  
Frequency Tolerance @ 25°C  
Frequency Stability, ref @ 25°C Over  
Operating Temperature Range  
Temperature Range (commerical)  
Temperature Range (industrial)  
Equivalent Series Resistance (ESR)  
Shunt Capacitance (CO)  
20  
±
PPM Max  
20  
±
PPM Max  
1
C
°
C
°
0~70  
-40~85  
50  
1
1
1
1
Ω
Max  
7
pF Max  
pF Max  
mW Max  
PPM Max  
Load Capacitance (CL)  
Drive Level  
8
0.1  
±5  
1
1
1
Aging per year  
REVISION R 11/23/16  
11  
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
6V49205B DATASHEET  
Test Loads  
Device  
Low-Power push-pull HCSL Output test load  
(integrated terminations)  
CL=4.7pF  
except  
DDRCLK  
outputs  
where  
Zo  
L inches  
Rs=39  
Test Load  
CL=15pf  
Differential Zo  
2pF  
2pF  
Single-ended  
Output  
Differential Test Load, Zo = 100ohm, L = 5 inches  
Thermal Characteristics (48-TSSOP) PAG48  
TYP  
VALUE  
28  
PARAMETER  
SYMBOL  
CONDITIONS  
PKG  
UNITS NOTES  
C/W  
C/W  
Junction to Case  
Junction to Base  
°
1
1
1
1
1
θJC  
θJb  
θJA0  
θJA1  
θJA3  
42  
62  
54  
51  
°
C/W  
°
Thermal Resistance  
Junction to Air, still air  
Junction to Air, 1 m/s air flow  
Junction to Air, 3 m/s air flow  
PAG48  
C/W  
°
C/W  
°
Thermal Characteristics (48-VFQFPN) NLG48  
TYP  
VALUE  
PARAMETER  
SYMBOL  
CONDITIONS  
PKG  
UNITS NOTES  
C/W  
C/W  
Junction to Case  
Junction to Base  
25  
3.1  
32  
25  
22  
°
1
1
1
1
1
θJC  
θJb  
θJA0  
θJA1  
θJA3  
°
C/W  
°
Thermal Resistance  
Junction to Air, still air  
Junction to Air, 1 m/s air flow  
Junction to Air, 3 m/s air flow  
NLG48  
C/W  
°
°
C/W  
1ePad soldered to board  
Marking Diagrams  
25  
48  
IDT6V4  
9205BN  
LGI  
IDT  
6V49205BPAGI  
YYWW$  
YYWW$  
24  
1
48VFQFPN  
48TSSOP  
Notes:  
1. ‘$’ is the mark code.  
2. YYWW is the last two digits of the year, and the week number that the part was assembled.  
3. “G” after the two-letter package code denotes Pb free package.  
4. “I” denotes industrial temperature range.  
5. Bottom marking for TSSOP: country of origin if not USA.  
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
12  
REVISION R 11/23/16  
6V49205B DATASHEET  
Package Outline and Package Dimensions (NLG48, 48-pin 7mm x 7mm VFQFPN)  
Millimeters  
Symbol  
Min  
0.80  
0
Max  
0.90  
0.05  
A
A1  
A3  
0.20 Reference  
b
0.18  
0.30  
e
0.50 BASIC  
N
ND  
48  
12  
NE  
12  
D x E BASIC  
7.00 x 7.00  
5.50 BASIC  
5.50 BASIC  
5.80  
5.80  
0.75 BASIC  
0.75 BASIC  
0.45  
D1  
E1  
D2  
E2  
ZD  
ZE  
L
5.50  
5.50  
0.35  
REVISION R 11/23/16  
13  
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
6V49205B DATASHEET  
Package Outline and Package Dimensions (PAG48, 48-pin TSSOP, 6.10 mm Body, 0.50 Pitch)  
Package dimensions are kept current with JEDEC Publication No. 95  
48  
Millimeters  
Inches*  
Symbol  
Min  
--  
Max  
1.20  
0.15  
1.05  
0.27  
0.20  
12.60  
Min  
--  
Max  
A
A1  
A2  
b
0.047  
0.006  
0.041  
0.011  
0.05  
0.80  
0.17  
0.09  
12.40  
0.002  
0.032  
0.007  
E1  
E
INDEX  
AREA  
c
0.0035 0.008  
0.488 0.496  
0.319 BASIC  
D
1 2  
E
8.10 BASIC  
E1  
e
6.00  
6.20  
0.236  
0.244  
D
0.50 Basic  
0.020 Basic  
L
0.45  
0  
0.75  
8  
0.018  
0  
0.030  
8  
aaa  
--  
0.10  
--  
0.004  
A
A2  
*For reference only. Controlling dimensions in mm.  
A1  
c
- C -  
e
SEATING  
PLANE  
b
L
aaa C  
Ordering Information  
Part / Order Number  
Marking  
Shipping Packaging  
Tubes  
Package  
Temperature  
-40to +85C  
-40to +85C  
-40to +85C  
-40to +85C  
6V49205BPAGI  
6V49205BPAGI8  
6V49205BNLGI  
6V49205BNLGI8  
see page 12  
48-pin TSSOP  
48-pin TSSOP  
48-pin VFQFPN  
48-pin VFQFPN  
Tape and Reel  
Tray  
see page 12  
Tape and Reel  
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.  
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
14  
REVISION R 11/23/16  
6V49205B DATASHEET  
Revision History  
Rev.  
Issue Date  
Issuer  
Description  
Page #  
1. Updated pins 12, 20, 33 and 42 in pinouts and pin  
descriptions.  
L
9/12/2013 V. Chaudhry  
Various  
1. Extensive overhaul of Electrical tables to more closely align  
with Freescale published specifications.  
2. Updated electrical tables with characterization data.  
3. Clarified SMBus registers for Slew Rate Controls  
4. Moved electrical tables in front of SMBus for consistency  
M
12/9/2013  
R. Wade with other data sheets.  
Various  
5. Updated Thermal Data and added test loads for clarity.  
6. Updated front page text  
7. Minor updates to pin names (mainly power and ground) for  
consistency and clarity  
8. Move to Final  
6/2/2014  
3
5
N
P
R. Wade 1. Corrected pin description for pin 44.  
1. Updated SMBus operating frequency from 100KHz minimum  
8/10/2015  
R. Wade  
to 400KHz maximum.  
1. Correct PCIeT_LRn and PCIeC_LRn to be PCIeT_Ln and  
PCIeC_Ln to indicate that the Rs for the PCIe outputs is outside  
5/11/2016  
1-3  
Q
R
RDW  
RDW  
the part and to correct the pin description accordingly. The test  
loads for the device are correct.  
2. Update block diagram PCIe pin names to be consistent.  
1. Undo Revision Q  
2. PCIe outputs have integrated terminations for 100ohm  
differential Zo.  
11/22/2016  
1-3, 12  
3. Update Test Loads  
4. Update Features/Benefits  
REVISION R 11/23/16  
15  
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
www.idt.com/go/sales  
Tech Support  
www.idt.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether  
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This  
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected  
names, logos and designs, are the property of IDT or their respective third party owners.  
Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved.  
厂商 型号 描述 页数 下载

IDT

 		6V49205APAG [ FREESCALE P10XX AND P20XX SYSTEM CLOCK ] 15 页

IDT

 		6V49205APAG8 [ FREESCALE P10XX AND P20XX SYSTEM CLOCK ] 15 页

IDT

 		6V49205APAGI [ FREESCALE P10XX AND P20XX SYSTEM CLOCK ] 15 页

IDT

 		6V49205APAGI8 [ FREESCALE P10XX AND P20XX SYSTEM CLOCK ] 15 页

IDT

 		6V49205B [ Freescale System Clock w/Selectable DDR Frequency ] 16 页

IDT

 		6V49205BNLGI8 [ Freescale System Clock w/Selectable DDR Frequency ] 16 页

IDT

 		6V49205BPAGI [ Freescale System Clock w/Selectable DDR Frequency ] 16 页

IDT

 		6V49205BPAGI8 [ Freescale System Clock w/Selectable DDR Frequency ] 16 页

IDT

 		6V49205B_16 [ Freescale System Clock w/Selectable DDR Frequency ] 16 页

IDT

 		6V49205B_17 [ Freescale P10XX and P20XX System Clock ] 18 页

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