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NVTFS4C05NWFTAG

型号：

NVTFS4C05NWFTAG

品牌：

ONSEMI[ ONSEMI ]

页数：

6 页

PDF大小：

85 K

下载PDF手册
NVTFS4C05N  
Power MOSFET  
30 V, 3.6 mW, 102 A, Single N−Channel,  
m8FL  
Features  
• Low R  
to Minimize Conduction Losses  
DS(on)  
• Low Capacitance to Minimize Driver Losses  
• Optimized Gate Charge to Minimize Switching Losses  
• NVTFS4C05NWF − Wettable Flanks Product  
• NVT Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q101  
Qualified and PPAP Capable  
http://onsemi.com  
V
R
MAX  
I MAX  
D
(BR)DSS  
DS(on)  
3.6 mW @ 10 V  
5.1 mW @ 4.5 V  
30 V  
102 A  
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
N−Channel MOSFET  
MAXIMUM RATINGS (T = 25°C unless otherwise stated)  
J
D (5−8)  
Parameter  
Drain−to−Source Voltage  
Symbol Value Unit  
V
30  
20  
22  
V
V
A
DSS  
Gate−to−Source Voltage  
V
GS  
G (4)  
Continuous Drain  
Current R  
I
D
T = 25°C  
A
q
JA  
T = 100°C  
A
15.7  
(Notes 1, 2, 4)  
S (1,2,3)  
Power Dissipation R  
(Notes 1, 2, 4)  
P
W
A
T = 25°C  
3.2  
1.6  
q
D
D
JA  
A
T = 100°C  
A
Steady  
State  
MARKING DIAGRAM  
Continuous Drain  
Current R  
I
D
T
C
= 25°C  
102  
1
1
y
JC  
S
S
S
G
D
D
D
D
T
C
= 100°C  
72  
(Notes 1, 3, 4)  
XXXX  
AYWWG  
G
WDFN8  
(m8FL)  
CASE 511AB  
Power Dissipation  
P
W
T
= 25°C  
68  
34  
C
R
(Notes 1, 3, 4)  
y
JC  
T
C
= 100°C  
Pulsed Drain Current  
T = 25°C, t = 10 ms  
I
DM  
433  
A
A
p
4C05  
= Specific Device Code for  
NVMTS4C05N  
Operating Junction and Storage Temperature  
T ,  
−55 to  
+175  
°C  
J
stg  
T
05WF = Specific Device Code of  
NVTFS4C05NWF  
A
Source Current (Body Diode)  
I
S
65  
88  
A
= Assembly Location  
= Year  
= Work Week  
Single Pulse Drain−to−Source Avalanche Energy  
E
AS  
mJ  
Y
(T = 25°C, V = 10 V, I = 18.8 A, L = 0.5 mH)  
J
GS  
L
WW  
G
Lead Temperature for Soldering Purposes  
(1/8″ from case for 10 s)  
T
L
260  
°C  
= Pb−Free Package  
(Note: Microdot may be in either location)  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information on  
THERMAL RESISTANCE MAXIMUM RATINGS  
page 5 of this data sheet.  
Parameter  
Symbol  
Value  
2.2  
Unit  
Junction−to−Case (Drain) (Notes 1, 3)  
R
°C/W  
y
JC  
Junction−to−Ambient – Steady State  
(Notes 1, 2)  
R
47  
q
JA  
1. The entire application environment impacts the thermal resistance values  
shown; they are not constants and are valid for the specific conditions noted.  
2
2. Surface−mounted on FR4 board using 650 mm , 2 oz. Cu Pad.  
3. Assumes heat−sink sufficiently large to maintain constant case temperature  
independent of device power.  
4. Continuous DC current rating. Maximum current for pulses as long as one  
second is higher but dependent on pulse duration and duty cycle.  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
July, 2014 − Rev. 2  
NVTFS4C05N/D  
 
NVTFS4C05N  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)  
J
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Drain−to−Source Breakdown Voltage  
V
V
GS  
= 0 V, I = 250 mA  
30  
V
(BR)DSS  
D
Drain−to−Source Breakdown Voltage  
Temperature Coefficient  
V
/
11.7  
(BR)DSS  
mV/°C  
T
J
Zero Gate Voltage Drain Current  
I
V
V
= 0 V,  
= 24 V  
T = 25°C  
1.0  
10  
DSS  
GS  
DS  
J
mA  
T = 125°C  
J
Gate−to−Source Leakage Current  
ON CHARACTERISTICS (Note 5)  
Gate Threshold Voltage  
I
V
= 0 V, V  
=
GS  
20 V  
100  
nA  
GSS  
DS  
V
V
= V , I = 250 mA  
1.3  
2.2  
V
GS(TH)  
GS  
DS  
D
Threshold Temperature Coefficient  
Drain−to−Source On Resistance  
V
/T  
−5.0  
2.9  
4.1  
68  
mV/°C  
GS(TH)  
J
R
V
= 10 V  
I
I
= 30 A  
= 30 A  
3.6  
5.1  
DS(on)  
GS  
D
mW  
V
GS  
= 4.5 V  
D
Forward Transconductance  
Gate Resistance  
g
FS  
V
= 1.5 V, I = 15 A  
S
DS  
D
R
T = 25°C  
A
1.0  
W
G
CHARGES AND CAPACITANCES  
Input Capacitance  
C
1988  
1224  
71  
ISS  
Output Capacitance  
C
V
= 0 V, f = 1 MHz, V = 15 V  
pF  
nC  
OSS  
RSS  
GS  
DS  
Reverse Transfer Capacitance  
Capacitance Ratio  
C
C
/C  
V
GS  
= 0 V, V = 15 V, f = 1 MHz  
0.036  
14.5  
2.9  
RSS ISS  
DS  
Total Gate Charge  
Q
G(TOT)  
Threshold Gate Charge  
Gate−to−Source Charge  
Gate−to−Drain Charge  
Gate Plateau Voltage  
Total Gate Charge  
Q
G(TH)  
Q
V
GS  
= 4.5 V, V = 15 V; I = 30 A  
5.2  
GS  
GD  
GP  
DS  
D
Q
V
5.5  
V
3.1  
Q
V
GS  
= 10 V, V = 15 V; I = 30 A  
31  
nC  
G(TOT)  
DS  
D
SWITCHING CHARACTERISTICS (Note 6)  
Turn−On Delay Time  
Rise Time  
t
11  
30  
d(ON)  
t
r
V
= 4.5 V, V = 15 V,  
DS  
GS  
ns  
ns  
V
I
D
= 15 A, R = 3.0 W  
G
Turn−Off Delay Time  
Fall Time  
t
20  
d(OFF)  
t
f
8.0  
8.0  
25  
Turn−On Delay Time  
Rise Time  
t
d(ON)  
t
r
V
= 10 V, V = 15 V,  
DS  
GS  
I
D
= 15 A, R = 3.0 W  
G
Turn−Off Delay Time  
Fall Time  
t
26  
d(OFF)  
t
f
5.0  
DRAIN−SOURCE DIODE CHARACTERISTICS  
Forward Diode Voltage  
V
SD  
T = 25°C  
J
0.77  
0.62  
42.4  
21.1  
21.3  
34.4  
1.1  
V
GS  
= 0 V,  
I
S
= 10 A  
T = 125°C  
J
Reverse Recovery Time  
Charge Time  
t
RR  
t
t
ns  
a
V
= 0 V, dIS/dt = 100 A/ms,  
GS  
I
S
= 30 A  
Discharge Time  
b
nC  
Reverse Recovery Charge  
Q
RR  
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.  
6. Switching characteristics are independent of operating junction temperatures.  
http://onsemi.com  
2
 
NVTFS4C05N  
TYPICAL CHARACTERISTICS  
140  
130  
120  
110  
100  
90  
140  
10 V  
T = 25°C  
J
V
DS  
= 5 V  
130  
120  
110  
100  
90  
3.8 V  
3.6 V  
4 V to 6.5 V  
3.4 V  
3.2 V  
80  
70  
80  
70  
60  
60  
50  
40  
50  
40  
3.0 V  
T = 125°C  
J
30  
20  
10  
0
30  
20  
10  
0
T = 25°C  
2.8 V  
2.6 V  
J
T = −55°C  
J
0
1
2
3
4
5
0
0.5 1.0 1.5  
2.0 2.5 3.0 3.5 4.0 4.5  
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
V
GS  
, GATE−TO−SOURCE VOLTAGE (V)  
Figure 1. On−Region Characteristics  
Figure 2. Transfer Characteristics  
0.028  
0.026  
0.024  
0.022  
0.020  
0.018  
0.016  
0.014  
0.012  
0.010  
0.008  
0.006  
0.004  
0.002  
0.008  
0.007  
I
= 30 A  
T = 25°C  
D
J
T = 25°C  
J
0.006  
0.005  
V
= 4.5 V  
= 10 V  
GS  
0.004  
0.003  
0.002  
V
GS  
3.0  
4.0  
5.0  
6.0  
7.0  
8.0  
9.0  
10  
10  
20  
30  
40  
50  
60  
70  
V
GS  
, GATE−TO−SOURCE VOLTAGE (V)  
I , DRAIN CURRENT (A)  
D
Figure 3. On−Resistance vs. VGS  
Figure 4. On−Resistance vs. Drain Current and  
Gate Voltage  
10000  
1000  
1.9  
1.8  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
V
GS  
= 0 V  
I
V
= 30 A  
= 10 V  
D
T = 150°C  
J
GS  
T = 125°C  
J
100  
10  
T = 85°C  
J
0.8  
0.7  
−50 −25  
0
25  
50  
75  
100 125 150 175  
5
10  
, DRAIN−TO−SOURCE VOLTAGE (V)  
DS  
15  
20  
25  
30  
T , JUNCTION TEMPERATURE (°C)  
J
V
Figure 5. On−Resistance Variation with  
Temperature  
Figure 6. Drain−to−Source Leakage Current  
vs. Voltage  
http://onsemi.com  
3
NVTFS4C05N  
TYPICAL CHARACTERISTICS  
3000  
2750  
2500  
10  
Q
V
= 0 V  
T
GS  
T = 25°C  
J
8
6
4
2
0
2250  
2000  
1750  
1500  
1250  
1000  
750  
C
iss  
C
oss  
Q
Q
gd  
gs  
T = 25°C  
J
V
V
= 15 V  
= 10 V  
DD  
GS  
500  
250  
0
C
rss  
I
D
= 30 A  
0
5
10  
15  
20  
25  
30  
0
4
8
12  
16  
20  
24  
28  
32  
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
Q , TOTAL GATE CHARGE (nC)  
g
Figure 7. Capacitance Variation  
Figure 8. Gate−to−Source and  
Drain−to−Source Voltage vs. Total Charge  
20  
18  
16  
14  
12  
10  
8
1000  
100  
V
GS  
= 0 V  
V
= 15 V  
= 15 A  
= 10 V  
DD  
I
D
t
V
GS  
d(off)  
t
d(on)  
t
r
t
f
10  
1
6
T = 125°C  
J
4
T = 25°C  
J
2
0
0.4  
1
10  
R , GATE RESISTANCE (W)  
100  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
V
SD  
, SOURCE−TO−DRAIN VOLTAGE (V)  
G
Figure 9. Resistive Switching Time Variation  
vs. Gate Resistance  
Figure 10. Diode Forward Voltage vs. Current  
1000  
100  
0.01 ms  
10  
0.1 ms  
1 ms  
V
T
= 10 V  
= 25°C  
GS  
C
1
R
Limit  
DS(on)  
Thermal Limit  
Package Limit  
10 ms  
dc  
0.1  
0.1  
1
10  
100  
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
Figure 11. Maximum Rated Forward Biased  
Safe Operating Area  
http://onsemi.com  
4
NVTFS4C05N  
TYPICAL CHARACTERISTICS  
100  
10  
Duty Cycle = 50%  
20%  
10%  
5%  
2%  
1%  
1
R
Single Pulse  
y
JC  
R
Single Pulse  
q
JA  
0.1  
y
, Infinite Heat Sink Assumption  
, 650 mm , 2 oz Cu Pad, Single  
JC  
2
q
JA  
Layer on FR4  
0.01  
0.000001 0.00001  
0.0001  
0.001  
0.01  
t, PULSE TIME (s)  
0.1  
1
10  
100  
1000  
Figure 12. Thermal Response  
120  
100  
80  
60  
40  
20  
0
1000  
100  
10  
1
T
= 25°C  
J(initial)  
T
= 85°C  
J(initial)  
0
10  
20  
30  
40  
(A)  
50  
60  
70  
80  
0.000001  
0.00001  
T , TIME IN AVALANCHE (s)  
AV  
0.0001  
0.001  
I
D
Figure 13. GFS vs. ID  
Figure 14. Avalanche Characteristics  
ORDERING INFORMATION  
Device  
†
Package  
Shipping  
NVTFS4C05NTAG  
WDFN8  
(Pb−Free)  
1500 / Tape & Reel  
1500 / Tape & Reel  
NVTFS4C05NWFTAG  
WDFN8  
(Pb−Free)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
http://onsemi.com  
5
NVTFS4C05N  
PACKAGE DIMENSIONS  
WDFN8 3.3x3.3, 0.65P  
CASE 511AB  
ISSUE D  
2X  
NOTES:  
0.20  
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH  
PROTRUSIONS OR GATE BURRS.  
D
A
B
E
2X  
D1  
MILLIMETERS  
INCHES  
NOM  
0.030  
−−−  
0.012  
0.20  
C
8
1
7
6
5
4
DIM  
A
A1  
b
MIN  
0.70  
0.00  
0.23  
0.15  
NOM  
0.75  
−−−  
0.30  
0.20  
MAX  
MIN  
MAX  
0.031  
0.002  
0.016  
0.010  
0.028  
0.000  
0.009  
0.006  
0.80  
0.05  
0.40  
0.25  
4X  
q
E1  
c
0.008  
D
3.30 BSC  
3.05  
2.11  
3.30 BSC  
3.05  
1.60  
0.30  
0.65 BSC  
0.41  
0.80  
0.43  
0.130 BSC  
0.120  
0.083  
0.130 BSC  
0.120  
0.063  
0.012  
0.026 BSC  
0.016  
0.032  
0.017  
D1  
D2  
E
E1  
E2  
E3  
e
G
K
L
L1  
M
2.95  
1.98  
3.15  
2.24  
0.116  
0.078  
0.124  
0.088  
c
2
3
A1  
TOP VIEW  
2.95  
1.47  
0.23  
3.15  
1.73  
0.40  
0.116  
0.058  
0.009  
0.124  
0.068  
0.016  
0.10  
0.10  
C
C
A
C
6X  
e
0.30  
0.65  
0.30  
0.06  
1.40  
0
0.51  
0.95  
0.56  
0.20  
1.60  
0.012  
0.026  
0.012  
0.002  
0.055  
0
0.020  
0.037  
0.022  
0.008  
0.063  
SEATING  
PLANE  
0.13  
1.50  
−−−  
0.005  
0.059  
−−−  
DETAIL A  
SIDE VIEW  
DETAIL A  
q
12  
12  
_
_
_
_
8X  
b
0.10  
0.05  
C
C
A B  
SOLDERING FOOTPRINT*  
8X  
e/2  
0.42  
0.65  
PITCH  
4X  
L
4X  
0.66  
1
8
4
5
PACKAGE  
OUTLINE  
K
E2  
M
E3  
3.60  
L1  
D2  
BOTTOM VIEW  
G
2.30  
0.57  
0.47  
0.75  
2.37  
3.46  
DIMENSION: MILLIMETERS  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,  
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC  
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any  
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without  
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications  
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC  
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for  
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where  
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and  
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,  
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture  
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81−3−5817−1050  
ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada  
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
NVTFS4C05N/D  
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