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CUI Inc │ SERIES: PYB20-DIN │ DESCRIPTION: DC-DC CONVERTER
date 06/16/2015 │ page 6 of 7
APPLICATION NOTES
1. Recommended circuit
This series has been tested according to the following recommended testing circuit before leaving the factory. This series should be
tested under load (see Figure 2). If you want to further decrease the input/output ripple, you can increase the capacitance accord-
ingly or choose capacitors with low ESR (see Table 2). However, the capacitance of the output filter capacitor must be appropriate. If
the capacitance is too high, a startup problem might arise. For every channel of the output, to ensure safe and reliable operation, the
maximum capacitance must be less than the maximum capacitive load (see Table 3).
Figure 2
Single Output
Dual Output
Vin
+Vo
0V
Vin
+Vo
0V
Cout
Cout
Cin
Cin
Cout
DC DC
DC DC
GND
GND
-Vo
Table 2
Cout Dual Vout
Table 3
Max. Capacitive Load1
Single Vout
Cin
(µF)
Cin
(µF)
Cout1
(µF)
Single Vout Max. Capacitive Load Dual Vout
(μF)
(Vdc)
3.3
5
(µF)
470
470
220
220
100
(Vdc)
(Vdc)
3.3
5
(μF)
10200
4020
1035
705
(Vdc)
100
100
100
100
100
--
--
--
--
--
4800
800
500
--
±5
100
100
100
--
220
100
100
--
5
12
±12
±15
--
12
12
15
--
15
15
24
24
470
Note:
1. For each output.
Note:
1. For each output.
2. Output voltage trimming
Leave open if not used.
Figure 3
Application Circuit for Trim pin
(part in broken line is the interior of models)
Formula for Trim Resistor
+Vo
+Vo
2
Vref
Vo’ - Vref
aR
-R
-R
3
3
up
down
:
:
R
R
T
=
a=
a=
R
R
1
2
R
2-a
aR
1
Vo’ - Vref
Vref
R
1
T
=
R
1-a
R
T
R
1
R
3
V
re f
Trim
R
3
V
ref
Trim
R
2
R
T
Note: Value for R1, R2, R3, and Vref refer to Table 4
RT: Trim Resistor
R
2
a: User-defined parameter, no actual meanings
Vo': The trim up/down voltage
0V
Trim down
0V
Trim up
Vout
(Vdc)
R1
(kΩ)
R2
(kΩ)
R3
(kΩ)
Vref
(V)
3.3
5
4.801 2.863
2.883 2.864
15
10
1.24
2.5
2.5
2.5
2.5
Table 4
12
15
24
10.971 2.864 17.8
14.497 2.864 17.8
24.872 2.863
20
Note:
1. Minimum load shouldn't be less than 5%, otherwise ripple may increase dramatically. Operation under minimum load will not damage the converter, however, they may
not meet all specifications listed.
2. Maximum capacitive load is tested at input voltage range and full load.
3. All specifications are measured at Ta=25°C, humidity<75%, nominal input voltage and rated output load unless otherwise specified.
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