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5P90005CDCGH8

型号：

5P90005CDCGH8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

15 页

PDF大小：

146 K

下载PDF手册
Serial Real-Time Clock  
IDT5P90005C  
DATASHEET  
Description  
Features  
The IDT5P90005C is a serial real-time clock (RTC) device  
that consumes ultra-low power and provides a full  
binary-coded decimal (BCD) clock/calendar. The  
• Packaged in 8-pin SOIC, RoHS compliant  
• Counters for seconds, minutes, hours, days, date, months,  
years, and century  
clock/calendar provides seconds, minutes, hours, day, date,  
month, and year information. The clock operates in either the  
24-hour or 12-hour format with AM/PM indicator. The end of  
the month date is automatically adjusted for months with  
fewer than 31 days, including corrections for leap year.  
• 32kHz crystal oscillator integrating load capacitance  
(12.5 pF) providing exceptional oscillator stability and high  
crystal series resistance operation  
2
• Serial interface supports I C bus (100 or 400kHz protocol)  
2
Access to the clock/calendar registers is provided by an I C  
• Ultra low battery supply current of 0.8µA (typical at 3V)  
• 2.0 to 5.5V clock operating voltage  
2
interface capable of operating in fast I C mode. Built-in  
Power-sense circuitry detects power failures and  
automatically switches to the backup supply, maintaining time  
and date operation.  
• Automatic switch over and deselect circuitry  
• Automatic leap year compensation  
• Extended commercial operating temperature (0 to +85°C)  
Block Diagram  
1 Hz  
32.768 kHz  
Oscillator and  
Divider  
OSCI  
MUX/  
FT/OUT  
Buffer  
OSCO  
VCC  
GND  
VBAT  
Power  
Control  
Control  
Logic  
Clock, Calendar  
Counter  
SCL  
SDA  
I2C  
Interface  
1 Byte 7 Bytes  
Control  
Buffer  
IDT5P90005C REVISION C 07/03/14  
1
©2014 Integrated Device Technology, Inc.  
IDT5P90005C DATASHEET  
Pin Assignment  
8
7
6
5
1
2
3
4
VCC  
OSCI  
OSCO  
VBAT  
FT/OUT  
SCL  
VSS  
SDA  
8-Pin (150 mil) SOIC  
Pin Descriptions  
Pin  
Number  
Pin  
Name  
Pin Type  
Pin Description  
1
2
3
4
5
6
7
8
OSCI  
OSCO  
VBAT  
Input  
Output  
Power  
Power  
I/O  
Oscillator input.  
Oscillator output.  
Battery supply voltage.  
Connect to ground.  
Serial data address input/output.  
Serial clock.  
VSS  
SDA  
SCL  
Input  
FT/OUT  
VCC  
Output  
Power  
Frequency test/output driver (open drain).  
Supply voltage.  
SERIAL REAL-TIME CLOCK  
2
REVISION C 07/03/14  
IDT5P90005C DATASHEET  
Device Operation  
The IDT5P90005C clock operates as a slave device on the  
serial bus. Access is obtained by implementing a start  
condition followed by the correct slave address (D0h). The 8  
bytes contained in the device can then be accessed  
sequentially in the following order:  
1st byte: seconds register  
2nd byte: minutes register  
3rd byte: century/hours register  
4th byte: day register  
5th byte: date register  
6th byte: month register  
7th byte: years register  
8th byte: control register  
The IDT5P90005C clock continually monitors VCC for an  
out-of-tolerance condition. Should VCC fall below VSO, the  
device terminates an access in progress and resets the device  
address counter. Inputs to the device will not be recognized at  
this time, to prevent erroneous data from being written to the  
device from an out-of-tolerance system. When VCC falls  
below VSO, the device automatically switches over to the  
battery and powers down into an ultra low current mode of  
operation to conserve battery life. Upon power-up, the device  
switches from battery to VCC at VSO and recognizes inputs.  
REVISION C 07/03/14  
3
SERIAL REAL-TIME CLOCK  
IDT5P90005C DATASHEET  
2
I C Serial Data Bus  
2
The IDT5P90005C supports the I C bus protocol. A device  
that sends data onto the bus is defined as a transmitter and a  
device receiving data as a receiver. The device that controls  
the message is called a master. The devices that are  
Acknowledge: Each receiving device, when addressed, is  
obliged to generate an acknowledge after the reception of  
each byte. The master device must generate an extra clock  
pulse that is associated with this acknowledge bit.  
controlled by the master are referred to as slaves. The bus  
must be controlled by a master device that generates the  
serial clock (SCL), controls the bus access, and generates the  
START and STOP conditions. The IDT5P90005C operates as  
A device that acknowledges must pull down the SDA line  
during the acknowledge clock pulse in such a way that the  
SDA line is stable LOW during the HIGH period of the  
acknowledge related clock pulse. Of course, setup and hold  
times must be taken into account. A master must signal an  
end of data to the slave by not generating an acknowledge bit  
on the last byte that has been clocked out of the slave. In this  
case, the slave must leave the data line HIGH to enable the  
master to generate the STOP condition.  
2
a slave on the I C bus. Within the bus specifications, a  
standard mode (100 kHz maximum clock rate) and a fast  
mode (400 kHz maximum clock rate) are defined. The  
IDT5P90005C works in both modes. Connections to the bus  
are made via the open-drain I/O lines SDA and SCL.  
The following bus protocol has been defined (see the “Data  
2
Transfer on I C Serial Bus” figure):  
• Data transfer may be initiated only when the bus is not  
busy.  
• During data transfer, the data line must remain stable  
whenever the clock line is HIGH. Changes in the data line  
while the clock line is HIGH are interpreted as control  
signals.  
Accordingly, the following bus conditions have been defined:  
Bus not busy: Both data and clock lines remain HIGH.  
Start data transfer: A change in the state of the data line,  
from HIGH to LOW, while the clock is HIGH, defines a START  
condition.  
Stop data transfer: A change in the state of the data line,  
from LOW to HIGH, while the clock line is HIGH, defines the  
STOP condition.  
Data valid: The state of the data line represents valid data  
when, after a START condition, the data line is stable for the  
duration of the HIGH period of the clock signal. The data on  
the line must be changed during the LOW period of the clock  
signal. There is one clock pulse per bit of data.  
Each data transfer is initiated with a START condition and  
terminated with a STOP condition. The number of data bytes  
transferred between START and STOP conditions is not  
limited, and is determined by the master device. The  
information is transferred byte-wise and each receiver  
acknowledges with a ninth bit.  
SERIAL REAL-TIME CLOCK  
4
REVISION C 07/03/14  
IDT5P90005C DATASHEET  
2
Data Transfer on I C Serial Bus  
Depending upon the state of the R/W bit, two types of data  
transfer are possible:  
the direction bit (R/W), which is 0 for a write. After receiving  
and decoding the slave address byte the slave outputs an  
acknowledge on the SDA line. After the IDT5P90005C  
acknowledges the slave address + write bit, the master  
transmits a register address to the IDT5P90005C. This sets  
the register pointer on the IDT5P90005C, with the  
IDT5P90005C acknowledging the transfer. The master may  
then transmit zero or more bytes of data, with the  
IDT5P90005C acknowledging each byte received. The  
address pointer increments after each data byte is transferred.  
The master generates a STOP condition to terminate the data  
write.  
1) Data transfer from a master transmitter to a slave  
receiver. The first byte transmitted by the master is the slave  
address. Next follows a number of data bytes. The slave  
returns an acknowledge bit after each received byte. Data is  
transferred with the most significant bit (MSB) first.  
2) Data transfer from a slave transmitter to a master  
receiver. The first byte (the slave address) is transmitted by  
the master. The slave then returns an acknowledge bit. This is  
followed by the slave transmitting a number of data bytes. The  
master returns an acknowledge bit after all received bytes  
other than the last byte. At the end of the last received byte, a  
“not acknowledge” is returned. The master device generates  
all of the serial clock pulses and the START and STOP  
conditions. A transfer is ended with a STOP condition or with  
a repeated START condition. Since a repeated START  
condition is also the beginning of the next serial transfer, the  
bus is not released. Data is transferred with the most  
significant bit (MSB) first.  
2) Slave Transmitter Mode (Read Mode): The first byte is  
received and handled as in the slave receiver mode. However,  
in this mode, the direction bit indicates that the transfer  
direction is reversed. Serial data is transmitted on SDA by the  
IDT5P90005C while the serial clock is input on SCL. START  
and STOP conditions are recognized as the beginning and  
end of a serial transfer (see the “Data Read–Slave Transmitter  
Mode” figure). The slave address byte is the first byte received  
after the START condition is generated by the master. The  
slave address byte contains the 7-bit IDT5P90005C address,  
which is 1101000, followed by the direction bit (R/W), which is  
1 for a read. After receiving and decoding the slave address  
byte the slave outputs an acknowledge on the SDA line. The  
IDT5P90005C then begins to transmit data starting with the  
register address pointed to by the register pointer. If the  
register pointer is not written to before the initiation of a read  
mode the first address that is read is the last one stored in the  
register pointer. The address pointer is incremented after each  
byte is transferred. The IDT5P90005C must receive a “not  
acknowledge” to end a read.  
The IDT5P90005C can operate in the following two modes:  
1) Slave Receiver Mode (Write Mode): Serial data and clock  
are received through SDA and SCL. After each byte is  
received an acknowledge bit is transmitted. START and STOP  
conditions are recognized as the beginning and end of a serial  
transfer. Address recognition is performed by hardware after  
reception of the slave address and direction bit (see the “Data  
Write–Slave Receiver Mode” figure). The slave address byte  
is the first byte received after the START condition is  
generated by the master. The slave address byte contains the  
7-bit IDT5P90005C address, which is 1101000, followed by  
REVISION C 07/03/14  
5
SERIAL REAL-TIME CLOCK  
IDT5P90005C DATASHEET  
Data Write – Slave Receiver Mode  
Data Read (from current Pointer location) – Slave Transmitter Mode  
Data Read (Write Pointer, then Read) – Slave Receive and Transmit  
Bus Timing Requirements Sequence  
Note: P=STOP and S=START.  
SERIAL REAL-TIME CLOCK  
6
REVISION C 07/03/14  
IDT5P90005C DATASHEET  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the IDT5P90005C. These ratings, which are standard  
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other  
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the  
recommended operating temperature range.  
Parameter  
Condition  
Min.  
-0.3  
-0.3  
-0.5  
-55  
Typ.  
Max.  
7
Units  
V
Supply Voltage, VCC  
Referenced to GND  
Referenced to GND  
Referenced to GND  
Input or Output Voltages  
Clock Outputs  
7
V
VDD+ 0.5  
125  
V
Storage Temperature  
Soldering Temperature1  
°C  
°C  
mA  
°C  
W
Max 10 seconds  
260  
Output Current  
20  
Ambient Operating Temperature (extended commercial range)  
Power Dissipation  
0
+85  
0.25  
Note 1: Re flow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30 seconds).  
Caution: Negative undershoots below -0.3V are not allowed on any pin while in the backup mode.  
REVISION C 07/03/14  
7
SERIAL REAL-TIME CLOCK  
IDT5P90005C DATASHEET  
DC and AC Parameters  
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device.  
The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement  
conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the  
measurement conditions when using the quoted parameters.  
1
Operating and AC Measurement Conditions  
Parameter  
Rating  
2.0 to 5.5V  
Supply Voltage, VCC  
Ambient Operating Temperature (extended commercial range)  
Load Capacitance  
0 to +85ºC  
100pF  
Input Rise and Fall times  
< 5ns  
Input Pulse Voltages  
0.2 VCC to 0.8 VCC  
0.3 VCC to 0.7 VCC  
Input and Output Timing Reference Voltages  
Note 1: Output Hi-Z is defined as the point where data is no longer driven.  
AC Testing Input/Output Waveform  
Capacitance  
1,2  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
7
Units  
pF  
Input Capacitance  
CIN  
3
Output Capacitance (SDA, FT/OUT)  
COUT  
10  
pF  
Low-pass Filter Input Time Constant (SDA and SCL)  
tLP  
250  
1000  
ns  
Note 1: Effective capacitance measured with power supply at 3.3V; sampled only, not 100% tested.  
Note 2: At 25°C, f = 1 MHz.  
Note 3: Output deselected.  
SERIAL REAL-TIME CLOCK  
8
REVISION C 07/03/14  
IDT5P90005C DATASHEET  
DC Characteristics  
1
Parameter  
Input Leakage Current  
Output Leakage Current  
Supply Current  
Symbol  
ILI  
Conditions  
0V = VIN = VCC  
0V = VOUT = VCC  
Min.  
Typ.  
Max.  
±1  
Units  
µA  
ILO  
±1  
µA  
ICC1  
ICC2  
VIL  
Switch Frequency = 100 kHz  
SCL, SDA = VCC - 0.3  
300  
70  
µA  
RTC Supply Current (standby)  
Input Low Voltage  
µA  
-0.3  
0.3VCC  
VCC+0.5  
0.4  
V
V
V
V
V
Input High Voltage  
VIH  
0.7VCC  
Output Low Voltage  
VOL  
IOL = 3.0 mA  
FT/OUT  
Output Low Voltage (open drain)  
Battery Supply Voltage  
5.5  
VBAT  
IBAT  
2.5  
3.5  
TA = 25°C, VCC = 0V  
Battery Supply Current  
0.8  
1
µA  
Oscillator ON, VBAT = 3V  
Note 1: Valid for ambient operating temperature: TA = 0 to +85°C; VCC = 2.0 to 5.5V (except where noted).  
Crystal Electrical Characteristics  
1
Parameter  
Symbol  
Min.  
Typ.  
Max.  
Units  
kHz  
K  
Resonant Frequency  
Series Resistance  
Load Capacitance  
fO  
RS  
CL  
32.768  
60  
12.5  
pF  
Note 1: Load capacitors are integrated within the IDT5P90005C. Circuit board layout considerations for the 32.768kHz crystal  
of minimum trace lengths and isolation from RF generating signals should be taken into account.  
REVISION C 07/03/14  
9
SERIAL REAL-TIME CLOCK  
IDT5P90005C DATASHEET  
AC Electrical Characteristics  
Unless stated otherwise, VCC = 2.0 to 5.5V, Ambient Temperature 0 to +85C (extended commercial range)  
Parameter  
Symbol  
STANDARD MODE  
FAST MODE  
Min. Max.  
Units  
Min.  
Max.  
SCL Clock Frequency  
fSCL  
tLOW  
tHIGH  
tR  
100  
400  
kHz  
µs  
Clock Low Period  
4.7  
4.0  
1.3  
0.6  
Clock High Period  
µs  
SDA and SCL Rise time  
SDA and SCL Fall Time  
1
0.3  
µs  
tF  
300  
300  
ns  
START Condition Hold Time (after this period the  
first clock pulse is generated)  
tHD:STA  
4
µs  
µs  
START Condition Setup Time (only relevant for a  
repeated start condition)  
t
SU:STA  
4.7  
0.6  
Data Hold Time  
t
HD:DAT1  
0
1.3  
100  
0.6  
ns  
ns  
µs  
Data Setup Time  
tSU:DAT  
tSU:STO  
250  
4.0  
STOP Condition Setup Time  
Time the bus must be free before a new  
transmission can start  
tBUF  
4.7  
1.3  
µs  
Note 1: Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.  
Power Down/Up Mode AC Waveforms  
RTC Power Down/Up AC Characteristics  
1,2  
Parameter  
SCL and SDA at VIH before Power Down  
SCL and SDA at VIH after Power Up  
Symbol  
tPD  
Min.  
0
Typ.  
Max.  
Units  
ns  
trec  
10  
2000  
µs  
Note 1: Valid for ambient operating temperature: TA = 0 to +85°C; VCC = 2.0 to 5.5V (except where noted).  
Note 2: VCC fall time should not exceed 5 mV/µs.  
RTC Power Down/Up Trip Points DC Characteristics  
1,2  
3
Parameter  
Symbol  
Min.  
Typ.  
Max  
VBAT-0.30  
Units  
3
Backup Switchover Voltage  
VSO  
VBAT-0.90  
VBAT-0.50  
V
Note 1: Valid for ambient operating temperature: TA = 0 to +85°C; VCC = 2.0 to 5.5V (except where noted).  
Note 2: All voltages referenced to VSS.  
Note 3: Switchover and deselect point.  
SERIAL REAL-TIME CLOCK  
10  
REVISION C 07/03/14  
IDT5P90005C DATASHEET  
Clock Operation  
The eight byte clock register (see “Register Map” table) is used to both set the clock and to read the date and time from the  
clock, in a binary coded decimal format. Seconds, minutes, and hours are contained within the first three registers. Bits D6 and  
D7 of clock register 2 (century/hours register) contain the century enable bit (CEB) and the century bit (CB). Setting CEB to a '1'  
will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is  
set to a '0', CB will not toggle. Bits D0 through D2 of register 3 contain the day (day of week). Registers 4, 5 and 6 contain the  
date (day of month), month and years. The final register is the control register (this is described in the clock calibration section).  
Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected  
to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the  
oscillator restarts within one second.  
When reading or writing the time and date registers, secondary(user) buffers are used to prevent error when the internal  
registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any  
start or stop, and when the address pointer rolls over to zero. The countdown chain is reset whenever the seconds register is  
written. Write transfers occurs on the acknowledge pulse from the device. To avoid rollover issues, once the countdown chain is  
reset, the remaining time and date registers must be written within one second. If enabled, the 1Hz square-wave output  
transitions high 500ms after the seconds data transfer, provided the oscillator is already running.  
Note: In order to guarantee oscillator start-up after the initial power-up, set the ST bit to a '1,' then reset this bit to a '0.' This  
sequence enables a “kick start” circuit which aids the oscillator start-up during worst case conditions of voltage and  
temperature.  
1
Register Map  
Data  
D7  
ST  
R
Function/Range  
BCD Format  
Address  
D6  
D5  
D4  
D3  
R
D2  
D1  
D0  
0
1
2
3
4
5
6
7
10 seconds  
10 minutes  
Seconds  
Minutes  
Hours  
Seconds  
00 - 59  
00 - 59  
0-1/00-23  
01 - 07  
01 - 31  
01 - 12  
00 - 99  
Minutes  
Century/Hours  
Day  
CEB2  
CB  
R
10 hours  
R
R
R
R
R
Day  
R
R
10 date  
Date  
Month  
Years  
Date  
R
R
10 M  
R
Month/Century  
Year  
10 years  
OUT  
FT  
R
R
R
R
Control  
Note 1. Keys:  
FT = frequency test bit  
ST = stop bit  
OUT = output level  
CEB = century enable bit  
CB = century bit  
R = Reserved BIT (keep same as default value)  
Note 2. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial  
value set).When CEB is set to '0', CB will not toggle.  
REVISION C 07/03/14  
11  
SERIAL REAL-TIME CLOCK  
IDT5P90005C DATASHEET  
Output Driver Pin  
When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the contents of D7 of the control register. In  
other words, when D6 of address 7 is a zero and D7 of address 7 is a zero and then the FT/OUT pin will be driven low.  
Note: The FT/OUT pin is open drain which requires an external pull-up resistor.  
FT  
0
OUT  
FT/OUT  
0
1
x
0
1
0
1
512Hz  
Initial Power-on Defaults  
Upon initial application of power to the device, the FT bit will be set to a '0' and the OUT bit will be set to a '1'. All other  
register bits will initially power on in a random state.  
Thermal Characteristics  
Parameter  
Symbol  
JA  
Conditions  
Still air  
Min.  
Typ.  
150  
140  
120  
40  
Max. Units  
°C/W  
°C/W  
Thermal Resistance Junction to Ambient  
JA  
1 m/s air flow  
3 m/s air flow  
°C/W  
JA  
°C/W  
Thermal Resistance Junction to Case  
JC  
Marking Diagram  
IDT  
5P90005  
CDCG  
YYWW$  
Notes:  
1. “$” is the assembly mark code.  
2. “YYWW” is the last two digits of the year and week that the part was assembled.  
3. Bottom marking: country of origin if not USA.  
SERIAL REAL-TIME CLOCK  
12  
REVISION C 07/03/14  
IDT5P90005C DATASHEET  
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)  
Package dimensions are kept current with JEDEC Publication No. 95  
Millimeters  
Inches  
8
Symbol  
Min  
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
Max  
1.75  
0.25  
0.51  
0.25  
5.00  
4.00  
Min  
Max  
.0688  
.0098  
.020  
A
A1  
B
C
D
E
e
.0532  
.0040  
.013  
E
H
.0075  
.1890  
.1497  
.0098  
.1968  
.1574  
INDEX  
AREA  
1.27 BASIC  
0.050 BASIC  
H
h
5.80  
0.25  
0.40  
0  
6.20  
0.50  
1.27  
8  
.2284  
.010  
.016  
0  
.2440  
.020  
.050  
8  
1
2
L
D
A
h x 45  
A1  
C
- C -  
e
SEATING  
PLANE  
B
L
.10 (.004)  
C
Ordering Information  
Part / Order Number  
5P90005CDCGH  
5P90005CDCGH8  
Marking  
see page 12  
Shipping Packaging  
Tubes  
Package  
8-pin SOIC  
8-pin SOIC  
Temperature  
0 to +85C  
0 to +85C  
Tape and Reel  
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.  
REVISION C 07/03/14  
13  
SERIAL REAL-TIME CLOCK  
IDT5P90005C DATASHEET  
Revision History  
Rev.  
Date  
Originator Description of Change  
1. Added top-side device marking.  
S. Lou  
B
12/16/13  
2. Moved from Prelim to Final.  
1. Changed ambient operating temperature from -40 to +85°C, to extended commercial  
range; 0 to +85°C.  
2. Updated ordering information to reflect extended commercial range (removed “I”).  
C
C
05/27/14  
07/03/14  
J. Chen  
S. Lou  
Added “H” to orderable part number to reflect extended commercial range.  
SERIAL REAL-TIME CLOCK  
14  
REVISION C 07/03/14  
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San Jose, CA 95138 USA  
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Tech Support  
email: clocks@idt.com  
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www.IDT.com  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether  
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This  
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected  
names, logos and designs, are the property of IDT or their respective third party owners.  
Copyright ©2014 Integrated Device Technology, Inc.. All rights reserved.  
厂商 型号 描述 页数 下载

IDT

 		5P90005CDCGH [ Serial Real-Time Clock ] 15 页

IDT

 		5P90005DCGI 串行实时时钟[ SERIAL REAL-TIME CLOCK ] 16 页

IDT

 		5P90005DCGI8 串行实时时钟[ SERIAL REAL-TIME CLOCK ] 16 页

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