5P49V5935 DATASHEET
If OUT0_SEL_I2CB was 0 at POR, alternate configurations
can only be loaded via the I2C interface.
PLL Features and Descriptions
Spread Spectrum
Table 4: Input Clock Select
Input clock select. Selects the active input reference source in
manual switchover mode.
0 = Integrated XTAL (default)
1 = CLKIN, CLKINB
To help reduce electromagnetic interference (EMI), the
5P49V5935 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread energy
across a broader range of frequencies, lowering system EMI.
The 5P49V5935 implements spread spectrum using the
Fractional-N output divide, to achieve controllable modulation
rate and spreading magnitude. The Spread spectrum can be
applied to any output clock, any clock frequency, and any
spread amount from ±0.25% to ±2.5% center spread and
-0.5% to -5% down spread.
2
CLKSEL Polarity can be changed by I C programming as
shown in the table below.
PRIMSRC
CLKSEL
Source
0
0
1
1
0
1
0
1
Integrated XTAL
CLKIN, CLKINB
CLKIN, CLKINB
Integrated XTAL
Table 2: Loop Filter
PLL loop bandwidth range depends on the input reference
frequency (Fref) and can be set between the loop bandwidth
range as shown in the table below.
PRIMSRC is bit 1 of Register 0x13.
Input Reference
Loop
Loop
Frequency–Fref BandwidthMin Bandwidth Max
Reference Clock Input Pins and
Selection
(MHz)
1
(kHz)
40
(kHz)
126
The 5P49V5935 by default uses an integrated 25MHz crystal
as input reference. It also has a redundant external clock
input. A glitchless manual switchover functions allows
selection of either one as mentioned above as input reference
during normal operation.
350
300
1000
Table 3: Configuration Table
This table shows the SEL1, SEL0 settings to select the
configuration stored in OTP. Four configurations can be stored
in OTP. These can be factory programmed or user
programmed.
Either clock input can be set as the primary clock. The primary
clock designation is to establish which is the main reference
clock to the PLL. The non-primary clock is designated as the
secondary clock in case the primary clock goes absent and a
backup is needed. The PRIMSRC bit determines which clock
input will be selected as primary clock. When PRIMSRC bit is
“0”, integrated crystal is selected as the primary clock, and
when “1”, (CLKIN, CLKINB) as the primary clock.
2
OUT0_SEL_I2CB SEL1 SEL0
@ POR
I C
REG0:7 Config
Access
1
1
1
1
0
0
0
1
1
X
0
1
0
1
X
No
No
No
No
Yes
0
0
0
0
1
0
1
2
3
The two reference inputs can be manually selected using the
CLKSEL pin. The SM bits must be set to “0x” for manual
switchover which is detailed in Manual Switchover Mode
section.
I2C
defaults
0
X
X
Yes
0
0
Manual Switchover Mode
At power up time, the SEL0 and SEL1 pins must be tied to
either the VDDD/VDDA power supply so that they ramp with
that supply or are tied low (this is the same as floating the
pins). This will cause the register configuration to be loaded
that is selected according to Table 3 above. Providing that
OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after
the first 10mS of operation the levels of the SELx pins can be
changed, either to low or to the same level as VDDD/VDDA.
The SELx pins must be driven with a digital signal of < 300nS
Rise/Fall time and only a single pin can be changed at a time.
After a pin level change, the device must not be interrupted for
at least 1ms so that the new values have time to load and take
effect.
When SM[1:0] is “0x”, the redundant inputs are in manual
switchover mode. In this mode, CLKSEL pin is used to switch
between the primary and secondary clock sources. The
primary and secondary clock source setting is determined by
the PRIMSRC bit. During the switchover, no glitches will occur
at the output of the device, although there may be frequency
and phase drift, depending on the exact phase and frequency
relationship between the primary and secondary clocks.
PROGRAMMABLE CLOCK GENERATOR
4
NOVEMBER 11, 2016
