5P49V5944_17,PDF,5P49V5944_17 PDF资料,Datasheet,下载5P49V5944

Programmable Clock Generator

5P49V5944

DATASHEET

Description

Features

The 5P49V5944 is a programmable clock generator intended

for high-performance consumer, networking, industrial,

computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

• Generates up to two independent output frequencies

• High-performance, low phase noise PLL, < 0.7ps RMS

typical phase jitter on outputs:

2

– PCIe Gen1–3 compliant clock capability

– USB 3.0 compliant clock capability

– 1 GbE and 10 GbE

Programmable (OTP) memory or changed using I C

interface. This is IDT’s fifth generation of programmable clock

®

technology (VersaClock 5).

The frequencies are generated from a single reference clock.

The input reference can be either a crystal or an LVCMOS

reference clock.

• Two fractional output dividers (FODs)

• Independent spread spectrum capability on each output

pair

Two select pins allow up to 4 different configurations to be

programmed and accessible using processor GPIOs or

bootstrapping. The different selections may be used for

different operating modes (full function, partial function, partial

power-down), regional standards (US, Japan, Europe) or

system production margin testing.

• Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

2

• I C serial programming interface

• One reference LVCMOS output clock

• Two universal output pairs:

2

The device may be configured to use one of two I C

– Each configurable as one differential output pair or two

LVCMOS outputs

addresses to allow multiple devices to be used in a system.

• I/O standards:

Pin Assignment

– Single-ended I/Os: 1.8V to 3.3V LVCMOS

– Differential I/Os: LVPECL, LVDS and HCSL

• Input frequency ranges:

– LVCMOS reference clock input (XIN/REF): 1MHz to

200MHz

– Crystal frequency range: 8MHz to 40MHz

• Output frequency ranges:

– LVCMOS clock outputs: 1MHz to 200MHz

20 19 18 17 16

1

– LVDS, LVPECL, HCSL differential clock outputs: 1MHz

to 350MHz

15

14

13

V_DDO1

XOUT

XIN/REF

V_DDA

2

OUT1

• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for

each output pair

EPAD

8

3

4

OUT1B

12

11

• Programmable loop bandwidth

• Programmable output to output skew

• Programmable slew rate control

• Programmable crystal load capacitance

• Individual output enable/disable

• Power-down mode

GND

5

SD/OE

7

9

10

6

• 1.8V, 2.5V or 3.3V core V

, V

DDA

DDD

• 3 x 3 mm 20-VFQFPN package

• -40° to +85°C industrial temperature operation

3 × 3 mm 20-VFQFPN

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5P49V5944 DATASHEET

Functional Block Diagram

V_DDO0

OUT0_SEL_I2CB

XIN/REF

XOUT

V_DDO1

SD/OE

OUT1

PLL

FOD1

FOD2

SEL1/SDA

OUT1B

OTP

and

Control Logic

SEL0/SCL

V_DDO

2

V_DDA

OUT2

V_DDD

OUT2B

Applications

• Ethernet switch/router

• PCI Express 1.0/2.0/3.0

• Broadcast video/audio timing

• Multi-function printer

• Processor and FPGA clocking

• Any-frequency clock conversion

• MSAN/DSLAM/PON

• Fiber channel, SAN

• Telecom line cards

• 1 GbE and 10 GbE

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Table 1: Pin Descriptions

Number

Name

Type

Description

1

XOUT

Input

Crystal Oscillator interface output.

Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure

that the input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF

Interface”.

2

XIN/REF

Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD

should have the same voltage applied.

Connect to ground.

3

4

VDDA

GND

Power

Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit

controls the configuration of the SD/OE pin. The SH bit needs to be high for

SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of the

signal to be either active HIGH or LOW only when pin is configured as OE

(Default is active LOW.) Weak internal pull down resistor. When configured as

SD, device is shut down, differential outputs are driven high/low, and the single-

ended LVCMOS outputs are driven low. When configured as OE, and outputs are

disabled, the outputs can be selected to be tri-stated or driven high/low,

depending on the programming bits as shown in the SD/OE Pin Function Truth

table.

5

SD/OE

Input

Pull-down

Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB.

Weak internal pull down resistor.

Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB.

Weak internal pull down resistor.

6

7

SEL1/SDA

SEL0/SCL

Input

Pull-down

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT2/OUT2B.

Output Clock 2. Please refer to the Output Drivers section for more details.

Complementary Output Clock 2. Please refer to the Output Drivers section for

more details.

8

9

VDDO2

OUT2

Power

Output

10

OUT2B

11

12

GND

Power

Connect to ground.

Complementary Output Clock 1. Please refer to the Output Drivers section for

more details.

Output Clock 1. Please refer to the Output Drivers section for more details.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT1/OUT1B.

13

14

15

16

17

18

19

OUT1B

OUT1

Output

Power

VDDO1

GND

Connect to ground.

Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDB

should have the same voltage applied.

Connect to ground.

Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output

voltage levels for OUT0.

VDDD

GND

VDDO0

Latched input/LVCMOS Output. At power up, the voltage at the pin

OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8

and 9. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9

20

OUT0_SELB_I2C Input/Output Pull-down will be configured as hardware select pins, SEL1 and SEL0. If a weak pull down

(10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will

act as the SDA and SCL pins of an I2C interface. After power up, the pin acts as

a LVCMOS reference output.

ePAD

Connect to ground pad.

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5P49V5944 DATASHEET

PLL Features and Descriptions

After a pin level change, the device must not be interrupted for

at least 1ms so that the new values have time to load and take

effect.

Spread Spectrum

To help reduce electromagnetic interference (EMI), the

5P49V5944 supports spread spectrum modulation. The

output clock frequencies can be modulated to spread energy

across a broader range of frequencies, lowering system EMI.

The 5P49V5944 implements spread spectrum using the

Fractional-N output divide, to achieve controllable modulation

rate and spreading magnitude. The spread spectrum can be

applied to any output clock, any clock frequency, and any

spread amount from ±0.25% to ±2.5% center spread and

-0.5% to -5% down spread.

If OUT0_SEL_I2CB was 0 at POR, alternate configurations

2

can only be loaded via the I C interface.

Table 2: Loop Filter

PLL loop bandwidth range depends on the input reference

frequency (Fref) and can be set between the loop bandwidth

range as shown in the table below.

Input Reference

Loop

Frequency–Fref BandwidthMin Bandwidth Max

(MHz)

1

(kHz)

40

(kHz)

126

350

300

1000

Table 3: Configuration Table

This table shows the SEL1, SEL0 settings to select the

configuration stored in OTP. Four configurations can be stored

in OTP. These can be factory programmed or user

programmed.

2

OUT0_SEL_I2CB SEL1 SEL0

at POR

I C

REG0:7 Config

Access

1

0

1

X

0

1

0

1

X

No

Yes

0

1

0

1

2

3

I²C

defaults

0

X

Yes

0

At power up time, the SEL0 and SEL1 pins must be tied to

either the VDDD/VDDA power supply so that they ramp with

that supply or are tied low (this is the same as floating the

pins). This will cause the register configuration to be loaded

that is selected according to Table 3 above. Providing that

OUT0_SEL_I2CB was 1 at POR and OTP register 0:7 = 0,

after the first 10ms of operation the levels of the SELx pins can

be changed, either to low or to the same level as

VDDD/VDDA. The SELx pins must be driven with a digital

signal of < 300ns Rise/Fall time and only a single pin can be

changed at a time.

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5P49V5944 DATASHEET

Reference Clock Input Pins

The 5P49V5944 supports one clock input. The clock input

(XIN/ REF) can be driven by either an external crystal or a

reference clock.

Crystal Input (XIN/REF)

The crystal used should be a fundamental mode quartz

crystal; overtone crystals should not be used.

A crystal manufacturer will calibrate its crystals to the nominal

frequency with a certain load capacitance value. When the

oscillator load capacitance matches the crystal load

capacitance, the oscillation frequency will be accurate. When

the oscillator load capacitance is lower than the crystal load

capacitance, the oscillation frequency will be higher than

nominal and vice versa so for an accurate oscillation

frequency you need to make sure to match the oscillator load

capacitance with the crystal load capacitance.

You can write the following equations for the total capacitance

at each crystal pin:

C

= Ci + Cs + Ce

1 1 1

XIN

= Ci + Cs + Ce

XOUT

2

To set the oscillator load capacitance there are two tuning

capacitors in the IC, one at XIN and one at XOUT. They can

be adjusted independently but commonly the same value is

used for both capacitors. The value of each capacitor is

composed of a fixed capacitance amount plus a variable

capacitance amount set with the XTAL[5:0] register.

Adjustment of the crystal tuning capacitors allows for

maximum flexibility to accommodate crystals from various

manufacturers. The range of tuning capacitor values available

are in accordance with the following table.

Ci and Ci are the internal, tunable capacitors. Cs and Cs

2

are stray capacitances at each crystal pin and typical values

are between 1pF and 3pF.

1

2

1

Ce and Ce are additional external capacitors that can be

1

2

added to increase the crystal load capacitance beyond the

tuning range of the internal capacitors. However, increasing

the load capacitance reduces the oscillator gain so please

consult the factory when adding Ce and/or Ce to avoid

1

2

crystal startup issues. Ce and Ce can also be used to adjust

1

2

for unpredictable stray capacitance in the PCB.

XTAL[5:0] Tuning Capacitor Characteristics

The final load capacitance of the crystal:

Parameter

Bits

Step (pF)

Min. (pF)

Max. (pF)

C = C

× C

/ (C

+ C

)

XOUT

L

XIN

XOUT

XIN

XTAL

6

0.5

9

25

For most cases it is recommended to set the value for

capacitors the same at each crystal pin:

The capacitance at each crystal pin inside the chip starts at

9pF with setting 000000b and can be increased up to 25pF

with setting 111111b. The step per bit is 0.5pF.

C

= C

= Cx → C = Cx / 2

XOUT L

XIN

The complete formula when the capacitance at both crystal

pins is the same:

You can write the following equation for this capacitance:

Ci = 9pF + 0.5pF × XTAL[5:0]

C = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2

L

The PCB where the IC and the crystal will be assembled adds

some stray capacitance to each crystal pin and more

capacitance can be added to each crystal pin with additional

external capacitors.

Example 1: The crystal load capacitance is specified as 8pF

and the stray capacitance at each crystal pin is Cs = 1.5pF.

Assuming equal capacitance value at XIN and XOUT, the

equation is as follows:

8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2 →

0.5pF × XTAL[5:0] = 5.5pF → XTAL[5:0] = 11 (decimal)

Example 2: The crystal load capacitance is specified as 12pF

and the stray capacitance Cs is unknown. Footprints for

external capacitors Ce are added and a worst case Cs of 5pF

is used. For now we use Cs + Ce = 5pF and the right value for

Ce can be determined later to make 5pF together with Cs.

12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2 →

XTAL[5:0] = 20 (decimal)

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OTP Interface

Table 4: SD/OE Pin Function Truth Table

SH bit SP bit OSn bit OEn bit SD/OE

OUTn

The 5P49V5944 can also store its configuration in an internal

OTP. The contents of the device's internal programming

registers can be saved to the OTP by setting burn_start

(W114[3]) to high and can be loaded back to the internal

programming registers by setting usr_rd_start(W114[0]) to

high.

0

1

x

0

1

x

0

1

Tri-state²

Output active

Output driven High Low

0

1

0

1

x

0

1

x

0

1

Tri-state²

Output active

Output driven High Low

Output active

2

To initiate a save or restore using I C, only two bytes are

transferred. The Device Address is issued with the read/write

bit set to “0”, followed by the appropriate command code. The

save or restore instruction executes after the STOP condition

is issued by the Master, during which time the 5P49V5944 will

not generate Acknowledge bits. The 5P49V5944 will

1

0

1

x

0

1

0

Tri-state²

Output active

1

0

1

x

0

1

0

Tri-state²

acknowledge the instructions after it has completed execution

Output active

Output driven High Low

Output driven High Low ¹

2

of them. During that time, the I C bus should be interpreted as

busy by all other users of the bus.

1

x

1

On power-up of the 5P49V5944, an automatic restore is

performed to load the OTP contents into the internal

programming registers. The 5P49V5944 will be ready to

accept a programming instruction once it acknowledges its

Note 1 : Global Shutdown

Note 2 : Tri-state regardless of OEn bits

2

Output Alignment

7-bit I C address.

2

Each output divider block has a synchronizing POR pulse to

provide startup alignment between outputs. This allows

alignment of outputs for low skew performance. The phase

alignment works both for integer output divider values and for

fractional output divider values.

Availability of Primary and Secondary I C addresses to allow

2

programming for multiple devices in a system. The I C slave

address can be changed from the default 0xD4 to 0xD0 by

programming the I2C_ADDR bit D0. VersaClock 5

2

Programming Guide provides detailed I C programming

guidelines and register map.

Besides the POR at power up, the same synchronization reset

is also triggered when switching between configurations with

the SEL0/1 pins. This ensures that the outputs remain aligned

in every configuration. This reset causes the outputs to

suspend for a few hundred microseconds so the switchover is

not glitch-less. The reset can be disabled for applications

where glitch-less switch over is required and alignment is not

critical.

SD/OE Pin Function

The polarity of the SD/OE signal pin can be programmed to be

either active HIGH or LOW with the SP bit (W16[1]). When SP

is “0” (default), the pin becomes active LOW and when SP is

“1”, the pin becomes active HIGH. The SD/OE pin can be

configured as either to shutdown the PLL or to enable/disable

the outputs. The SH bit controls the configuration of the

SD/OE pin The SH bit needs to be high for SD/OE pin to be

configured as SD.

2

When using I C to reprogram an output divider during

operation, alignment can be lost. Alignment can be restored

2

by manually triggering the reset through I C.

When alignment is required for outputs with different

SP

OUTn

frequencies, the outputs are actually aligned on the falling

edges of each output by default. Rising edge alignment can

also be achieved by utilizing the programmable skew feature

to delay the faster clock by 180 degrees. The programmable

skew feature also allows for fine tuning of the alignment.

SD/OE Input

OEn

Global Shutdown

OSn

SH

For details of register programming, please see VersaClock 5

Family Register Descriptions and Programming Guide for

details.

When configured as SD, device is shut down, differential

outputs are driven High/low, and the single-ended LVCMOS

outputs are driven low. When configured as OE, and outputs

are disabled, the outputs are driven high/low.

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Output Divides

Device Hardware Configuration

Each of the four output divides are comprised of a 12-bit

integer counter, and a 24-bit fractional counter. The output

divide can operate in integer divide only mode for improved

performance, or utilize the fractional counters to generate any

frequency with a synthesis accuracy better than 50ppb.

The 5P49V5944 supports an internal One-Time

Programmable (OTP) memory that can be pre-programmed

at the factory with up to 4 complete device configuration.

These configurations can be over-written using the serial

interface once reset is complete. Any configuration written via

the programming interface needs to be re-written after any

power cycle or reset. Contact IDT if a specific

The output divide also has the capability to apply a spread

modulation to the output frequency. Independent of output

frequency, a triangle wave modulation between 30 and 63kHz

may be generated.

factory-programmed configuration is desired.

Device Start-up & Reset Behavior

Output Skew

The 5P49V5944 has an internal power-up reset (POR) circuit.

The POR circuit will remain active for a maximum of 10ms

after device power-up.

For outputs that share a common output divide value, there

will be the ability to skew outputs by quadrature values to

minimize interaction on the PCB. The skew on each output

can be adjusted from 0 to 360 degrees. Skew is adjusted in

units equal to 1/32 of the VCO period. So, for 100MHz output

and a 2800MHz VCO, you can select how many 11.161ps

units you want added to your skew (resulting in units of 0.402

degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so

on. The granularity of the skew adjustment is always

Upon internal POR circuit expiring, the device will exit reset

and begin self-configuration.

The device will load internal registers according to Table 3.

Once the full configuration has been loaded, the device will

respond to accesses on the serial port and will attempt to lock

the PLL to the selected source and begin operation.

dependent on the VCO period and the output period.

Power Up Ramp Sequence

Output Drivers

VDDA and VDDD must ramp up together. VDDO0–2 must

ramp up before, or concurrently with, VDDA and VDDD. All

power supply pins must be connected to a power rail even if

the output is unused. All power supplies must ramp in a linear

fashion and ramp monotonically.

The OUT1 to OUT2 clock outputs are provided with

register-controlled output drivers. By selecting the output drive

type in the appropriate register, any of these outputs can

support LVCMOS, LVPECL, HCSL or LVDS logic levels

The operating voltage ranges of each output is determined by

its independent output power pin (V

) and thus each can

DDO

VDDO0~2

have different output voltage levels. Output voltage levels of

2.5V or 3.3V are supported for differential HCSL, LVPECL

operation, and 1. 8V, 2.5V, or 3.3V are supported for LVCMOS

and differential LVDS operation.

Each output may be enabled or disabled by register bits.

When disabled an output will be in a logic 0 state as

determined by the programming bit table shown on page 6.

VDDA

VDDD

LVCMOS Operation

When a given output is configured to provide LVCMOS levels,

then both the OUTx and OUTxB outputs will toggle at the

selected output frequency. All the previously described

configuration and control apply equally to both outputs.

Frequency, phase alignment, voltage levels and enable /

disable status apply to both the OUTx and OUTxB pins. The

OUTx and OUTxB outputs can be selected to be

phase-aligned with each other or inverted relative to one

another by register programming bits. Selection of

phase-alignment may have negative effects on the phase

noise performance of any part of the device due to increased

simultaneous switching noise within the device.

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2

I C Mode Operation

2

The device acts as a slave device on the I C bus using one of

2

the two I C addresses (0xD0 or 0xD4) to allow multiple

devices to be used in the system. The interface accepts

byte-oriented block write and block read operations. Two

address bytes specify the register address of the byte position

of the first register to write or read. Data bytes (registers) are

accessed in sequential order from the lowest to the highest

byte (most significant bit first). Read and write block transfers

can be stopped after any complete byte transfer. During a

write operation, data will not be moved into the registers until

the STOP bit is received, at which point, all data received in

the block write will be written simultaneously.

2

For full electrical I C compliance, it is recommended to use

external pull-up resistors for SDATA and SCLK. The internal

pull-down resistors have a size of 100k typical.

Current Read

S

Dev Addr + R

A

Data 0

A

Data 1

A

Data n

Data 0

A

Abar

P

Sequential Read

S

Dev Addr + W

Reg start Addr

A

Sr

Dev Addr + R

A

Data 1

A

Data n

Abar

P

Sequential Write

S

Dev Addr + W

Data 0

A

Data 1

A

Data n

A

P

S = start

from master to slave

from slave to master

Sr = repeated start

A = acknowledge

Abar= none acknowledge

P = stop

I²C Slave Read and Write Cycle Sequencing

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Table 5: I²C Bus DC Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

For SEL1/SDA pin

and SEL0/SCL

pin.

5.5 ²

VIH

Input HIGH Level

Input LOW Level

0.7xVDDD

V

For SEL1/SDA pin

and SEL0/SCL

pin.

VIL

GND-0.3

0.3xVDDD

V

VHYS

IIN

VOL

Hysteresis of Inputs

Input Leakage Current

Output LOW Voltage

0.05xVDDD

-1

V

µA

V

30

0.4

IOL = 3 mA

Table 6: I²C Bus AC Characteristics

Symbol

FSCLK

tBUF

Parameter

Serial Clock Frequency (SCL)

Bus free time between STOP and START

Min

10

1.3

0.6

0.1

Typ

Max

400

Unit

kHz

µs

tSU:START Setup Time, START

tHD:START Hold Time, START

tSU:DATA Setup Time, data input (SDA)

tHD:DATA Hold Time, data input (SDA) ¹

µs

0

µs

pF

ns

µs

tOVD

CB

tR

tF

tHIGH

tLOW

Output data valid from clock

0.9

400

300

Capacitive Load for Each Bus Line

Rise Time, data and clock (SDA, SCL)

Fall Time, data and clock (SDA, SCL)

HIGH Time, clock (SCL)

20 + 0.1 x CB

0.6

1.3

0.6

LOW Time, clock (SCL)

tSU:STOP Setup Time, STOP

Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IH(MIN) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

Note 2: I²C inputs are 5V tolerant.

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Table 7: Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 5P49V5944. These ratings, which are standard values for IDT

commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect

product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

Item

Rating

Supply Voltage, V_DDA,V_DDD,V_DDO

3.465V

Inputs

XIN/REF

Other inputs

0V to 1.2V voltage swing

-0.5V to V_DDD

Outputs, V_DDO(LVCMOS)

Outputs, I_O(SDA)

-0.5V to V_DDO+ 0.5V

10mA

Package Thermal Impedance, _JA

Package Thermal Impedance, _JC

Storage Temperature, T_STG

ESD Human Body Model

Junction Temperature

42C/W (0 mps)

41.8C/W (0 mps)

-65C to 150C

2000V

125°C

Table 8: Recommended Operation Conditions

Symbol

V_DDOx

V_DDD

Parameter

Min

1.71

Typ

1.8

2.5

3.3

Max

1.89

Unit

V

Power supply voltage for supporting 1.8V outputs

Power supply voltage for supporting 2.5V outputs

Power supply voltage for supporting 3.3V outputs

2.375

3.135

1.71

2.625

3.465

V

Power supply voltage for core logic functions.

Analog power supply voltage. Use filtered analog power

supply if available.

V

V_DDA

1.71

-40

3.465

V

T_A

C_{LOAD_OUT}

F_IN

Operating temperature, ambient

85

15

40

°C

pF

Maximum load capacitance (3.3V LVCMOS only)

External reference crystal

8

MHz

Power up time for all VDDs to reach minimum specified

voltage (power ramps must be monotonic)

t_PU

0.05

5

ms

Note: V_DDO1 and V_DDO2 must be powered on either before or simultaneously with V_DDD, V_DDAand V_DDO0.

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Table 9: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down

Resistance (T = +25 °C)

A

Symbol

Parameter

Min

Typ

Max

7

Unit

pF

C_IN

Input Capacitance (SD/OE, SEL1/SDA, SEL0/SCL)

3

SD/OE, SEL1/SDA, SEL0/SCL, OUT0_SEL_I2CB

Pull-down Resistor

R_OUT

100

300

kΩ

Ω

LVCMOS Output Driver Impedance (VDDO = 1.8V, 2.5V, 3.3V)

17

Programmable capacitance at XIN/REF (X1 in parallel with X2)

Programmable capacitance at XOUT (X1 in parallel with X2)

XIN/REF

XOUT

0

8

pF

Table 10: Crystal Characteristics

Parameter

Mode of Oscillation

Frequency

Equivalent Series Resistance (ESR)

Shunt Capacitance

Test Conditions

Minimum

Typical Maximum

Fundamental

25

Units

8

40

100

7

MHz

Ω

10

pF

Load Capacitance (CL) @ <=25 MHz

Load Capacitance (CL) >25M to 40M

Maximum Crystal Drive Level

6

8

12

8

100

pF

µW

Note: Typical crystal used is FOX 603-25-150. For different reference crystal options please go to www.foxonline.com.

Table 11: DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

100 MHz on all outputs, 25 MHz

REFCLK

Iddcore³

Core Supply Current

30

42

37

18

17

16

29

28

16

14

12

36

27

16

10

34

47

42

21

20

19

33

18

16

14

42

32

19

14

mA

LVPECL, 350 MHz, 3.3V VDDOx

LVPECL, 350 MHz, 2.5V VDDOx

LVDS, 350 MHz, 3.3V VDDOx

LVDS, 350 MHz, 2.5V VDDOx

LVDS, 350 MHz, 1.8V VDDOx

HCSL, 250 MHz, 3.3V VDDOx, 2 pF load

HCSL, 250 MHz, 2.5V VDDOx, 2 pF load

Iddox

Output Buffer Supply Current

1,2

LVCMOS, 50 MHz, 3.3V, VDDOx

1,2

LVCMOS, 50 MHz, 2.5V, VDDOx

1,2

LVCMOS, 50 MHz, 1.8V, VDDOx

LVCMOS, 200 MHz, 3.3V VDDOx¹

LVCMOS, 200 MHz, 2.5V VDDOx^1,2

LVCMOS, 200 MHz, 1.8V VDDOx^1,2

SD asserted, I2C Programming

Iddpd

Power Down Current

1. Single CMOS driver active.

2. Measured into a 5” 50 Ohm trace with 2 pF load.

3. Iddcore = IddA+ IddD, no loads.

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5P49V5944 DATASHEET

1

Table 12: DC Electrical Characteristics for 3.3V LVCMOS (V

= 3.3V ±5%, T = -40°C to +85°C)

A

DDO

Symbol

VOH

VOL

IOZDD

VIH

Parameter

Test Conditions

Min

Typ

Max

Unit

IOH = -15mA

Output HIGH Voltage

Output LOW Voltage

Output Leakage Current (OUT1~4)

Output Leakage Current (OUT0)

Input HIGH Voltage

2.4

VDDO

V

IOL = 15mA

0.4

Tri-state outputs, VDDO = 3.465V

Single-ended inputs - SD/OE

Single-ended input OUT0_SEL_I2CB

Single-ended input - XIN/REF

5

30

µA

V

0.7xVDDD

GND - 0.3

2

VDDD + 0.3

0.3xVDDD

VDDO0 + 0.3

0.4

VIL

Input LOW Voltage

V

VIH

Input HIGH Voltage

V

VIL

Input LOW Voltage

GND - 0.3

0.8

V

VIH

Input HIGH Voltage

1.2

V

VIL

Input LOW Voltage

GND - 0.3

0.4

V

TR/TF

SD/OE, SEL1/SDA, SEL0/SCL

Input Rise/Fall Time

300

ns

1. See “Recommended Operating Conditions” table.

Table 13: DC Electrical Characteristics for 2.5V LVCMOS (V

= 2.5V ±5%, T = -40°C to +85°C)

A

DDO

Symbol

VOH

VOL

IOZDD

VIH

Parameter

Test Conditions

Min

Typ

Max

Unit

V

IOH = -12mA

Output HIGH Voltage

Output LOW Voltage

Output Leakage Current (OUT1~4)

Output Leakage Current (OUT0)

Input HIGH Voltage

0.7xVDDO

IOL = 12mA

0.4

V

Tri-state outputs, VDDO = 2.625V

Single-ended inputs - SD/OE

Single-ended input OUT0_SEL_I2CB

Single-ended input - XIN/REF

SD/OE, SEL1/SDA, SEL0/SCL

5

30

µA

V

0.7xVDDD

GND - 0.3

1.7

VDDD + 0.3

0.3xVDDD

VDDO0 + 0.3

0.4

VIL

Input LOW Voltage

V

VIH

Input HIGH Voltage

V

VIL

Input LOW Voltage

GND - 0.3

0.8

V

VIH

Input HIGH Voltage

1.2

V

VIL

Input LOW Voltage

GND - 0.3

0.4

V

TR/TF

Input Rise/Fall Time

300

ns

Table 14: DC Electrical Characteristics for 1.8V LVCMOS ^(V

= 1.8V ±5%, T = -40°C to +85°C)

A

DDO

Symbol

VOH

VOL

IOZDD

VIH

Parameter

Test Conditions

Min

Typ

Max

Unit

V

IOH = -8mA

Output HIGH Voltage

Output LOW Voltage

Output Leakage Current (OUT1~4)

Output Leakage Current (OUT0)

Input HIGH Voltage

0.7 xVDDO

VDDO

IOL = 8mA

0.25 x VDDO

V

Tri-state outputs, VDDO = 1.89V

Single-ended inputs - SD/OE

Single-ended input OUT0_SEL_I2CB

Single-ended input - XIN/REF

SD/OE, SEL1/SDA, SEL0/SCL

5

30

µA

V

0.7 * VDDD

GND - 0.3

0.65 * VDDO0

GND - 0.3

0.8

VDDD + 0.3

0.3 * VDDD

VDDO0 + 0.3

0.4

VIL

Input LOW Voltage

V

VIH

Input HIGH Voltage

V

VIL

Input LOW Voltage

V

VIH

Input HIGH Voltage

1.2

V

VIL

Input LOW Voltage

GND - 0.3

0.4

V

TR/TF

Input Rise/Fall Time

300

ns

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5P49V5944 DATASHEET

Table 15: DC Electrical Characteristics for LVDS (V

= 3.3V +5% or 2.5V +5%, T = -40°C to +85°C)

DDO

A

Symbol

Parameter

Min

247

Typ

Max

454

-454

50

Unit

mV

V

Differential Output Voltage for the TRUE binary state

Differential Output Voltage for the FALSE binary state

Change in V_OTbetween Complimentary Output States

Output Common Mode Voltage (Offset Voltage)

V

(+)

(-)

OT

V

-247

OT

V

OT

V

1.125

1.25

1.375

50

OS

Change in V_OSbetween Complimentary Output States

Outputs Short Circuit Current, V_OUT+ or V_OUT- = 0V or V_DDO

V

mV

mA

OS

I

9

6

24

OS

Differential Outputs Short Circuit Current, V_OUT+ = V_OUT

-

I

12

OSD

Table 16: DC Electrical Characteristics for LVDS (V

= 1.8V +5%, T = -40°C to +85°C)

A

DDO

Symbol

Parameter

Min

247

Typ

Max

454

-454

50

Unit

mV

V

Differential Output Voltage for the TRUE binary state

Differential Output Voltage for the FALSE binary state

Change in V_OTbetween Complimentary Output States

Output Common Mode Voltage (Offset Voltage)

V

(+)

(-)

OT

V

-247

OT

V

OT

V

0.8

0.875

0.95

50

OS

Change in V_OSbetween Complimentary Output States

Outputs Short Circuit Current, V_OUT+ or V_OUT- = 0V or V_DDO

V

mV

mA

OS

I

9

6

24

OS

Differential Outputs Short Circuit Current, V_OUT+ = V_OUT

-

I

12

OSD

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5P49V5944 DATASHEET

Table 17: DC Electrical Characteristics for LVPECL (V

+85°C)

= 3.3V +5% or 2.5V +5%, T = -40°C to

A

DDO

Symbol

Parameter

Min

Typ

Max

Unit

V

Output Voltage HIGH, terminated through 50 tied to V_DD- 2 V

Output Voltage LOW, terminated through 50 tied to V_DD- 2 V

Peak-to-Peak Output Voltage Swing

V

- 1.19

- 1.94

V

- 0.69

DDO

OH

DDO

V

- 1.4

DDO

V

OL

V

0.55

0.993

V

SWING

Table 18: Electrical Characteristics – DIF 0.7V Low Power HCSL Differential Outputs

(V

= 3.3V ±5%, 2.5V ±5%, T = -40°C to +85°C)

A

DDO

Symbol Parameter

Conditions

Min

Typ

Max

4

Units

V/ns

%

Notes

1,2,3

dV/dt

Slew Rate

Scope averaging on

1

Scope averaging on

20

Δ

Statistical measurement on single-ended

signal using oscilloscope math function

(Scope averaging ON)

VHIGH

VLOW

VMAX

VMIN

Voltage High

660

850

150

mV

1,6,7

1,6

1

Voltage Low

-150

Maximum Voltage

Minimum Voltage

1150

Measurement on single-ended signal using

absolute value (Scope averaging off)

Scope averaging off

-300

300

250

1

VSWING Voltage Swing

1,2,6

1,4,6

1,5

Scope averaging off

VCROSS Crossing Voltage Value

550

140

VCROSS

Crossing Voltage variation

Δ

1. Guaranteed by design and characterization. Not 100% tested in production.

2. Measured from differential waveform.

3. Slew rate is measured through the V_SWINGvoltage range centered around differential 0V. This results in a ±150mV window around differential 0V.

4. V_CROSSis defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and

Clock# falling).

5. The total variation of all V_CROSSmeasurements in any particular system. Note that this is a subset of V_CROSSmin/max (V_CROSSabsolute) allowed. The intent

is to limit V_CROSSinduced modulation by setting V_CROSSto be smaller than V_CROSSabsolute.

6. Measured from single-ended waveform.

7. Measured with scope averaging off, using statistics function. Variation is difference between minimum and maximum.

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5P49V5944 DATASHEET

Table 19: AC Timing Electrical Characteristics

(V_DDO= 3.3V +5% or 2.5V +5% or 1.8V ±5%, T = -40°C to +85°C)

A

(Spread spectrum generation = OFF)

Symbol

Min.

Typ.

Max.

40

Units

Parameter

Test Conditions

1

Input Frequency

1

MHz

f_IN

Input frequency limit (XIN)

200

Single ended clock output limit (LVCMOS)

Differential cock output limit (LVPECL/

LVDS/HCSL)

f_OUT

Output Frequency

MHz

1

350

f_VCO

f_PFD

f_BW

t2

VCO Frequency

PFD Frequency

Loop Bandwidth

Input Duty Cycle

2600

2900

150

0.9

MHz

%

VCO operating frequency range

PFD operating frequency range

Input frequency = 25MHz

1 ¹

0.06

45

50

55

Duty Cycle

Measured at VDD/2, all outputs except

Reference output OUT0, VDDOX= 2.5V or

3.3V

Measured at VDD/2, all outputs except

Reference output OUT0, VDDOX=1.8V

Measured at VDD/2, Reference output

OUT0 (5MHz - 120MHz) with 50% duty

cycle input

45

40

55

60

%

50

t3 ⁵

Output Duty Cycle

Measured at VDD/2, Reference output

OUT0 (150.1MHz - 200MHz) with 50% duty

cycle input

30

50

70

%

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Rise Times

2.2

2.3

2.4

2.7

1.3

1.4

1.7

0.7

0.8

0.9

1.2

300

400

1.0

1.2

1.3

1.7

0.6

0.7

0.6

1.0

0.3

0.4

0.7

Single-ended 3.3V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX=3.3V

Single-ended 2.5V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX=2.5V

t4 ²

V/ns

Single-ended 1.8V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX=1.8V

LVDS, 20% to 80%

LVDS, 80% to 20%

LVPECL, 20% to 80%

LVPECL, 80% to 20%

Fall Times

t5

ps

Rise Times

Fall Times

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PROGRAMMABLE CLOCK GENERATOR

5P49V5944 DATASHEET

Cycle-to-Cycle jitter (Peak-to-Peak),

multiple output frequencies switching,

differential outputs (1.8V to 3.3V nominal

output voltage)

OUT0=25MHz

OUT1=100MHz

46

ps

OUT2=125MHz

OUT3=156.25MHz

Cycle-to-Cycle jitter (Peak-to-Peak),

multiple output frequencies switching,

LVCMOS outputs (1.8 to 3.3V nominal

output voltage)

OUT0=25MHz

OUT1=100MHz

74

OUT2=125MHz

OUT3=156.25MHz

t6

Clock Jitter

RMS Phase Jitter (12kHz to 5MHz

integration range) reference clock (OUT0),

25 MHz LVCMOS outputs (1.8 to 3.3V

nominal output voltage).

OUT0=25MHz

0.5

OUT1=100MHz

OUT2=125MHz

OUT3=156.25MHz

RMS Phase Jitter (12kHz to 20MHz

integration range) differential output, VDDO

= 3.465V, 25MHz crystal, 156.25MHz

output frequency

OUT0=25MHz

OUT1=100MHz

0.75

75

1.5

ps

OUT2=125MHz

OUT3=156.25MHz

Skew between the same frequencies, with

outputs using the same driver format and

phase delay set to 0 ns.

t7

Output Skew

t8 ³

t9 ⁴

Lock Time

PLL lock time from power-up

10

3

20

4

ms

PLL lock time from shutdown mode

1. Practical lower frequency is determined by loop filter settings.

2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.

3. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.

4. Actual PLL lock time depends on the loop configuration.

5. Duty Cycle is only guaranteed at max slew rate settings.

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Table 20: PCI Express Jitter Specifications (V

= 3.3V +5% or 2.5V +5%, T = -40°C to +85°C)

A

DDO

Symbol

Parameter

Conditions

Min Typ Max PCIe Industry Units Notes

Specification

t_J

ƒ = 100MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

30

86

ps

1,4

Phase Jitter

Peak-to-Peak

(PCIe Gen1)

t_{REFCLK_HF_RMS}

(PCIe Gen2)

ƒ = 100MHz, 25MHz Crystal Input

Phase Jitter RMS High Band: 1.5MHz - Nyquist (clock

frequency/2)

2.56

3.10

ps

2,4

t_{REFCLK_LF_RMS}

(PCIe Gen2)

ƒ = 100MHz, 25MHz Crystal Input

Phase Jitter RMS

0.27

0.8

3.0

1.0

ps

2,4

3,4

Low Band: 10kHz - 1.5MHz

t_{REFCLK_RMS}

(PCIe Gen3)

ƒ = 100MHz, 25MHz Crystal Input

Phase Jitter RMS

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test

socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these

conditions.

1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.

2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results

for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t

Band).

(High Band) and 3.0ps RMS for t

(Low

REFCLK_HF_RMS

REFCLK_LF_RMS

3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10 Nov, 2010

specification, and is subject to change pending the final release version of the specification.

4. This parameter is guaranteed by characterization. Not tested in production.

Table 21: Jitter Specifications ^1,2,3

(VDDx = 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)

Parameter

Symbol

J_GbE

Test Condition

Crystal in = 25 MHz, All CLKn at 125 MHz⁵

Total Jitter⁶

RMS Jitter⁶, 10 kHz to 1.5MHz

RMS Jitter⁶, 1.5MHz to 50MHz

RMS Jitter⁶

Min

Typ

0.79

0.32

9.1

Max

0.95

0.5

12

Unit

ps

GbE Random Jitter (12 kHz–20 MHz)⁴

GbE Random Jitter (1.875–20 MHz)

PCI Express 1.1 Common Clocked

-

R_JGbE

ps

0.1

0.3

1.1

0.4

ps

PCI Express 2.1 Common Clocked

PCI Express 3.0 Common Clocked

0.9

ps

0.2

ps

Notes:

¹All measurements w ith Spread Spectrum Off.

²For best jitter performance, keep the single ended clock input slew rates at more than 1.0 V/ns and the differential clock input slew rates more than 0.3 V/ns.

³All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there is the potential that the output jitter may increase

due to the nature of single-ended outputs. If your configuration implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact

IDT for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS outputs have little to no effect upon jitter.

⁴DJ for PCI and GbEis < 5 ps pp.

⁵Output FOD in Integer mode.

⁶All output clocks 100 MHz HCSL format. Jitter is from the PCIEjitter filter combination that produces the highest jitter. Jitter is measured w ith the Intel Clock Jitter Tool,

Ver. 1.6.6.

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Table 22: Spread Spectrum Generation Specifications

Symbol

Parameter

Output Frequency

Mod Frequency

Spread Value

Description

Min Typ Max

Unit

MHz

kHz

Output Frequency Range

Modulation Frequency

f

5

300

OUT

f

30 to 63

MOD

Amount of Spread Value (programmable) – center spread

Amount of Spread Value (programmable) – down spread

f

±0.25% to ±2.5%

-0.5% to -5%

%f

OUT

SPREAD

Test Circuits and Loads

V_DDOx

V_DDD

V_DDA

OUTx

CLK_OUT

0.1µF

C_L

GND

HCSL Differential Output Test Load

Zo=100ohm differential

33

2pF

33

50

HCSL Output

Test Circuits and Loads for Outputs

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OCTOBER 30, 2017

5P49V5944 DATASHEET

Phase Noise Plots

NOTE: OUT1 = 100MHz HCSL, OUT2 = 156.25MHz; all phase noise plots with spurs on (3.3V, 25°C).

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5P49V5944 DATASHEET

5P49V5944 Application Schematic

The following figure shows an example of 5P49V5944 application schematic. Input and output terminations shown are intended as examples

only and may not represent the exact user configuration. In this example, the device is operated at V_DDD,V_DDA= 3.3V. The decoupling

capacitors should be located as close as possible to the power pin. A 12pF parallel resonant 8MHz to 40MHz crystal is used in this example.

Different crystal frequencies may be used. The C1 = C2 = 5pF are recommended for frequency accuracy. If different crystal types are used,

please consult IDT for recommendations. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy.

As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power

supply isolation is required. 5P49V5944 provides separate power supplies to isolate any high switching noise from coupling into the internal

PLL.

In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB

as close to the power pins as possible. If space is limited, the 0.1µf capacitor in each power pin filter should be placed on the device side. The

other components can be on the opposite side of the PCB.

Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter

performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a

specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be

adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests

adding bulk capacitance in the local area of all devices.

The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables

in the datasheet to ensure the logic control inputs are properly set.

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5P49V5944 DATASHEET

Overdriving the XIN/REF Interface

LVCMOS Driver

The XIN/REF input can be overdriven by an LVCMOS driver

or by one side of a differential driver through an AC coupling

capacitor. The XOUT pin can be left floating. The amplitude of

the input signal should be between 500mV and 1.2V and the

slew rate should not be less than 0.2V/ns. Figure General

Diagram for LVCMOS Driver to XTAL Input Interface shows an

example of the interface diagram for a LVCMOS driver.

This configuration has three properties; the total output

impedance of Ro and Rs matches the 50 transmission line

impedance, the Vrx voltage is generated at the CLKIN inputs

which maintains the LVCMOS driver voltage level across the

transmission line for best S/N and the R1–R2 voltage divider

values ensure that the clock level at XIN is less than the

maximum value of 1.2V.

VDD

XOUT

C3

Ro

Rs

Zo = 50 Ohm

R1

V_XIN

XIN / REF

Ro + Rs

LVCMOS

=

50 ohms

0. 1 uF

R2

General Diagram for LVCMOS Driver to XTAL Input Interface

Table 23 Nominal Voltage Divider Values vs LVCMOS VDD for

XIN shows resistor values that ensure the maximum drive

level for the XIN/REF port is not exceeded for all combinations

of 5% tolerance on the driver VDD, the VersaClock VDDAand

5% resistor tolerances. The values of the resistors can be

adjusted to reduce the loading for slower and weaker

LVCMOS driver by increasing the voltage divider attenuation

as long as the minimum drive level is maintained over all

tolerances. To assist this assessment, the total load on the

driver is included in the table.

Table 23: Nominal Voltage Divider Values vs LVCMOS VDD for XIN

LVCMOS Driver VDD Ro + Rs

R1

130

100

62

R2

75

V_XIN (peak)

Ro + Rs + R1 + R2

3.3

2.5

1.8

50.0

0.97

1.00

0.97

255

250

242

100

130

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5P49V5944 DATASHEET

LVPECL Driver

Figure General Diagram for LVPECL Driver to XTAL Input

Interface shows an example of the interface diagram for a

+3.3V LVPECL driver. This is a standard LVPECL termination

with one side of the driver feeding the XIN/REF input. It is

recommended that all components in the schematics be

placed in the layout; though some components might not be

used, they can be utilized for debugging purposes. The

datasheet specifications are characterized and guaranteed by

using a quartz crystal as the input. If the driver is 2.5V

LVPECL, the only change necessary is to use the appropriate

value of R3.

XOUT

C1

Zo = 50 Ohm

XIN / REF

0. 1 uF

Zo = 50 Ohm

R1

50

R2

50

+3.3V LVPECL Dr iv er

R3

50

General Diagram for +3.3V LVPECL Driver to XTAL Input Interface

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5P49V5944 DATASHEET

LVDS Driver Termination

For a general LVDS interface, the recommended value for the

common mode noise. The capacitor value should be

approximately 50pF. In addition, since these outputs are LVDS

compatible, the input receiver's amplitude and common-mode

input range should be verified for compatibility with the IDT

LVDS output. If using a non-standard termination, it is

recommended to contact IDT and confirm that the termination

will function as intended. For example, the LVDS outputs

cannot be AC coupled by placing capacitors between the

LVDS outputs and the 100 shunt load. If AC coupling is

required, the coupling caps must be placed between the 100

shunt termination and the receiver. In this manner the

termination of the LVDS output remains DC coupled.

termination impedance (Z ) is between 90. and 132. The

T

actual value should be selected to match the differential

impedance (Zo) of your transmission line. A typical

point-to-point LVDS design uses a 100 parallel resistor at the

receiver and a 100. differential transmission-line

environment. In order to avoid any transmission-line reflection

issues, the components should be surface mounted and must

be placed as close to the receiver as possible. The standard

termination schematic as shown in figure Standard

Termination or the termination of figure Optional Termination

can be used, which uses a center tap capacitance to help filter

Z_O Z_T

LVDS

Z_T

LVDS

Driver

Receiver

Standard Termination

Z_T

2

Z_O Z_T

LVDS

Driver

LVDS

Receiver

Z_T

2

C

Optional Termination

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5P49V5944 DATASHEET

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination

for LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs generate ECL/LVPECL compatible

outputs. Therefore, terminating resistors (DC current path to

ground) or current sources must be used for functionality.

These outputs are designed to drive 50 transmission lines.

Matched impedance techniques should be used to maximize

operating frequency and minimize signal distortion. The figure

below show two different layouts which are recommended

only as guidelines. Other suitable clock layouts may exist and

it would be recommended that the board designers simulate

to guarantee compatibility across all printed circuit and clock

component process variations.

3.3V

Zo=50ohm

+

-

LVPECL

Input

R1

50ohm

R2

50ohm

RTT

50ohm

3.3V LVPECL Output Termination (1)

3.3V

R3

R4

125ohm

Zo=50ohm

+

-

Zo=50ohm

Input

LVPECL

R1

84ohm

R2

84ohm

3.3V LVPECL Output Termination (2)

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5P49V5944 DATASHEET

Termination for 2.5V LVPECL Outputs

Figures 2.5V LVPECL Driver Termination Example (1) and (2)

show examples of termination for 2.5V LVPECL driver. These

terminations are equivalent to terminating 50 to V

– 2V.

DDO

For V

= 2.5V, the V

– 2V is very close to ground level.

DDO

The R3 in Figure 2.5V LVPECL Driver Termination Example

(3) can be eliminated and the termination is shown in example

(2).

V_DDO= 2.5V

2.5V

V_DDO= 2.5V

Zo=50ohm

2.5V

R1

250ohm

R3

250ohm

+

-

Zo=50ohm

+

-

2.5V LVPECL

Driver

Zo=50ohm

R1

50ohm

R2

50ohm

2.5V LVPECL

Driver

R2

62.5ohm

R4

62.5ohm

R3

18ohm

2.5V LVPECL Driver Termination Example (3)

2.5V LVPECL Driver Termination Example (1)

V_DDO= 2.5V

2.5V

Zo=50ohm

+

Zo=50ohm

-

2.5V LVPECL

R1

50ohm

R2

50ohm

Driver

2.5V LVPECL Driver Termination Example (2)

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5P49V5944 DATASHEET

PCI Express Application Note

For PCI Express Gen2, two transfer functions are defined with 2

evaluation ranges and the final jitter number is reported in RMS. The

two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz

(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the

individual transfer functions as well as the overall transfer function Ht.

PCI Express jitter analysis methodology models the system

response to reference clock jitter. The block diagram below

shows the most frequently used Common Clock Architecture

in which a copy of the reference clock is provided to both ends

of the PCI Express Link.

In the jitter analysis, the transmit (Tx) and receive (Rx) serdes

PLLs are modeled as well as the phase interpolator in the

receiver. These transfer functions are called H1, H2, and H3

respectively. The overall system transfer function at the

receiver is:

Hts = H3s  H1s – H2s

The jitter spectrum seen by the receiver is the result of

applying this system transfer function to the clock spectrum

X(s) and is:

Ys = Xs  H3s  H1s – H2s

In order to generate time domain jitter numbers, an inverse

Fourier Transform is performed on X(s) × H3(s) × [H1(s) -

H2(s)].

PCIe Gen2A Magnitude of Transfer Function

PCI Express Common Clock Architecture

For PCI Express Gen 1, one transfer function is defined and the

evaluation is performed over the entire spectrum: DC to Nyquist (e.g

for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is

reported in peak-peak.

PCIe Gen2B Magnitude of Transfer Function

For PCI Express Gen 3, one transfer function is defined and the

evaluation is performed over the entire spectrum. The transfer

function parameters are different from Gen 1 and the jitter result is

reported in RMS.

PCIe Gen1 Magnitude of Transfer Function

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5P49V5944 DATASHEET

PCIe Gen3 Magnitude of Transfer Function

For a more thorough overview of PCI Express jitter analysis

methodology, please refer to IDT Application Note PCI Express

Reference Clock Requirements.

Marking Diagram

ddd

5944B

YW**$

1. “ddd” denotes the dash code.

2. Line 2: truncated part number.

3. “YW” is the last digit of the year and week that the part was assembled.

4. “**” denotes sequential lot number.

5. “$” denotes mark code.

PROGRAMMABLE CLOCK GENERATOR

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OCTOBER 30, 2017

5P49V5944 DATASHEET

Package Drawings (3 x 3 mm 20-VFQFPN)

OCTOBER 30, 2017

29

PROGRAMMABLE CLOCK GENERATOR

5P49V5944 DATASHEET

Package Drawings (3 x 3 mm 20-VFQFPN), cont.

PROGRAMMABLE CLOCK GENERATOR

30

OCTOBER 30, 2017

Ordering Information

Part / Order Number

5P49V5944BdddNDGI

5P49V5944BdddNDGI8

Marking

see page 28

Shipping Packaging

Trays

Package

3 × 3 mm 20-VFQFPN

Temperature

-40° to +85C

Tape and Reel

Note: “ddd” denotes the dash code.

“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.

Revision History

Date

Description of Change

October 30, 2017

March 3, 2017

February 24, 2017

Updated Phase Noise plot diagrams.

Updated package outline drawings and legal disclaimer.

1. Added “Output Alignment” section.

2. Update “Output Divides” section.

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.idt.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without

notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed

in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any

particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-

lectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of

5P49V5944 OCTOBER 30, 2017

31

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