MAX20034
Automotive High-Efficiency 2.2MHz, 36V, Dual Buck
Controller with 17μA Quiescent Current
Light-Load Efficiency Skip Mode (V
= 0V)
MOSFET Gate Drivers (DH_ and DL_)
FSYNC
Drive FSYNC low to enable skip mode. In skip mode, the
IC stops switching until the FB_ voltage drops below the
reference voltage. Once the FB_ voltage has dropped
below the reference voltage, the IC begins switching until
the inductor current reaches 30% (skip threshold) of the
maximum current defined by the inductor DCR or output
shunt resistor.
The DH_ high-side n-channel MOSFET drivers are
powered from capacitors at BST_, while the low-side
drivers (DL_) are powered by the 5V linear regulator
(BIAS). On each channel, a shoot-through protection
circuit monitors the gate-to-source voltage of the external
MOSFETs to prevent a MOSFET from turning on until the
complementary switch is fully off. There must be a low-
resistance, low-inductance path from the DL_ and DH_
drivers to the MOSFET gates for the protection circuits to
work properly. Follow the instructions listed to provide the
necessary low-resistance and low-inductance path:
Forced-PWM Mode (V
= High)
FSYNC
Driving FSYNC high prevents the IC from entering skip
mode by disabling the zero-crossing detection of the induc-
tor current. This forces the low-side gate-driver waveform
to constantly be the complement of the high-side gate-
driver waveform, so the inductor current reverses at light
loads and discharges the output capacitor. The benefit
of forced-PWM (FPWM) mode is to keep the switching
frequency constant under all load conditions; however,
forced-frequency operation diverts a considerable amount
of the output current to PGND, reducing the efficiency
under light-load conditions.
● Use very short, wide traces (50 mils to 100 mils wide
if the MOSFET is 1in from the driver).
● It may be necessary to decrease the slew rate for the
gate drivers to reduce switching noise or to compen-
sate for low-gate-charge capacitors. For the low-side
drivers, use 1nF to 5nF gate capacitors from DL_ to
PGND, and for the high-side drivers, connect a small
5Ω to 10Ω resistor between BST_ and the bootstrap
capacitor.
FPWM mode is useful for improving load-transient
response and eliminating unknown frequency harmonics
that can interfere with AM radio bands.
Note: Gate drivers must be protected during shutdown,
at the absence of the supply voltage (V
= 0V) when
BIAS
the gate is pulled high either capacitively or by the leak-
age path on the PCB; therefore, external-gate pulldown
resistors are needed to prevent making a direct path from
Maximum Duty-Cycle Operation
The IC has a maximum duty cycle of 97% (min). The inter-
nal logic of the IC looks for approximately 10 consecutive
high-side FET-on pulses and decides to turn on the low-
side FET for 150ns (typ) every 12μs. The input voltage at
which the IC enters dropout changes depending on the
input voltage, output voltage, switching frequency, load
current, and the efficiency of the design. The input voltage
at which the IC enters dropout can be approximated as:
V
BAT
to PGND.
High-Side Gate-Driver Supply (BST_)
The high-side MOSFET is turned on by closing an inter-
nal switch between BST_ and DH_ and transferring the
bootstrap capacitor’s (at BST_) charge to the gate of the
high-side MOSFET. This charge refreshes when the high-
side MOSFET turns off and the LX_ voltage drops down to
ground potential, taking the negative terminal of the capaci-
tor to the same potential. At this time, the bootstrap diode
recharges the positive terminal of the bootstrap capacitor.
V
OUT_
= [V
+ (I
x R
)]/0.97
OUT_
OUT_
ON_H
Note: The above equation does not take into account
the efficiency and switching frequency, but is a good first-
order approximation. Use the R
the data sheet of the high-side MOSFET used.
(max) number from
ON_H
The selected n-channel high-side MOSFET determines the
appropriate boost capacitance values (C
in the Typical
BST_
Operating Circuit) according to the following equation:
Spread Spectrum
Q
G
The IC features enhanced EMI performance, which per-
forms ±6% dithering of the switching frequency to reduce
peak emission noise at the clock frequency and its har-
monics, making it easier to meet stringent emission limits.
C
=
BST_
∆V
BST_
where Q is the total gate charge of the high-side
G
MOSFET and ΔV
on the high-side MOSFET driver after turn-on. Choose
is the voltage variation allowed
BST_
When using an external clock source (i.e., driving the
FSYNC input with an external clock), spread spectrum is
disabled.
ΔV such that the available gate-drive voltage is not
BST_
significantly degraded (e.g., ΔV
= 100mV to 300mV)
BST_
when determining C
.
BST_
The boost capacitor should be a low-ESR ceramic
capacitor. A minimum value of 100nF works in most cases.
Maxim Integrated
│ 13
www.maximintegrated.com