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®

VersaClock 3S Programmable

5L35021

Datasheet

Clock Generator

Description

Features

The 5L35021 is a member of the VersaClock 3S programmable

clock generator family with 1.8V operation voltage, and is

designed for industrial, consumer, and PCI Express applications.

The device features a 3 PLL architecture design; each PLL is

individually programmable and allowing up to 6 unique frequency

outputs.

▪ Configurable OE pin function as OE, PD#, PPS or DFC control

function

▪ Configurable PLL bandwidth; minimizes jitter peaking

▪ PPS: Proactive Power Saving features save power during the

end device power down mode

▪ PPB: Performance Power Balancing feature allows minimum

The 5L35021 has built-in features such as Proactive Power

Saving (PPS), Performance-Power Balancing (PPB), Overshoot

Reduction Technology (ORT) and extreme low power DCO. An

internal OTP memory allows the user to store the configuration in

the device without programming after power up, then program the

5L35021 again through the I²C interface.

power consumption based on required performance

▪ DFC: Dynamic Frequency Control feature allows user to

dynamically switch between and up to 4 different frequencies

smoothly

▪ Spread spectrum clock to lower system EMI

▪ I²C interface

The device has programmable VCO and PLL source selection,

allowing power-performance optimization based on the application

requirements.

▪ Suspend Mode, featuring RTC clock only when system goes

into low-power operation modes

Output Features

▪ 2 DIFF outputs with configurable LPHSCL, LVCMOS output

Typical Applications

▪ Embedded computing devices

pairs: 1MHz–250MHz (125MHz with LVCMOS mode)

▪ Consumer application crystal replacements

▪ SmartDevice, Handheld, and Consumer applications

▪ 1 LVCMOS output: 1MHz–125MHz

▪ LVPECL, LVDS, CML and SSTL logic can be easily supported

with the LP-HCSL outputs. See application note AN-891 for

alternate terminations

Key Specifications

▪ PCIe Gen1/2/3 compliant

▪ Maximum of 5 LVCMOS outputs as REF + 3 × SE + 2 ×

DIFF_T/C as LVCMOS

▪ Typical 1.5ps rms jitter integer range: 12kHz–20MHz

▪ Typical ultra-power-down current 50μA

▪ < 2μA RTC clock in Suspend Mode operation

▪ Low-power 32.768kHz clock supported for SE1 output

Block Diagram

CLKIN/X1

OSC

X2

VDDDIFF 1

DIFF1

Programmable

Load Capacitor

DIFF1B

PLL1

VDDDIFF 2

SEL_DFC/ SCL_DFC1

SDA_DFC0

Mux

&

Divider

DIFF2

PLL2

PLL3

DIFF2B

Calibration

VDDSE1

SE1

VDD18

VDDA

VBAT

OE1

32.768K

DCO

1

November 29, 2017

5L35021 Datasheet

Pin Assignments

Figure 1. Pin Assignments for 3 x 3 mm 20-VFQFPN Package – Top View

19

18

17

16

20

1

2

3

4

5

15

14

13

12

11

VDDA

SDA_DFCO

DIFF1

DIFF1B

VDDDIFF1

OE1

5L35021

SEL_DFC/SCL_DFC1

CLKIN/X2

CLKINB/X1

SE1

6

7

8

9

10

3 x 3 mm 20-QFN

Pin Descriptions

Table 1. Pin Descriptions

Number

Name

Type

Description

1

2

V_DDA

Power

I/O

V_DD1.8V

SDA_DFC0

I²C data pin. The pin can be DFC0 function by pin 3 SEL_DFC power-on latch status.

I²C CLK pin.

SEL_DFC/

SCL_DFC1

SEL_DFC is a latch input pin during the power-up.

High on power-on: I²C mode as SCLK function.

Low on power-on: pin 3 SCL and pin 2 SDA as DFC function control pins.

3

Input

4

5

CLKIN/X2

CLKINB/X1

V_BAT

I/O

Crystal oscillator interface output or differential clock input pin (CLKIN).

Crystal oscillator interface input or differential clock input pin (CLKINB).

Power supply pin for 32.768kHz DCO; usually connect to coin cell battery, 1.8V.

Connect to ground.

Input

6

Power

Output

7

V_SS

8

V_DD18

V_DD1.8V.

9

V_SSSE1

V_DDSE1

SE1

Connect to ground.

10

11

Output power supply. Connect to 1.8V. Sets output voltage levels for SE1.

Output clock SE1.

OE1’s function selected from OTP pre-programmed register bits.

OE1 pull to 6.5V when burn OTP registers.

Refer to OE Pin Functions table for details.

12

13

OE1

Input

V_DDDIFF1

Power

Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF1.

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5L35021 Datasheet

Table 1. Pin Descriptions (Cont.)

Number

Name

Type

Description

Differential clock output 1_Complement; can be OTP pre-programmed to

LVCMOS/LPHCSL output type.

14

DIFF1B

Output

Differential clock output 1_True; can be OTP pre-programmed to LVCMOS/LPHCSL

output type.

15

DIFF1

Output

16

17

V_SSDIFF1

V_DDDIFF2

Power

Connect to ground.

Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF2.

Differential clock output 2_Complement; can be OTP pre-programmed to

LVCMOS/LPHCSL output type.

18

DIFF2B

DIFF2

Output

Differential clock output 2_True; can be OTP pre-programmed to LVCMOS/LPHCSL

output type.

19

20

V_SSDIFF2

EPAD

Power

Connect to ground.

Connect to ground pad.

Detailed Block Diagram

VDDDIFF2

DIV1/REF

DIV3

DIV

1

OSC

DIFF2

DIFF2B

MUX

CLKINB/X1

VDDDIFF1

PLL1

PLL2

DIV1/REF

DIV3

CLKIN/X2

DIV

2

DIFF1

DIFF1B

DIV

3

VBAT

Power

Monitor

MUX

VDD18

DIV

4

POR

VDDA

VSS

DIV

5

MUX

PLL3

DIV4/REF

DIV5

32K

OE1

SE1

VDDSE1

Calibration

MUX

32.768K

DCO

SCL_DFC1

SDA_DFC0

Overshot Reduction

(ORT)

I²C Engine

Dynamic Frequency Control Logic (DFC)

OTP memory (1 configuration)

Proactive Power Saving Logic (PPS)

Timer

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November 29, 2017

5L35021 Datasheet

Pow er Group¹

Table 2. Power Group

Power Supply

SE

DIFF

DIV

MUX

PLL

DCO

REF

Xtal

V_DDSE1

V_DDDIFF1

V_DDDIFF2

V_DD18

SE1 ²

DIFF1

DIFF2

DIV3/4

DIV1

MUXPLL2

MUXPLL1

PLL2

PLL3

PLL1

DIV5

DCO

REF

Xtal

V_BAT

V_DDA

DIV2

¹V_BATmust be power-up earlier or same time as other V_DDs.

²V_DDSE1for non-32kHz outputs should be OFF when V_DDA/V_DD18turns OFF; V_BATmode only supports 32.768kHz outputs from SE1.

Absolute Maximum Ratings

The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the

device. Functional operation of the 5L35021 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions

may affect device reliability.

Table 3. Absolute Maximum Ratings

Item

Rating

Supply Voltage, V_DDA, V_DD18, V_DDSE,V_DDDIFF

Supply Voltage, V_BAT

1.89V

Inputs

XIN/CLKIN

0V to 1.8V voltage swing for both LVCMOS or DIFF CLK

-0.5V to V_DD18or V_DDSE

Other Inputs

x

Outputs, V_DDSEx (LVCMOS)

Outputs, IO (SDA)

-0.5V to V_DDSEx or V_DDDIFF+ 0.5V

10mA

Package Thermal Impedance, Θ_JA

Package Thermal Impedance, Θ_JC

Storage Temperature, T_STG

ESD Human Body Model

Junction Temperature

42°C/W (0mps)

41.8°C/W (0mps)

-65°C to 150°C

2000V

125°C

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5L35021 Datasheet

Recommended Operating Conditions

Table 4. Recommended Operating Conditions

Symbol

V_DDSE

V_DD18

Parameter

Minimum

Typical Maximum Units

x

Power supply voltage for supporting 1.8V outputs.

Power supply voltage for core logic functions.

1.71

1.8

1.89

V

Analog power supply voltage. Use filtered analog power supply if

available.

V_DDA

1.71

1.8

1.89

V

V_BAT

T_A

Battery power supply voltage.

1.71

-40

1.89

85

V

Operating temperature, ambient.

Maximum load capacitance (LVCMOS only).

External reference crystal.

°C

pF

C_{LOAD_OUT}

5

8

1

40

F_IN

MHz

ms

External reference clock CLKIN, CLKINB.

125

Power up time for all V_DDs to reach minimum specified voltage (power

ramps must be monotonic).

t_PU

0.05

3

Crystal Characteristics

Table 5. Crystal Characteristics

Parameter

Conditions

Minimum

Typical

Maximum Units

Mode of Oscillation

—

Fundamental

Frequency

8

40

39

MHz

Ω

Frequency when 32.768kHz DCO is used

Equivalent Series Resistance (ESR)

Shunt Capacitance

25

10

2

100

7

pF

Load Capacitance (C_L)

6

8

10

pF

Maximum Crystal Drive Level

30

100

μW

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November 29, 2017

5L35021 Datasheet

Electrical Characteristics

Supply voltage: all V_DD±5%, unless otherwise stated

1,2

Table 6. Electrical Characteristics – Current Consumption

Symbol

Parameter

Conditions

Minimum

Typical

Maximum Units

V_DD= V_DDSE= V_DD18= 1.8V; XTAL = 25MHz,

PLL2/3 off, no output, PLLs disabled.

I_DDCORE

Core Supply Current

3.4

4.8

15.3

0.8

3.2

4.1

3.5

mA

PLL1 Supply

Current

V_DD= V_DDSE= V_DD18= 1.8V; XTAL = 25MHz,

PLL2/3 off, no output, PLL1 = 600MHz.

3

I_{DD_PLL1}

I_{DD_PLL2}

I_{DD_PLL3}

12.1

0.5

2.5

3.4

2.9

PLL2 Supply

Current

V_DD= V_DDSE= V_DD18= 1.8V; XTAL = 25MHz,

PLL1/3 off, no output, PLL2 = 60MHz.

3

PLL3 Supply

Current

V_DD= V_DDSE= V_DD18= 1.8V; XTAL = 25MHz,

PLL1/2 off, no output, PLL3 = 480MHz.

LPHCSL, 125MHz, 1.8V V_DDDIFF, no load

(DIFF1,2).

LPHCSL, 100MHz, 1.8V V_DDDIFF, no load

(DIFF1,2).

Output Buffer

Supply Current

I_DDOx

LVCMOS, 8MHz, 1.8V, V_DDSE^1,2(SE1).

LVCMOS, 160MHz, 1.8V V_DDSEx ^1,2(SE1).

0.5

2.7

0.6

3.4

mA

I²C functional during power-down, just 32kHz

running (if any); DIFF outputs in LPHCSL mode

are high/low.

I²C functional during power-down, just 32kHz

running (if any); DIFF outputs in LVCMOS mode

are high/low or low/low.

I²C functional during power-down, just 32kHz

running (if any); DIFF outputs in LPHCSL mode

are low/low.

Power Down

Current – LPHCSL

3

I_DDPD

2.6

0.5

33

3.4

1

mA

μA

Power Down

Current – LVCMOS

3

I_DDPD

Ultra Power Down

Current – LPHCSL

4

I_DDUPD

65

I²C functional during power-down, just 32kHz

running (if any) – DIFF outputs in LVCMOS mode

are low/low.

Ultra Power Down

Current – LVCMOS

4

I_DDUPD

33

65

μA

Suspend Mode

I²C off in Suspend Mode. One 32kHz output

5

I_DDSUSPEND

1.4

2.1

Current – 32kHz x 1 running.

¹All output currents measured with 0.5 inch transmission line and 0pF load.

²Single CMOS driver active.

³Power-down can be controlled by PD (OE1 input pin) and/or I²C bit.

⁴Ultra Power-down must be controlled by PD (OE1 input pin).

⁵Suspend mode requires all V_DDto GND except V_DDSEn (as desired) and V_DD18

.

⁶DIFF outputs in LVCMOS mode can power-down to be high/low or low/low, depending on register 0x22<1:0>.

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5L35021 Datasheet

Table 7. Electrical Characteristics–Input Parameters

Symbol

Parameter

Input High Voltage

Conditions

Minimum

Typical

Maximum

Units

V_IH

V_IL

V_IH

V_IL

Single-ended inputs – OE pins. 0.65 x V_DDSE

V_DDSE+ 0.3

0.35 x V_DDSE

V_DDSE+ 0.3

0.35 x V_DDSE

V_DD

V

Input Low Voltage

Single-ended inputs – OE pins.

Single-ended input.

Single-ended input swing.

V_IN= GND

GND - 0.3

0.65 x V_DDSE

GND - 0.3

600

Input High Voltage – OE

Input Low Voltage – OE

V

V_SWINGInput Amplitude – CLKIN

mV

μA

I_IL

Input Leakage Low Current

Input Leakage High Current

-20

20

I_IH

V_IN= 1.89V.

-20

20

Measurement from differential

waveform.

d_TIN

Input Duty Cycle

45

55

7

%

Input capacitance (CLKIN,

CLKINB, OE, SDA, SCL, DFC1:0).

C_IN

3

pF

kΩ

Ω

R_PDR

R_OUT

Pull-down Resistor – OE pin

550

17

LVCMOS output driver impedance

(V_DDSE= 1.8V)

Table 8. DC Electrical Characteristics – LVCMOS

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

V_OH

V_OL

Output High Voltage

Output Low Voltage

I_OH= -8mA.

I_OL= 8mA.

0.7 x V_DDSE

V_DDSE

0.25 x V_DDSE

3

V

I_OZDD

Output Leakage Current Tri-state outputs, V_DDSE= 1.89V.

μA

Single-ended LVCMOS output clock

t_R/F

Output Rise/Fall Time

rise and fall time, 20% to 80% of

_DDSE1.8V.

1.0

ns

V

Table 9. Electrical Characteristics – LPHCSL Differential Outputs

Symbol

Parameter

Minimum

Typical

Maximum

Units

Notes

1,2,3,8

dV/dt

ΔdV/dt

V_MAX

Slew Rate

1

2.5

4

V/ns

%

Slew Rate Mismatch

Maximum Voltage

Minimum Voltage

Voltage Swing

20

1,2,3,8,9

1,6

-150

-300

300

0

1150

mV

V_MIN

1,6

V_SWING

V_CROSS

1,2,6

1,4,6

Crossing Voltage Value

250

400

550

7

November 29, 2017

5L35021 Datasheet

Table 9. Electrical Characteristics – LPHCSL Differential Outputs (Cont.)

Symbol

Parameter

Minimum

Typical

Maximum

Units

Notes

ΔV_CROSS

Jitter-Cy/Cy

Jitter-STJ

T_DC

Crossing Voltage Variation

Cycle to Cycle Jitter

Short Term Period Jitter

Duty Cycle

140

160

300

55

mV

ps

%

1,5,9

1,2

45

1,2

¹Guaranteed by design and characterization, not 100% tested in production.

²Measured from differential waveform.

³Slew rate is measured through the V_SWINGvoltage range centered around differential 0V. This results in a ±150mV window around differential 0V.

⁴V_CROSSis defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock

rising and Clock# falling).

⁵The total variation of all V_CROSSmeasurements in any particular system. Note that this is a subset of V_CROSSmin/max (V_CROSSabsolute) allowed.

The intent is to limit V_CROSSinduced modulation by setting ΔV_CROSSto be smaller than V_CROSSabsolute.

⁶Measured from single-ended waveform.

⁷Measured with scope averaging off, using statistics function. Variation is the difference between minimum and maximum.

⁸Scope average on.

⁹100MHz, spread off and 0.5% spread.

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November 29, 2017

5L35021 Datasheet

General AC Electrical Characteristics

V_DD= 1.8V ±5%, T_A= -40°C to +85°C; spread spectrum = off

Table 10. AC Timing Electrical Characteristics

Symbol

Parameter

Input Frequency

Conditions

Minimum Typical Maximum Units

Input frequency limit (XIN).

8

1

40

MHz

%

1

f_IN

Input frequency limit (LVCMOS to X1).

Single-ended clock output limit (LVCMOS).

Differential clock output frequency (LPHCSL).

125

600

130

900

55

1

f_OUT

Output Frequency

1

f_VCO1VCO Frequency Range of PLL1 VCO operating frequency range.

f_VCO2VCO Frequency Range of PLL2 VCO operating frequency range.

f_VCO3VCO Frequency Range of PLL3 VCO operating frequency range.

300

30

300

45

Output Duty Cycle

LVCMOS (measured at V_DDO/2).

t_ODC

Reference clock output or SE1–3 fan out

clock measured at V_DDO/2.

Output Duty Cycle – REF

40

60

%

Cycle-to-cycle jitter (peak-to-peak), multiple

output frequencies switching, differential

outputs (1.8V nominal output voltage).

50

ps

SE1 = 25MHz.

DIFF1/2 = 100MHz.

RMS phase jitter (12kHz to 20MHz integration

range) differential output, 1.8V nominal output

voltage.

t_J

Clock Jitter

25MHz crystal.

1.5

75

ps

SE1 = 12.5MHz – REF/2.

DIFF1/2 = 100MHz – PLL1.

REF = 25M.

Skew between the same frequencies, with

outputs using the same driver format.

t_SKEWOutput Skew

ps

2

t_LOCK

Lock Time

PLL/DCO lock time.

10

ms

¹Practical lower frequency is determined by loop filter settings.

²Includes loading the configuration bits from OTP to PLL registers. It does not include OTP programming/write time.

³Actual PLL lock time depends on the loop configuration.

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November 29, 2017

5L35021 Datasheet

PCI Express Jitter Specifications

V_DDDIFF= 1.8V ±5% T_A= -40°C to +85°C

Table 11. PCI Express Jitter Specifications

Industry

Minimum Typical Maximum Specification Units Notes

Symbol

Parameter

Conditions

ƒ = 100MHz/125MHz,

25MHz crystal input.

Phase Jitter

Peak-to-Peak

t_J(PCIe Gen1)

27

86

ps

1,4

Evaluation band: 0Hz –

Nyquist (clock frequency/2).

ƒ = 100MHz/125MHz,

25MHz crystal input.

t_{REFCLK_HF_RMS}Phase Jitter

(PCIe Gen2) RMS

1.9

0.9

0.5

3.10

3.0

ps

2,4

3,4

High band: 1.5MHz –

Nyquist (clock frequency/2).

ƒ = 100MHz/125MHz,

25MHz crystal input.

t_{REFCLK_LF_RMS}Phase Jitter

(PCIe Gen2)

RMS

Low band: 10kHz – 1.5MHz.

ƒ = 100MHz/125MHz,

25MHz crystal input.

t_{REFCLK_RMS}

(PCIe Gen3)

Phase Jitter

RMS

1.0

Evaluation band: 0Hz –

Nyquist (clock frequency/2).

Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been

reached under these conditions.

¹Peak-to-peak jitter after applying system transfer function for the common clock architecture. Maximum limit for PCI Express Gen1.

²RMS jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architecture and reporting the worst

case results for each evaluation band. Maximum limit for PCI Express Gen2 is 3.1ps RMS for t_{REFCLK_HF_RMS}(high band) and 3.0ps RMS for

t_{REFCLK_LF_RMS}(low band).

³RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10

Nov. 2010 specification, and is subject to change pending the final release version of the specification.

⁴This parameter is guaranteed by characterization. Not tested in production.

I²C Bus Characteristics

Table 12. I²C Bus DC Characteristics

Symbol

Parameter

Input High Level

Conditions

Minimum

Typical

Maximum

Units

V_IH

V_IL

0.7 × V_DD18

V

Input Low Level

0.3 × V_DD18

V_HYS

I_IN

Hysteresis of Inputs

Input Leakage Current

Output Low Voltage

0.05 × V_DD18

V

±1

μA

V

V_OL

I_OL= 3mA.

0.4

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November 29, 2017

5L35021 Datasheet

Table 13. I²C Bus AC Characteristics

Symbol

Parameter

Conditions

Minimum

Typical

Maximum Units

F_SCLK

t_BUF

Serial Clock Frequency (SCL)

Bus Free Time between STOP and START

Setup Time, START

100

400

kHz

μs

ns

μs

pF

ns

μs

1.3

0.6

100

0

t_SU:START

t_HD:START

t_SU:DATA

t_HD:DATA

t_OVD

Hold Time, START

Setup Time, data input (SDA)

Hold Time, data input (SDA) ¹

Output Data Valid from Clock

Capacitive Load for Each Bus Line

Rise Time, data and clock (SDA, SCL)

Fall Time, data and clock (SDA, SCL)

High Time, clock (SCL)

0.9

400

300

C_B

t_R

20 + 0.1 × C_B

t_F

20 + 0.1 × C_B

t_HIGH

0.6

1.3

0.6

t_LOW

Low Time, clock (SCL)

t_SU:STOP

Setup Time, STOP

¹A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V_IH(MIN)of the SCL signal) to bridge the undefined

region of the falling edge of SCL.

Glossary of Features

Table 14. Glossary of Features

Term

DFC

Function Description

Apply to

Dynamic Frequency Control; from selected PLL to support four VCO frequencies; means two different

output frequencies by assigned H/W pin state changes (H-L or L-H) needs to have frequency change

Glitch-Free function in order to not crash application system.

PLL2

Overshot Reduction; when the DFC dynamic frequency change is functional, the VCO changes

frequencies smoothly to target frequency without overshoot or undershoot.

ORT

PLL2

OE1

Output enable function; each output can be controlled by assigned OE pin and the dedicated OE pin can

be OTP programmable as global Power Down function (PD#) or Output Enable (OE) or Proactive Power

Saving function (PPS) or RESET pin function.

OE

SS

Spread spectrum clock.

PLL1/PLL2

LVCMOS

Slew Rate LVCMOS outputs with slew rate control – slow and fast.

Proactive Power Saving; utilize OE pin as monitor pin for end device X2 clock status. See PPS Function

description for details.

PPS

SE1

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November 29, 2017

5L35021 Datasheet

Device Features and Functions

Performance Pow er Balancing

VersaClock 3S features Performance Power Balancing with three individual programmable PLL designs and provides a balance between

performance and power consumption.

The device can operate within single-digit mA low-power operation or support high-performance requirements such as PCIe Gen 3 with

additional power.

In order to satisfy system trade-off, outputs have the option to route from different PLL/input sources.

Table 15. Pow er Saving Modes Summary

Power Mode

External Condition

Internal Operating Condition

Core Current Consumption

Power-down Mode

Ultra-power-down

V_DDall connected.

All off, I²C still active.

All off.

2mA

V

_DDall connected.

50μA

All off, only DCO on with RTC

(32.768kHz) output only.

Suspend Mode

Only V_BATconnected.

2μA

Table 16. Output Source

Outputs

Source

SE1

DIFF1

DIFF2

Xtal REF

32.768kHz

PLL1

Xtal REF

32.768kHz

PLL1

PLL2

PLL3

PLL1

PLL2

PLL3

PLL2

PLL3

Table 17. SE1 Output

SE1

B36<4>

B36<3>

B31<1>

B29<3>

From 32kHz

0

1

0

1

0

1

0

1

From PLL3 + Divider 5

From PLL2 + Divider 4

From REF + Divider 4

Table 18. DIFF1 Output

DIFF1

B34<7>

B0<3>

From PLL1 + Divider 1

From PLL2 + Divider 3

From REF + Divider 1

0

1

0

1

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November 29, 2017

5L35021 Datasheet

Table 19. DIFF2 Output

DIFF2

B35<7>

B0<3>

From PLL1 + Divider 1

From PLL2 + Divider 3

From REF + Divider 1

0

1

0

1

DFC – Dynamic Frequency Control

▪ OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL2.

▪ ORT (over shoot reduction) function will be applied automatically during the VCO frequency change.

▪ Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection.

Figure 2. DFC Function Block Diagram

M divider

PLL2

OUT DIV

Selector

N divider

00

N divider

01

10

11

N divider

DFC1:0

OTP/I2C

Table 20. DFC Function Priority

OE1_fun_sel

(W30[6:5])

*OE3_fun_sel

(W30[3:2])

DFC_EN bit (W32[4])

SCL_DFC1

DFC[1:0]

Notes

0

1

x

0

DFC disable

11 (DFC)

00–10 (DFC)

[0,OE1]

One pin DFC–OE1

Two pin DFC–OE3,

OE1

1

11 (DFC)

00–10

11 (DFC)

11

x

0

[OE3,OE1]

Not permitted

Not supported

I²C pin as DFC

[SCL_DFC1,

SDA_DFC0]

00–10

control pins mode

I²C control DFC

mode

1

00–10

1

W30[1:0]

* The 5L35021 has only OE1 pin for DFC function hardware pin selection. For OE1/OE3 two pins DFC control, use 5L35023 24-QFN

package device.

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November 29, 2017

5L35021 Datasheet

DFC Function Programming

▪ Register B63b3:2 selects DFC00–DFC11 configuration.

▪ Byte16–19 are the registers for PLL2 VCO setting, based on B63b3:2 configuration selection, the data write to B16–19 will be stored

in selected configuration OTP memory.

▪ Refer to DFC Function Priority table. Select proper control pin(s) to activate DFC function.

▪ Note the DFC function can also be controlled by I²C access.

PPS – Proactive Power Saving Function

PPS (Proactive Power Saving) is an IDT patented unique design for the clock generator that proactively detects end device power down

state and then switches output clocks between normal operation clock frequency and low power mode 32kHz clock that only consumes

<2μA current. The system could save power when the device goes into power down or sleep mode. The PPS function diagram is shown

as below.

Figure 3. PPS Function Block Diagram

PPS

Control

Logic

Power

Down

Control

I²C

&

Logic

Low

Power

DCO

XOUT

XIN

Xtal

Oscillator

Logic

Xtal

Oscillator

PLL

MHz / kHz

Switching

Figure 4. PPS Assertion/Deassertion Timing Chart

3rd cycle

2nd cycle

1st cycle

PPS assertion

MHz clock

2nd cycle

32k clocks

PPS setting (1-2-4-8)

1st cycle

PPS deassertion

32k clocks

MHz clock

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November 29, 2017

5L35021 Datasheet

PPS Function Programming

1. Refer to the OE Pin Functions table to have the proper PPS function selected for OE pin(s). Note that the register default is set to

Output enable (OE) function for OE pins.

2. Have proper setup to Byte 30 and 32 for OE1–OE3 function selection; for PPS function, select 10 to control register bits.

Timer Function Description

1. The timer function can be used together with the DFC -Dynamic Frequency Control function or with another PLL frequency

programming.

2. The timer provides 4 different delay times as 0.5 sec – 1 sec – 2 sec – 4 sec by two bits selection.

3. The timeout flag will be set when timer times out and the flag can be cleared by writing 0 to timer enable bit.

4. When timer times out, RESET pin can generate a 250ms pulse signal if RESET control bit is enabled.

5. When timer times out, DFC stage will switch back to DFC00 setting if DFC function is enabled and DFC function will be disabled after

RESET.

Figure 5. Timer Functions

Select delay time 0.5 - 4.0 seconds and enable timer

Program New VCO frequency or enable DFC

System functional check

Disable Timer

Timer continue if system is not able to stop timer

Timeout Flag set and generate RESET pulse

OE Pin Function

The OE pin in the 5L35021 have multiple functions. The OE pins can be configured as output enable control (OE) or chip power-down

control (PD#) or Proactive Power Saving function (PPS). Furthermore, the OE pins can be configured as a single Dynamic Frequency

Control (DFC), or the RESET out function that is associated with the Timer function.

Table 21. OE Pin Functions

Function

OE1

SE Output Enable/Disable

DIFF Output Enable/Disable

Global Power Down (PD#)

Proactive Power Saving Input

DOC Control (Only PLL2)

RESET OUT

SE1 (default)

—

PD#

SE1_PPS

DFC0

—

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November 29, 2017

5L35021 Datasheet

Table 22. OE Pin Function Summary

OE Pin

Description

OE1 only control SE1 enable/disable; other outputs are not affected by this pin status.

OE1: SE1

OE1 control chip global power down (PD#) except 32.768kHz on OE1 (when 32kHz is enabled). When the

PD# pin is active low, the chip goes to lowest power down mode and all outputs are disabled except 32kHz

output and only keep 32k/Xtal calibration.

OE1: PD#

OE1: SE1_PPS

OE1: DFC0

Configure OE1 as SE1_PPS (Proactive Power Saving) function pin.

Configure OE1 as DFC0 control pin 0.

Table 23. PD# Priority

PD#

I2C_OE_EN_bit

SE1/2/3, DIFF1/DIFF2

Output

Notes

0

1

x

0

1

x

0

1

Stop

32kHz free run

Stop

Running

Crystal Input (X1/X2)

The crystal oscillators should be fundamental mode quartz crystals; overtone crystals are not suitable. Crystal frequency should be

specified for parallel resonance with 40MHz maximum.

A crystal manufacturer will calibrate its crystals to the nominal frequency with a certain load capacitance value. When the oscillator load

capacitance matches the crystal load capacitance, the oscillation frequency will be accurate as 0 PPM. When the oscillator load

capacitance is lower than the crystal load capacitance, the oscillation frequency will be higher than nominal. In order to get an accurate

oscillation frequency, the matching the oscillator load capacitance with the crystal load capacitance is required.

To set the oscillator load capacitance, 5L35021 has built-in two programmable tuning capacitors inside the chip, one at XIN and one at

XOUT. They can be adjusted independently. The value of each capacitor is composed of a fixed capacitance amount plus a variable

capacitance amount set with the XTAL[7:0] register. Adjustment of the crystal tuning capacitors allows for maximum flexibility to

accommodate crystals from various manufacturers. The range of tuning capacitor values available are in accordance with the following

table.

Table 24. Programmable Tuning Caps

Parameter

Bits

Range

Minimum (pF)

Maximum (pF)

Xtal [7:0]

4 × 2

+1 / +2 / +4 / +8pF

0

15pF

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November 29, 2017

5L35021 Datasheet

XTAL[4:0] = (XTAL CL - 7pF) *2 (Eq.1)

Equation 1 and the table of XTAL[7:0] tuning capacitor characteristics show that the parallel tuning capacitance can be set between 4.5pF

to 12.5pF with a resolution of 0.25pF.

For a crystal C_L= 8pF, where C_Lis the parallel capacity specified by the crystal vendor that sets the crystal frequency to the nominal

value. Under the assumptions that the stray capacity between the crystal leads on the circuit board is zero and that no external tuning

caps are placed on the crystal leads, then the internal parallel tuning capacity is equal to the load capacity presented to the crystal by the

device.

The internal load capacitors are true parallel-plate capacitors for ultra-linear performance. Parallel-plate capacitors were chosen to

reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature changes.

External non-linear crystal load capacitors should not be used for applications that are sensitive to absolute frequency requirements.

The 5L35023 supports spread spectrum clocks from PLL1 and PLL2; the PLL1 built-in with analog spread spectrum and PLL2 has digital

spread spectrum.

Spread Spectrum

The 5L35021 supports spread spectrum clocks from PLL1 and PLL2; the PLL1 built-in with analog spread spectrum and PLL2 has digital

spread spectrum.

Table 25. Spread Spectrum Generation Specifications

Symbol

Parameter

Description

Minimum

Typical Maximum

Units

f_OUT

f_MOD

Output Frequency

Mod Frequency

Spread Value

Output frequency range.

Modulation frequency.

1

125

MHz

kHz

30 to 63

f_SPREAD

Amount of spread value

-0.5% to -2%

% f_OUT

(programmable) – down spread.

%tolerance

Spread% Value

Variation of spread range.

15

%

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November 29, 2017

5L35021 Datasheet

Figure 6. Digital Spread Spectrum

Fvco

N 

2 * Fout

Fpfd

period



2 * Fss

N * SSamount

period

step 

Down spread or Spread off

N = Fvco/Fpfd

Center Spread

N = Nssoff + N × SSamount/2

N: include integer and fraction

Fvco: VCOs frequency

Fpfd: PLLs pfd frequency

Fss: spread modulation rate

SSamount: spread percentage

The black line is for the down spread; N will decrease to make the center frequency is lower than spread off.

The blue line is for the center spread; there is an offset put on divider ratio to make the center frequency keep same as spread off.

Example: 0.5% down spread at 32kHz modulation rate.

Suspend Mode w ith RTC Clock Only

VersaClock 3S can operate on the following two modes:

▪ Full-power mode:

— Full chip active with the most functionality and all V_DDs are connected to power supply.

▪ Low-power Suspend Mode:

— Device power-up with below sequence:

1. V_BATand all other V_DDs are powered up. V_BATramp must be earlier or same time as other V_DDs.

2. After full power up is completed, the device can go into Suspend Mode triggered by V_BATis powered and rest of the V_DDs ramped down

(ramp down time slower than 3ms).

In Suspend Mode, device will operate with a 2μA core power with only V_BATpowered up. Producing 32kHz outputs on SEx outputs (it can

be multiple copies). Operating at this state helps system in power-down, or sleep mode without losing date-time information at a very low

power budget. When system waking up, device will go back to full power mode automatically and produce outputs upon user

configuration.

When there is core power present (V_DD18and V_DDA), the device will switch DCO supply to core power to save battery.

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November 29, 2017

5L35021 Datasheet

ORT–VCO Overshoot Reduction Technology

The 5L35021 supports the VCO overshoot reduction technology (ORT) to prevent an output clock frequency spike when the device is

changing frequency on the fly or doing DFC (Dynamic Frequency Control) function. The VCO frequency changes are under control

instead of free-run to targeted frequency.

PLL Features and Descriptions

Table 26. Output 1 Divider

Output Divider bits <3:2>

Output Divider bits <1:0>

00

01

10

11

00

01

10

11

1

4

5

6

2

8

4

8

16

20

24

32

40

48

10

12

Table 27. Output 2, 4, and 5 Divider

Output Divider bits <3:2>

Output Divider bits <1:0>

00

01

10

11

00

01

10

11

1

3

2

6

4

5

12

20

40

15

25

50

5

10

20

10

Table 28. Output 3 Divider

Output Divider bits <3:2>

Output Divider bits <1:0>

00

01

10

11

00

01

10

11

1

3

2

6

4

8

12

20

40

24

40

80

5

10

20

10

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November 29, 2017

5L35021 Datasheet

Output Clock Test Conditions

Figure 7. LVCMOS Output Test Conditions

33 ohm

2 inches

2pF

LVCMOS

Figure 8. LP-HCSL Output Test Conditions

33 ohm

5 inches

33 ohm

2pF

LPHCSL

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November 29, 2017

5L35021 Datasheet

2

General I C Mode Operations

The device acts as a slave device on the I²C bus using one of the four I²C addresses (0xD0, 0xD2, 0xD4, or 0xD6) to allow multiple

devices to be used in the system. The interface accepts byte-oriented block write and block read operations. Two address bytes specify

the register address of the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from

the lowest to the highest byte (most significant bit first). Read and write block transfers can be stopped after any complete byte transfer.

During a write operation, data will not be moved into the registers until the STOP bit is received, at which point, all data received in the

block write will be written simultaneously.

For full electrical I²C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-down

resistors have a size of 100kΩ typical.

Figure 9. I²C Slave Read and Write Cycle Sequencing

Current Read

S

Dev Addr + R

A

Data 0

A

Data 1

A

Data n

Data 0

A

Abar

P

Sequential Read

S

Dev Addr + W

Reg start Addr

A

Sr

Dev Addr + R

A

Data1

A

Data n

Abar

P

Sequential Write

S

Dev Addr + W

Data 0

A

Data 1

A

Data n

A

P

Reg start Addr

S = start

from master to slave

from slave to master

Sr = repeated start

A = acknowledge

Abar = none acknowledge

P = stop

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November 29, 2017

5L35021 Datasheet

Byte 0: General Control

Byte 00h

Name

Control Function

Type

0

1

PWD

OTP memory programming

indication

OTP memory

non-programmed

OTP memory

programmed

Bit 7

OTP_Burned

R/W

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I²C_addr[1]

I²C_addr[0]

I²C address select bit 1

I²C address select bit 0

PLL1 Spread Spectrum enable

Divider 1 source clock select

PLL3 source selection

Enable CLKIN

R/W

0

00: D0 / 01: D2

10: D4 / 11: D6

PLL1_SSEN

DIV1_src_sel

PLL3_refin_sel

EN_CLKIN

disable

enable

Xtal

PLL1

Xtal

Seed (DIV2)

enable

disable

read/write

OTP_protect

OTP memory protection

write locked

Byte 1: Dash Code ID (optional)

Byte 01h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DashCode ID[7]

DashCode ID[6]

DashCode ID[5]

DashCode ID[4]

DashCode ID[3]

DashCode ID[2]

DashCode ID[1]

DashCode ID[0]

Dash code ID

R/W

—

0

Byte 2: Crystal Cap Setting

Byte 02h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Xtal_Cap[7]

Xtal_Cap[6]

Xtal_Cap[5]

Xtal_Cap[4]

Xtal_Cap[3]

Xtal_Cap[2]

Xtal_Cap[1]

Xtal_Cap[0]

Xtal cap load trimming bits

R/W

0

1

0

1

x1 x2

x4 x8

total 15pf

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November 29, 2017

5L35021 Datasheet

Byte 3: PLL3 M Divider

Byte 03h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL3_MDIV1

PLL3_MDIV2

PLL3 source clock divider

R/W

disable M DIV1 bypadd divider (/1)

disable M DIV2 bypadd divider (/2)

0

1

0

1

PLL3 M_DIV[5]

PLL3 M_DIV[4]

PLL3 M_DIV[3]

PLL3 M_DIV[2]

PLL3 M_DIV[1]

PLL3 M_DIV[0]

PLL3 reference integer divider

3–64

—

default 25

—

Byte 4: PLL3 N Divider

Byte 04h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL3 N_DIV[7]

PLL3 N_DIV[6]

PLL3 N_DIV[5]

PLL3 N_DIV[4]

PLL3 N_DIV[3]

PLL3 N_DIV[2]

PLL3 N_DIV[1]

PLL3 N_DIV[0]

PLL3 VCO feedback integer divider bit7 R/W

PLL3 VCO feedback integer divider bit6 R/W

PLL3 VCO feedback integer divider bit5 R/W

PLL3 VCO feedback integer divider bit4 R/W

PLL3 VCO feedback integer divider bit3 R/W

PLL3 VCO feedback integer divider bit2 R/W

PLL3 VCO feedback integer divider bit1 R/W

PLL3 VCO feedback integer divider bit0 R/W

1

0

12–2048, default VCO setting is

480MHz

Byte 5: PLL3 Loop Filter Setting and N Divider 10:8

Byte 05h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

PLL3_R100K

PLL3_R50K

PLL3_R25K

PLL3_R12.5K

PLL3 Loop filter resister 100kohm

PLL3 Loop filter resister 50kohm

PLL3 Loop filter resister 25kohm

PLL3 Loop filter resister 12.5kohm

R/W

bypass

plus 100kohm

plus 50kohm

plus 25kohm

plus 12.5kohm

0

1

only 6kohm

applied

Bit 3

PLL3_R6K

PLL3 Loop filter resister 6kohm

R/W

bypass

0

Bit 2

Bit 1

Bit 0

PLL3 N_DIV[10]

PLL3 N_DIV[9]

PLL3 N_DIV[8]

PLL3 VCO feedback integer divider bit10 R/W

0

1

12–2048, default VCO setting is

480MHz

PLL3 VCO feedback integer divider bit9

PLL3 VCO feedback integer divider bit8

R/W

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November 29, 2017

5L35021 Datasheet

Byte 6: PLL3 Charge Pump Control

Byte 06h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OUTDIV 3 Source

PLL3_CP_8X

PLL3_CP_4X

PLL3_CP_2X

PLL3_CP_1X

PLL3_CP_/24

PLL3_CP_/3

Output divider 3 source clock selection R/W

PLL2

—

PLL3

x8

0

1

0

1

0

PLL3 charge pump control

PLL3 SiRef current selection

R/W

—

x4

—

x2

—

x1

—

/24

/3

—

PLL3_SIREF

10μA

20μA

Formula: (iRef (10μA) × (1 + SIREF) × (1 × 1X + 2 × 2X + 4 × 4X + 8 × 8X + 16 × 16X))/((24 × /24) + (3 × /3))

Byte 7: PLL1 Control and OUTDIV5 Divider

Byte 07h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL1_MDIV_Doubler

PLL1_SIREF

PLL1 reference clock doubler

PLL1 SiRef current selection

PLL1 output Channel 2 control

PLL1 3rd Pole control

R/W

disable

10.8μA

disable

—

enable

21.6μA

enable

—

0

1

0

1

PLL1_EN_CH2

PLL1_EN_3rdpole

OUTDIV5[3]

Output divider5 control bit 3

Output divider5 control bit 2

Output divider5 control bit 1

Output divider5 control bit 0

OUTDIV5[2]

—

OUTDIV5[1]

—

OUTDIV5[0]

—

Byte 8: PLL1 M Divider

Byte 08h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL1_MDIV1

PLL1_MDIV2

PLL3 VCO reference clock divider 1

PLL3 VCO reference clock divider 2

R/W

disable M DIV1

disable M DIV2

bypass divider (/1)

bypass divider (/2)

0

1

0

1

PLL1 M_DIV[5]

PLL1 M_DIV[4]

PLL1 M_DIV[3]

PLL1 M_DIV[2]

PLL1 M_DIV[1]

PLL1 M_DIV[0]

PLL1 reference clock divider control bit 5 R/W

PLL1 reference clock divider control bit 4 R/W

PLL1 reference clock divider control bit 3 R/W

PLL1 reference clock divider control bit 2 R/W

PLL1 reference clock divider control bit 1 R/W

PLL1 reference clock divider control bit 0 R/W

3–64, default is 25

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November 29, 2017

5L35021 Datasheet

Byte 9: PLL1 VCO N Divider

Byte 09h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL1 N_DIV[7]

PLL1 N_DIV[6]

PLL1 N_DIV[5]

PLL1 N_DIV[4]

PLL1 N_DIV[3]

PLL1 N_DIV[2]

PLL1 N_DIV[1]

PLL1 N_DIV[0]

PLL1 VCO feedback divider control bit 7 R/W

PLL1 VCO feedback divider control bit 6 R/W

PLL1 VCO feedback divider control bit 5 R/W

PLL1 VCO feedback divider control bit 4 R/W

PLL1 VCO feedback divider control bit 3 R/W

PLL1 VCO feedback divider control bit 2 R/W

PLL1 VCO feedback divider control bit 1 R/W

PLL1 VCO feedback divider control bit 0 R/W

0

1

0

1

0

12–2048, default is 600

Byte 10: PLL Loop Filter and N Divider

Byte 0Ah

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL1_R100K

PLL1_R50K

PLL1_R25K

PLL1_R12.5K

PLL1_R1.0K

PLL1 Loop filter resister 100kohm

PLL1 Loop filter resister 50kohm

PLL1 Loop filter resister 25kohm

PLL1 Loop filter resister 12.5kohm

PLL1 Loop filter resister 1kohm

R/W

bypass

plus 100kohm

plus 50kohm

1

0

1

0

1

0

plus 25kohm

plus 12.5kohm

only 1.0kohm applied

PLL1 N_DIV[10] PLL1 VCO feedback integer divider bit10 R/W

PLL1 N_DIV[9]

PLL1 N_DIV[8]

PLL1 VCO feedback integer divider bit9

PLL1 VCO feedback integer divider bit8

R/W

12–2048, default is 600

Byte 11: PLL1 Charge Pump

Byte 0Bh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL1_CP_32X

PLL1_CP_16X

PLL1_CP_8X

PLL1_CP_4X

PLL1_CP_2X

PLL1_CP_1X

PLL1_CP_/24

PLL1_CP_/3

PLL1 charge pump control

R/W

—

x32

x16

x8

0

1

0

x4

x2

x1

/24

/3

25

November 29, 2017

5L35021 Datasheet

Byte 12: PLL1 Spread Spectrum Control

Byte 0Ch

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL1_SS_REFDIV23 PLL1 Spread Spectrum control - Ref divider 23 R/W

—

0

PLL1_SS_REFDIV[6] PLL1 Spread Spectrum control - Ref divider 6

PLL1_SS_REFDIV[5] PLL1 Spread Spectrum control - Ref divider 5

PLL1_SS_REFDIV[4] PLL1 Spread Spectrum control - Ref divider 4

PLL1_SS_REFDIV[3] PLL1 Spread Spectrum control - Ref divider 3

PLL1_SS_REFDIV[2] PLL1 Spread Spectrum control - Ref divider 2

PLL1_SS_REFDIV[1] PLL1 Spread Spectrum control - Ref divider 1

PLL1_SS_REFDIV[0] PLL1 Spread Spectrum control - Ref divider 0

R/W

Byte 13: PLL1 Spread Spectrum Control

Byte 0Dh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL1_SS_FBDIV[15] PLL1 Spread Spectrum - feedback divider 15 R/W

PLL1_SS_FBDIV[14] PLL1 Spread Spectrum - feedback divider 14 R/W

PLL1_SS_FBDIV[13] PLL1 Spread Spectrum - feedback divider 13 R/W

PLL1_SS_FBDIV[12] PLL1 Spread Spectrum - feedback divider 12 R/W

PLL1_SS_FBDIV[11] PLL1 Spread Spectrum - feedback divider 11 R/W

PLL1_SS_FBDIV[10] PLL1 Spread Spectrum - feedback divider 10 R/W

—

0

PLL1_SS_FBDIV[9]

PLL1_SS_FBDIV[8]

PLL1 Spread Spectrum - feedback divider 9 R/W

PLL1 Spread Spectrum - feedback divider 8 R/W

Byte 14: PLL1 Spread Spectrum Control

Byte 0Eh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL1_SS_FBDIV[7] PLL1 Spread Spectrum - feedback divider 7 R/W

PLL1_SS_FBDIV[6] PLL1 Spread Spectrum - feedback divider 6 R/W

PLL1_SS_FBDIV[5] PLL1 Spread Spectrum - feedback divider 5 R/W

PLL1_SS_FBDIV[4] PLL1 Spread Spectrum - feedback divider 4 R/W

PLL1_SS_FBDIV[3] PLL1 Spread Spectrum - feedback divider 3 R/W

PLL1_SS_FBDIV[2] PLL1 Spread Spectrum - feedback divider 2 R/W

PLL1_SS_FBDIV[1] PLL1 Spread Spectrum - feedback divider 1 R/W

PLL1_SS_FBDIV[0] PLL1 Spread Spectrum - feedback divider 0 R/W

—

0

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November 29, 2017

5L35021 Datasheet

Byte 15: Output Divider1 Control

Byte 0Fh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OUTDIV1[3]

OUTDIV1[2]

OUTDIV1[1]

OUTDIV1[0]

OUTDIV2[3]

OUTDIV2[2]

OUTDIV2[1]

OUTDIV2[0]

Output divider1 control bit 3

Output divider1 control bit 2

Output divider1 control bit 1

Output divider1 control bit 0

Output divider2 control bit 3

Output divider2 control bit 2

Output divider2 control bit 1

Output divider2 control bit 0

R/W

—

0

1

0

1

Byte 16: PLL2 Integer Feedback Divide

Byte 10h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

0

PLL2_FB_INT[10]

PLL2_FB_INT[9]

PLL2_FB_INT[8]

PLL2 feedback integer divider 10 R/W

—

PLL2 feedback integer divider 9

PLL2 feedback integer divider 8

R/W

Byte 17: PLL2 Integer Feedback Divider

Byte 11h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL2_FB_INT_DIV[7]

PLL2_FB_INT_DIV[6]

PLL2_FB_INT_DIV[5]

PLL2_FB_INT_DIV[4]

PLL2_FB_INT_DIV[3]

PLL2_FB_INT_DIV[2]

PLL2_FB_INT_DIV[1]

PLL2_FB_INT_DIV[0]

PLL2 feedback integer divider 7

PLL2 feedback integer divider 6

PLL2 feedback integer divider 5

PLL2 feedback integer divider 4

PLL2 feedback integer divider 3

PLL2 feedback integer divider 2

PLL2 feedback integer divider 1

PLL2 feedback integer divider 0

R/W

—

0

1

0

27

November 29, 2017

5L35021 Datasheet

Byte 18: PLL2 Fractional Feedback Divider

Byte 12h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL2_FB_FRC_DIV[15]

PLL2_FB_FRC_DIV[14]

PLL2_FB_FRC_DIV[13]

PLL2_FB_FRC_DIV[12]

PLL2_FB_FRC_DIV[11]

PLL2_FB_FRC_DIV[10]

PLL2_FB_FRC_DIV[9]

PLL2_FB_FRC_DIV[8]

PLL2 feedback fractional divider 15 R/W

PLL2 feedback fractional divider 14 R/W

PLL2 feedback fractional divider 13 R/W

PLL2 feedback fractional divider 12 R/W

PLL2 feedback fractional divider 11 R/W

PLL2 feedback fractional divider 10 R/W

PLL2 feedback fractional divider 9 R/W

PLL2 feedback fractional divider 8 R/W

—

0

Byte 19: PLL2 Fractional Feedback Divider

Byte 13h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL2_FB_FRC_DIV[7]

PLL2_FB_FRC_DIV[6]

PLL2_FB_FRC_DIV[5]

PLL2_FB_FRC_DIV[4]

PLL2_FB_FRC_DIV[3]

PLL2_FB_FRC_DIV[2]

PLL2_FB_FRC_DIV[1]

PLL2_FB_FRC_DIV[0]

PLL2 feedback fractional divider 7

PLL2 feedback fractional divider 6

PLL2 feedback fractional divider 5

PLL2 feedback fractional divider 4

PLL2 feedback fractional divider 3

PLL2 feedback fractional divider 2

PLL2 feedback fractional divider 1

PLL2 feedback fractional divider 0

R/W

—

0

Byte 20: PLL2 Spread Spectrum Control

Byte 14h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL2_STEP[7]

PLL2_STEP[6]

PLL2_STEP[5]

PLL2_STEP[4]

PLL2_STEP[3]

PLL2_STEP[2]

PLL2_STEP[1]

PLL2_STEP[0]

PLL2 spread step size control bit 7

PLL2 spread step size control bit 6

PLL2 spread step size control bit 5

PLL2 spread step size control bit 4

PLL2 spread step size control bit 3

PLL2 spread step size control bit 2

PLL2 spread step size control bit 1

PLL2 spread step size control bit 0

R/W

—

0

28

November 29, 2017

5L35021 Datasheet

Byte 21: PLL2 Spread Spectrum Control

Byte 15h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL2_STEP_DELTA[7] PLL2 spread step size control delta bit 7 R/W

PLL2_STEP_DELTA[6] PLL2 spread step size control delta bit 6 R/W

PLL2_STEP_DELTA[5] PLL2 spread step size control delta bit 5 R/W

PLL2_STEP_DELTA[4] PLL2 spread step size control delta bit 4 R/W

PLL2_STEP_DELTA[3] PLL2 spread step size control delta bit 3 R/W

PLL2_STEP_DELTA[2] PLL2 spread step size control delta bit 2 R/W

PLL2_STEP_DELTA[1] PLL2 spread step size control delta bit 1 R/W

PLL2_STEP_DELTA[0] PLL2 spared step size control delta bit 0 R/W

—

0

Byte 22: PLL2 Spread Spectrum Control

Byte 16h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL2_STEP[15]

PLL2_STEP[14]

PLL2_STEP[13]

PLL2_STEP[12]

PLL2_STEP[11]

PLL2_STEP[10]

PLL2_STEP[9]

PLL2_STEP[8]

PLL2 spread step size control bit 15

PLL2 spread step size control bit 14

PLL2 spread step size control bit 13

PLL2 spread step size control bit 12

PLL2 spread step size control bit 11

PLL2 spread step size control bit 10

PLL2 spread step size control bit 9

PLL2 spread step size control bit 8

R/W

—

0

Byte 23: PLL2 Period Control

Byte 17h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL2_PERIOD[7]

PLL2_PERIOD[6]

PLL2_PERIOD[5]

PLL2_PERIOD[4]

PLL2_PERIOD[3]

PLL2_PERIOD[2]

PLL2_PERIOD[1]

PLL2_PERIOD[0]

PLL2 period control bit 7

PLL2 period control bit 6

PLL2 period control bit 5

PLL2 period control bit 4

PLL2 period control bit 3

PLL2 period control bit 2

PLL2 period control bit 1

PLL2 period control bit 0

R/W

—

0

29

November 29, 2017

5L35021 Datasheet

Byte 24: PLL2 Control Register

Byte 18h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL2_PERIOD[9]

PLL2_PERIOD[8]

PLL2_SSEN

PLL2_R100K

PLL2_R50K

PLL2 period control bit 9

PLL2 period control bit 8

R/W

—

0

1

0

—

PLL2 spread spectrum enable

PLL2 Loop filter resister 100kohm

PLL2 Loop filter resister 50kohm

PLL2 Loop filter resister 25kohm

PLL2 Loop filter resister 12.5kohm

PLL2 Loop filter resister 6kohm

disable

bypass

enable

plus 100kohm

plus 50kohm

plus 25kohm

plus 12.5kohm

only 6kohm applied

—

PLL2_R25K

—

PLL2_R12.5K

PLL2_R6K

—

Byte 25: PLL2 Charge Pump Control

Byte 19h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL2_CP_16X

PLL2_CP_8X

PLL2_CP_4X

PLL2_CP_2X

PLL2_CP_1X

PLL2_CP_/24

PLL2_CP_/3

PLL2_SIREF

PLL2 charge pump control

PLL2 SiRef current selection

R/W

—

x16

x8

0

1

0

1

0

—

x4

—

x2

—

x1

—

/24

/3

—

10μA

20μA

Byte 26: PLL2 M Divider Setting

Byte 1Ah

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL2_MDIV_Doubler

PLL2_MDIV1

PLL2 reference divider - doubler

PLL2 reference divider 1

R/W

disable

enable

0

1

0

1

disable M DIV1

disable M DIV2

bypadd divider (/1)

bypadd divider (/2)

PLL2_MDIV2

PLL2 reference divider 2

PLL2_MDIV[4]

PLL2_MDIV[3]

PLL2_MDIV[2]

PLL2_MDIV[1]

PLL2_MDIV[0]

PLL2 reference divider control bit 4 R/W

PLL2 reference divider control bit 3 R/W

PLL2 reference divider control bit 2 R/W

PLL2 reference divider control bit 1 R/W

PLL2 reference divider control bit 0 R/W

3–64, default is 25

30

November 29, 2017

5L35021 Datasheet

Byte 27: Output Divider 4

Byte 1Bh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OUTDIV3[3]

OUTDIV3[2]

OUTDIV3[1]

OUTDIV3[0]

OUTDIV4[3]

OUTDIV4[2]

OUTDIV4[1]

OUTDIV4[0]

Out divider 4 control bit 7

Out divider 4 control bit 6

Out divider 4 control bit 5

Out divider 4 control bit 4

Out divider 4 control bit 3

Out divider 4 control bit 2

Out divider 4 control bit 1

Out divider 4 control bit 0

R/W

—

0

1

0

1

Byte 28: PLL Operation Control Register

Byte 1Ch

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL2_HRS_EN

PLL2_refin_sel

PLL3_PDB

PLL2 spread high resolution selection enable R/W

normal

Xtal

enable (shift 4 bits)

DIV2

0

1

PLL2 reference clock source select

PLL3 Power Down

R/W

R/W Power Down

R/W bypass lock

R/W Power Down

R/W bypass lock

R/W Power Down

R/W bypass lock

running

lock

PLL3_LCKBYPSSB

PLL2_PDB

PLL3 lock bypass

PLL2 Power Down

running

lock

PLL2_LCKBYPSSB

PLL1_PDB

PLL2 lock bypass

PLL1 Power Down

running

lock

PLL1_LCKBYPSSB

PLL1 lock bypass

Byte 29: Output Control

Byte 1Dh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DIFF1_SEL

DIFF2_SEL

Differential clock 1 output OE2 control

Differential clock 2 output OE2 control

Differential clock 1 output enable

Differential clock 2 output enable

not controlled

disable

controlled

enable

Xtal

0

1

0

1

DIFF1_EN

R/W

DIFF2_EN

disable

OUTDIV4_Source

SE1_SLEW

Output divider 4 source clock selection R/W

PLL2

SE 1 slew rate control

VDD1 level control bit 1

VDD1 level control bit 0

R/W

normal

strong

VDD1_SEL[1]

VDD1_SEL[0]

11: 1.8

31

November 29, 2017

5L35021 Datasheet

Byte 30: OE and DFC Control

Byte 1Eh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SE1_EN

SE1 output enable control

OE1 pin function selection bit 1

OE1 pin function selection bit 0

Reserved

R/W

disable

enable

1

0

1

0

OE1_fun_sel[1]

OE1_fun_sel[0]

11:DFC0 10: SE1_PPS

01: PD# 00: SE1 OE

Reserved

DFC_SW_Sel[1]

DFC_SW_Sel[0]

DFC frequency select bit 1

DFC frequency select bit 0

R/W

00: N0 01: N1 10:N2 11:N3

Byte 31: Control Register

Byte 1Fh

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

1

0

1

0

Reserved

PLL2_3rd_EN_CFG

PLL2_EN_CH2

PLL2 3rd order control

PLL2 channel 2 enable control

PLL2 3rd Pole control

Reserved

1st order

disable

3rd order

enable

R/W

PLL2_EN_3rdpole

enable

Byte 32: Control Register

Byte 20h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

1

0

Reserved

DFC_EN

WD_EN

DFC function control

Watchdog timer control

Watchdog timer select bit 1

Watchdog timer select bit 0

Alarm Status (Read Only)

R/W

R

disable

enable

Timer_sel<1>

Timer_sel<0>

Alarm_Flag

00: 250ms 01: 500ms

10: 2s 11: 4s

No alarm Alarmed

32

November 29, 2017

5L35021 Datasheet

Byte 33: DIFF1 Control Register

Byte 21h

Name

Control Function

Reserved

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

1

0

1

0

Reserved

output tri-state,

bias off

Bit 2

Bit 1

Bit 0

DIFF_PDBHiZEN

Differential output high-Z at power down R/W

TBD

0

DIFF1_B

non-inverted

DIFF1_CMOS2_FLIP Differential 1/2 LVCMOS output control R/W DIFF1_B inverted

DIFF2_CMOS2_FLIP Differential 1/2 LVCMOS output control R/W DIFF2_B inverted

DIFF2_B

non-inverted

Byte 34: DIFF1 Control Register

Byte 22h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

DIFF1_CLK_SEL

Differential clock 1 source selection R/W

Reserved

DIV1

DIV3

1

0

1

DIFF1_OUTPUT_TYPE[1] Differential clock 1 type select bit 1 R/W

00: LVMOS 01: Reserved

10: Reserved 11: LPHCSL

DIFF1_OUTPUT_TYPE[0] Differential clock 1 type select bit 0 R/W

Reserved

Differential clock 1 LVCMOS slew

Bit 1

Bit 0

DIFF1_CMOS_SLEW

D1FF1_CMOS2_EN

R/W

normal

disable

strong

enable

0

rate control

Differential clock 1 LVCMOS

output_B control

33

November 29, 2017

5L35021 Datasheet

Byte 35: DIFF2 Control Register

Byte 23h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

DIFF2_CLK_SEL

Differential clock 2 source selection R/W

Reserved

DIV1

DIV3

0

1

0

1

DIFF2_OUTPUT_TYPE[1] Differential clock 2 type select bit 1 R/W

00: LVMOS 01: Reserved

10: Reserved 11: LPHCSL

DIFF2_OUTPUT_TYPE[0] Differential clock 2 type select bit 0 R/W

Reserved

Differential clock 2 LVCMOS slew

Bit 1

Bit 0

DIFF2_CMOS_SLEW

DIFF2_CMOS2_EN

R/W

normal

disable

strong

enable

0

rate control

Differential clock 2 LVCMOS

output_B control

Byte 36: SE1 and DIV4 control

Byte 24h

Name

Control Function

Type

0

1

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I2C_PDB

chip power down control bit

Reference clock output

Reserved

R/W

power down

stop

normal

freerun

1

0

1

0

Ref_free_run

SE1_Freerun_32K

SE1_CLKSEL1

REF_EN

SE1 clock output default

SEL1 output select

R/W

32k freerun

DIV5

B36bit3 control

DIV4

REF output enable

disable

enable

DIV4_CH3_EN

DIV4_CH2_EN

DIV4 channel 3 output control

enable

34

November 29, 2017

5L35021 Datasheet

Package Outline Draw ings

Figure 10. 3 × 3 mm 20-QFN Package Draw ings–page 1

35

November 29, 2017

5L35021 Datasheet

Figure 11. 3 × 3 mm 20-QFN Package Draw ings–page 2

36

November 29, 2017

5L35021 Datasheet

Marking Diagrams

1. Line 2 is the truncated part number.

2. “-000” denotes un-programmed part. Configuration left blank for user customization.

3. “-ddd” denotes dash code.

-000

L5021

YW**$

4. “YW” is the last digit of the year and week that the part was assembled.

5. “**” denotes lot sequence number.

6. “$” denotes mark code.

-ddd

L5021

YW**$

Ordering Information

Orderable Part Number

Package

Carrier Type

Temperature

5L35021-000NDGI

5L35021-000NDGI8

5L35021-dddNDGI

5L35021-dddNDGI8

3 x 3 mm, 0.4mm pitch 20-QFN

Trays

-40 to +85°C

Tape and Reel

Trays

Tape and Reel

Revision History

Revision Date

Description of Change

November 29, 2017

July 13, 2017

Updated I²C section.

Corrected typo in block diagram.

Initial release.

June 29, 2017

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

www.IDT.com/go/support

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,

without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same

way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability

of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not

convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-

sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property

37

November 29, 2017

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