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IXD5127N44ENR-G

型号：

IXD5127N44ENR-G

品牌：

IXYS[ IXYS CORPORATION ]

页数：

13 页

PDF大小：

555 K

下载PDF手册
IXD5127  
Voltage Detector with Delay Circuit and Manual Reset  
FEATURES  
DESCRIPTION  
o
o
Accuracy ± 0.8%  
The IXD5127 are highly precise, low power  
consumption, CMOS voltage detectors, with manual  
reset input and build-in delay circuit manufactured  
using laser trimming technology.  
Low Power Consumption  
0.6 µA (Detect at VDF = 1.8 V, VIN = 1.62 V)  
0.7 µA (Release at VDF = 1.8 V, VIN = 1.98 V)  
o
Detect Voltage Range 1.5 V – 5.5 V in 0.1 V  
increments  
It maintains high accuracy, low power consumption,  
and accurate release delay time over the full  
operation temperature range.  
o
o
o
Operating Voltage Range 0.7 V – 6.0 V  
Detect Voltage Temperature Drift ±50 ppm/0C  
Manual reset input allows IXD5127 generate reset at  
any desirable moment.  
Output Configuration CMOS (Version C) or N-  
channel Open Drain (N Version)  
With low power consumption and high accuracy, the  
series is suitable for precision mobile equipment.  
o
o
o
o
o
o
Preprogrammed Release Delay Time  
Manual Reset Input  
The IXD5127 in ultra small packages are ideally  
suited for high-density PC boards.  
Active High or Active Low Reset Output  
Operating Ambient Temperature - 40 + 850C  
Packages : USPN-4, SSOT-24, and SOT-25  
EU RoHS Compliant, Pb Free  
The IXD5127 is available in both CMOS and  
N-channel open drain output configurations  
Detector is available in USPN-4, SSOT-24, and  
SOT-25 packages.  
APPLICATIONS  
o
o
o
o
o
Microprocessor reset circuitry  
Memory battery back-up circuits  
Power-on reset circuits  
Power failure detection  
System battery life and charge voltage monitors  
TYPICAL APPLICATION CIRCUIT  
TYPICAL PERFORMANCE CHARACTERISTIC  
Release Delay Time vs. Ambient Temperature  
IXD5127x27Bx  
ꢀꢀꢀꢀꢀ  
VIN = VDFL x 0.9 →VDFL x 1.1, MR - Open  
Pull-up Resistor RPL used with N-channel output configuaration only  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
1
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
Input Voltage  
SYMBOL  
RATINGS  
UNITS  
VIN  
VMR  
IOUT  
– 0.3 ~ +6.5  
– 0.3 ~ +6.5  
20  
V
V
mA  
ꢀꢀꢀꢀꢀ  
MR Input Voltage  
Output Current  
Output  
CMOS Output  
N-channel Open Drain  
USPN-4  
– 0.3 ~ VIN + 0.3 ≤ 6.5  
– 0.3 ~ +6.5  
100  
VRST  
V
Voltage  
Power Dissipation  
SOT-25  
PD  
250  
mW  
SSOT-24  
Operating Temperature Range  
Storage Temperature Range  
150  
– 40 ~ + 85  
– 55 ~ +125  
TOPR  
TSTG  
0C  
0C  
All voltages are in respect to VSS  
ELECTRICAL OPERATING CHARACTERISTICS  
For N-channel open drain configuration RPULL = 100 kΩ, VPULL = VIN  
Ta = 25 0C  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
CIRCUIT  
1)  
ꢀꢀꢀꢀꢀ  
Operating Voltage  
Detect Voltage  
VIN  
VDF  
VDF(T) = 1.5 – 5.5 V, MR - Open  
0.72)  
6.0  
V
V
VIN = 1.0 – 6.0 V  
E-13)  
Å
Å
VDFL  
0.02  
x
VDFL  
0.05  
0.6  
0.7  
1.0  
0.7  
0.8  
1.1  
x
VDFL x  
0.08  
1.4  
1.6  
1.9  
1.6  
1.9  
2.35  
Hysteresis Width  
VHYS  
V
VIN = 1.5 – 1.8 V,  
VIN = VDFL x 0.9,  
MR - Open  
Supply Current13)  
ISS1  
VIN = 1.9 – 3.0 V  
VIN = 3.1 – 5.5 V  
VIN = 1.5 – 1.8 V,  
VIN = 1.9 – 3.0 V  
VIN = 3.1 – 5.5 V  
µA  
Ç
ꢀꢀꢀꢀꢀ  
VIN = VDF x 1.14)  
Supply Current23)  
ISS2  
µA  
Ç
Å
ꢀꢀꢀꢀꢀ  
MR - Open  
Detect Voltage  
Temperature  
∆ꢁꢂꢃ  
- 40 0C ≤ TOPR ≤ 85 0C  
± 50  
E-28)  
ppm/0C  
ꢁꢂꢃ ꢄ ∆ꢅꢆꢇꢈ  
Characteristics  
Detect Delay Time6)  
tDF  
tDR  
VMRL  
VMRH  
RMR  
TMR  
1009)  
µs  
ms  
V
V
MΩ  
ns  
Ñ
Ñ
Ö
Ö
Ü
á
ꢀꢀꢀꢀꢀ  
VIN = VDFL x 1.1 → VDFL x 0.9, MR - Open  
Release Delay Time7)  
ꢀꢀꢀꢀꢀ  
VIN = VDFL x 0.9 → VDFL x 1.1, MR - Open  
ꢀꢀꢀꢀꢀ  
MR LOW Level Voltage  
VDFL x 1.1 ≤ VIN ≤ 6.0 V  
VDFL x 1.1 ≤ VIN ≤ 6.0 V  
0
1.0  
0.4  
150  
0.014  
0.5  
4.4  
7.0  
8.5  
9.0  
0.3  
6.0  
3.0  
ꢀꢀꢀꢀꢀ  
MR HIGH Level Voltage  
ꢀꢀꢀꢀꢀ  
0.8  
MR Pull-up Resistance  
ꢀꢀꢀꢀꢀ  
MR Pulse Width  
VIN = 6.0 V  
VIN = 0.7 V  
VIN = 1.0 V  
0.2  
1.6  
7.0  
9.0  
11.0  
12.0  
V
RST = 0.5 V,  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
RESET  
Output Current  
IXD5118xxxA – E  
versions only  
VIN = 2.0 V, VDF(T) > 2.0 V  
ꢀꢀꢀꢀꢀ  
IOUT1  
MR - Open  
mA  
É
VIN = 3.0 V, VDF(T) > 3.0 V  
VIN = 4.0 V, VDF(T) > 4.0 V  
VIN = 5.0 V, VDF(T) > 5.0 V  
N-channel MOSFET  
ꢀꢀꢀꢀꢀ  
VIN = 6.0V, VRST = 5.5 V, MR - Open  
5)  
IOUT2  
VIN = 6.0 V  
-4.5  
-0.01  
0.01  
-3.0  
mA  
µA  
É
É
P-channel MOSFET  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
RESET  
Leakage Current  
IXD5118xxxA – E  
versions only  
VIN = VDFL x 0.9, VRST = 0 V,  
IXD5127CxxA - E  
(P-channel)  
ꢀꢀꢀꢀꢀ  
MR - Open  
ILEAK  
IXD5127NxxA - E  
(N-channel)  
VIN = VRST = 6.0 V,  
0.15  
ꢀꢀꢀꢀꢀ  
MR - Open  
VIN = 1.65 V, VDF(T) = 1.5 V  
VIN = 2.0 V, VDF(T) ≤ 1.8 V  
VIN = 3.0 V, VDF(T) ≤ 2.7 V  
VIN = 4.0 V, VDF(T) ≤ 3.6 V  
VIN = 5.0 V, VDF(T) ≤ 4.6 V  
VIN = 6.0 V  
VIN = 0.7 V  
VIN = 1.0 V  
VIN = 2.0 V, VDF(T) > 2.0 V  
VIN = 3.0 V, VDF(T) > 2.0 V  
VIN = 4.0 V, VDF(T) > 2.0 V  
VIN = 5.0 V, VDF(T) > 2.0 V  
0.5  
4.4  
7.0  
8.5  
9.0  
9.0  
1.6  
7.0  
9.0  
VRST = 0.5 V,  
MR - Open  
N-channel MOSFET  
ꢀꢀꢀꢀꢀ  
IOUT1  
mA  
mA  
É
É
11.0  
12.0  
12.0  
-0.07  
-0.4  
-2.0  
-3.0  
-4.0  
-4.5  
RESET  
Output Current  
IXD5118xxxF – K  
versions only  
-0.01  
-0.9  
-1.3  
-1.8  
-2.5  
-3.0  
VIN = 6.0V, VRST = 5.5  
5)  
ꢀꢀꢀꢀꢀ  
IOUT2  
V, MR - Open  
P-channel MOSFET  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
2
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
ELECTRICAL OPERATING CHARACTERISTICS (CONTINUED)  
Ta = 25 0C  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
CIRCUIT  
IXD5127CxxA - E  
(P-channel)  
IXD5127NxxA - E  
(N-channel)  
VIN = VDFL x 0.9, VRST = 0 V,  
RESET  
0.01  
0.15  
ꢀꢀꢀꢀꢀ  
Leakage Current  
IXD5118xxxF – K  
versions only  
MR - Open  
ILEAK  
µA  
É
VIN = VRST = 6.0 V,  
-0.01  
ꢀꢀꢀꢀꢀ  
MR - Open  
NOTE:  
1) VDF(T) is a nominal detect voltage  
6) A time between VIN = VDFL and VRST = VDFL × 0.45 when  
IN falls.  
7) A time between VIN=VDFL+VHYS and VRST=VDFL × 0.55  
when VIN rises.  
2) Minimum voltage, at which VRST remains below 0.3 V for  
IXD5127xxxA – E versions or above 0.4 V for  
IXD5127xxxF - K versions  
V
3)  
Please refer to the table named Voltage Chart  
8) Please refer to the table named Release Delay Time  
9) 200 µs for IXD5127NxxF – K versions  
4) VIN = 6.0 V at V DF(T) = 5.5 V  
5) IXD5127C version only  
Voltage Chart  
NOMINAL  
DETECT  
VOLTAGE  
(V)  
NOMINAL  
DETECT  
VOLTAGE  
(V)  
DETECT VOLTAGE  
DETECT VOLTAGE  
(V)  
E-1  
(V)  
E-1  
VDFL or VDFH  
VDFL or VDFH  
VDF(T)  
VDF(T)  
MIN.  
MAX  
MIN.  
MAX.  
1.50  
1.60  
1.70  
1.80  
1.90  
2.00  
2.10  
2.20  
2.30  
2.40  
2.50  
2.60  
2.70  
2.80  
2.90  
3.00  
3.10  
3.20  
3.30  
3.40  
3.50  
1.4880  
1.5872  
1.6864  
1.7856  
1.8848  
1.9840  
2.0832  
2.1824  
2.2816  
2.3808  
2.4800  
2.5792  
2.6784  
2.7776  
2.8768  
2.9760  
3.0752  
3.1744  
3.2736  
3.3728  
3.4720  
1.5120  
1.6128  
1.7136  
1.8144  
1.9152  
2.0160  
2.1168  
2.2176  
2.3184  
2.4192  
2.5200  
2.6208  
2.7216  
2.8224  
2.9232  
3.0240  
3.1248  
3.2256  
3.3264  
3.4272  
3.5280  
3.60  
3.70  
3.80  
3.90  
4.00  
4.10  
4.20  
4.30  
4.40  
4.50  
4.60  
4.70  
4.80  
4.90  
5.00  
5.10  
5.20  
5.30  
5.40  
5.50  
3.5712  
3.6704  
3.7696  
3.8688  
3.9680  
4.0672  
4.1664  
4.2656  
4.3648  
4.4640  
4.5632  
4.6624  
4.7616  
4.8608  
4.9600  
5.0592  
5.1584  
5.2576  
5.3568  
5.4560  
3.6288  
3.7296  
3.8304  
3.9312  
4.0320  
4.1328  
4.2336  
4.3344  
4.4352  
4.5360  
4.6368  
4.7376  
4.8384  
4.9392  
5.0400  
5.1408  
5.2416  
5.3424  
5.4432  
5.5440  
Release Delay Time  
RELEASE DELAY TIME  
(ms) E-2  
TYPE  
tDR  
MIN.  
42.5  
85  
170  
340  
680  
42.5  
85  
TYP.  
50  
MAX.  
57.5  
115  
230  
460  
920  
57.5  
115  
230  
460  
920  
IXD5127CxxA/IXD5127NxxA  
IXD5127CxxB/IXD5127NxxB  
IXD5127CxxC/IXD5127NxxC  
IXD5127CxxD/IXD5127NxxD  
IXD5127CxxE/IXD5127NxxE  
IXD5127CxxF/IXD5127NxxF  
IXD5127CxxG/IXD5127NxxG  
IXD5127CxxH/IXD5127NxxH  
IXD5127CxxJ/IXD5127NxxJ  
IXD5127CxxK/IXD5127NxxK  
100  
200  
400  
800  
50  
100  
200  
400  
800  
170  
340  
680  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
3
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
PIN CONFIGURATION  
USPN-4  
SSOT-24  
SOT-25  
(BOTTOM VIEW)  
(TOP VIEW)  
(TOP VIEW)  
PIN ASSIGNMENT  
PIN NUMBER  
SSOT-24  
PIN NAME  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
FUNCTIONS  
USPN-4  
SOT-25  
1)  
2)  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
1
4
4
RESET/RESET  
Output Voltage (RESET Active “LOW” , RESET – Active “HIGH” )  
Manual Reset Input (“HIGH” or “OPEN” State – Normal Operations, “LOW” –  
Forced Reset  
ꢀꢀꢀꢀꢀ  
MR  
2
3
1
3
4
2
1
2
5
3
VSS  
VIN  
NC  
Ground  
Power Input  
No internal Connect  
NOTE  
1) Type IXD5127xxxA – E versions  
2) Type IXD5127xxxF – K versions  
BLOCK DIAGRAMS  
XD5127CxxA - E  
IXD5127NxxA - E  
IXD5127CxxF - K  
IXD5127NxxF – K  
Diodes inside the circuits are ESD protection diodes and parasitic diodes.  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
4
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
BASIC OPERATION  
The timing diagram shown below exlains operation of the IXD5127xxxA - E in a typical application circuit.  
Å At the initial state, an input voltage VIN is higher than the detect voltage VDFL, and output voltage VRST is equal to  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
the input voltage VIN. In the case of N-channel open drain architecture, the RESET pin is in a high-impedance state,  
and the output voltage VRST is equal to the pull-up voltage.  
Ç, É After the elapse of the Detect Delay Time tDF that starts when the input voltage VIN falls below the detect  
voltage VDFL, an output voltage VRST becomes equal to the ground voltage VSS (detection state).  
Ñ If the input voltage VIN drops below minimum operating voltage of 0.7 V, the output goes into undefined state. In  
case of N-channel open drain output architecture, an output voltage VRST may be equal to the pull-up voltage.  
Ö If input voltage VIN is above minimum operating voltage of 0.7 V, but less than the release voltage VDR, the  
output voltage VRST is at the ground level.  
Ü The delay circuit keeps the output voltage VRST at the ground level until the Release Delay Time tDR from the  
moment, when the input voltage VIN becomes higher than the release voltage VDR, elapses.  
á After the Release Delay Time tDR elapses, the output voltage VRST becomes equal to the input voltage VIN  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
(release state). In the case of N-channel open drain architecture, the RESET pin goes into high impedance state,  
and an output voltage VRST becomes equal to the pull-up voltage.  
à The difference between the release voltage VDR and the detect voltage VDFL is the hysteresis width VHYS  
.
The timing diagram shown below explains operation of the IXD5127xxxF - K in a typical application circuit.  
Å At the initial state, when an input voltage VIN is higher than the detect voltage VDFH, an output voltage VRST is  
equal to the ground voltage VSS.  
ÇÉ After the elapse of the Detect Delay Time tDF that starts, when the input voltage VIN falls below the detect  
voltage VDFH, the output voltage VRST is equal to the input voltage VIN (detection state). In the case of N-channel  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
5
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
open drain architecture, the RESET pin is in a high-impedance state, and the output voltage VRST is equal to the  
pull-up voltage.  
Ñ If the input voltage VIN falls below the minimum operating voltage of 0.7 V, the output goes into undefined state.  
Ö When the input voltage VIN is above the minimum operating voltage of 0.7V, but below the release voltage VDR,  
the output voltage VRST is equal to the VIN voltage. In the case of N-channel open drain architecture, the RESET pin  
is in a high-impedance state, and the output voltage VRST is equal to the pull-up voltage.  
Ü The delay circuit keeps the output voltage VRST at the VIN level until the Release Delay Time tDR from the  
moment, when the input voltage VIN becomes higher than the release voltage VDR, elapses.  
á After the Release Delay Time tDR elapses, the output voltage VRST becomes equal to the ground voltage VSS  
(release state).  
à The difference between the release voltage VDR and the detect voltage VDFH is the hysteresis width VHYS  
ꢀꢀꢀꢀꢀ  
.
The timing diagram shown below explains operation of the MR pin.  
ꢀꢀꢀꢀꢀ  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
ꢉ pin output.  
Signal applied to the MR pin can forcibly change the state of the RESET (RESET  
ꢀꢀꢀꢀꢀ  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
) pin output change state to the  
If the MR pin voltage VMR falls equal or below “LOW” threshold level, RESET (RESET  
detect state, even if VIN voltage remains above detect voltage VDF.  
ꢀꢀꢀꢀꢀ  
After the MR input voltage, VMR, changes state from “LOW” to “HIGH,” the output pin remains in the detection state  
during the Release Delay Time tDR. After the Release Delay Time tDR elapses, the output pin changes state to the  
release one.  
NOTE:  
1) The output voltage in the release state is as shown below by product type.  
IXD5127CxxA – E types - VIN  
IXD5127NxxA – E types - VPULL  
IXD5127xxxF – K types - Ground voltage (VSS  
)
2) The output voltage in the detect state is as shown below by product type.  
IXD5127xxxA – E types - Ground voltage (VSS  
IXD5127CxxF – K types - VIN  
)
IXD5127NxxF – K types - VPULL  
ꢀꢀꢀꢀꢀ  
ꢀꢀꢀꢀꢀ  
3) A pull-up resistor (RMR) is built-in between the MR pin and the VIN pin, and thus, if a voltage below VIN is applied to the MR pin,  
ꢀꢀꢀꢀꢀ  
current will flow from the VIN to the MR pin.  
ꢀꢀꢀꢀꢀ  
4) The MR pin input voltage should be within the range from VSS to 6.0 V.  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
6
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
TYPICAL APPLICATION CIRCUIT  
IXD5127xxxF - K  
IXD5127xxxA - E  
LAYOUT AND USE CONSIDERATIONS  
1. The IC may malfunction if absolute maximum ratings are exceeded.  
2. High impedance VIN power supply may cause IC malfunction, if VIN voltage falls below minimum operating level due  
current consumption, when IC output changes state. In addition, output voltage at “High” state reflects every variations  
of VIN voltage.  
3. High impedance VIN power supply may cause IC oscillations, if voltage drop at power supply’s internal resistance  
exceeds IC hysteresis.  
4. Note that a rapid and high amplitude fluctuation of the VIN pin voltage, as well as a power supply noise, may cause a  
wrong IC operation. The capacitor between VIN and GND pins should be used to minimize noise impact.  
5. Output voltage In N channel open drain configuration depends on pull-up resistance, as well as on/off  
resistance of the N-channel MOSFET (see block diagrams above).  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
For IXD5127NxxA – E versions with RESET pin active LOW, output voltage during detection  
VOUT = VPULL / (1 + RPULL / RON),  
where VPULL is a pull up voltage and RON is an N-channel MOSFET on-resistance, which can be calculated  
as VRST / IOUT1 from electrical characteristics.  
For example:  
To get VOUT ≤ 0.1V at detect state, with RON = 0.5/4.4 ×10-3 = 114 Ω (max) at VIN = 2.0 V and VPULL = 3.0 V,  
pull-up resistor value should be  
RPULL = (VPULL /VOUT - 1) × RON= (3 / 0.1-1) × 114 ≥ 3.3 kΩ .(1)  
Note that decreasing VIN voltage increases RON resistance, so minimum expected VIN voltage should be  
used for calculations..  
At releasing state VOUT = VPULL/(1 + RPULL / ROFF), where ROFF = VOUT/ILEAK = 40 MΩ (min) for N-channel  
MOSFET in off state.  
Therefore, in this case, pull-up resistor should be  
RPULL = (VPULL/VOUT-1) × ROFF = (3/2.99 - 1) × 40 × 106 ≤ 133 kΩ (2)  
to get VOUT ≥ 2.99 V at VPULL = 3.0 V.  
For IXD5127NxxF – K versions with RESET pin active HIGH, output voltage during detect state should be  
calculated using equation (2), while output voltage during release state should be calculated using equation  
(1), because for these parts N-channel MOSFET is in opposite state compared to example shown above.  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
7
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
TEST CIRCUITS  
Circuit Å  
Circuit Ç  
Circuit É  
Circuit Ö  
Circuit Ñ  
Circuit Ü  
Circuit á  
Pull-up Resistor RPL = 100 kΩ is used for IXD5127N version only  
ORDERING INFORMATION  
IXD5127ÅÇÉÑÖÜ-á  
DESIGNATOR  
DESCRIPTION  
SYMBOL  
DESCRIPTION  
C
N
CMOS output  
N-channel Open Drain Output  
Å
Output Configuration  
ÇÉ  
Detect Voltage (VDF  
)
15 - 55  
A
B
C
D
E
F
G
H
J
K
7R-G  
NR-G  
MR-G  
Detect Voltage Range: 1.5 V～5.5 V, e.g. 3.2 V - Ç = 3, É = 2  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
RESET – Active LOW, Release Delay Time – 50 ms  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
RESET – Active LOW, Release Delay Time – 100 ms  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
RESET – Active LOW, Release Delay Time – 200 ms  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
RESET – Active LOW, Release Delay Time – 400 ms  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
RESET – Active LOW, Release Delay Time – 800 ms  
Ñ
Options  
RESET – Active HIGH, Release Delay Time – 50 ms  
RESET – Active HIGH, Release Delay Time – 100 ms  
RESET – Active HIGH, Release Delay Time – 200 ms  
RESET – Active HIGH, Release Delay Time – 400 ms  
RESET – Active HIGH, Release Delay Time – 800 ms  
USPN-4 (5000/Reel)  
Packages  
(Order Unit)  
ÖÜ-á(*)  
SSOT-24 (3000/reel)  
SOT-25 (3000/Reel)  
NOTE:  
The “-G” suffix denotes Halogen and Antimony free as well as being fully RoHS compliant.  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
8
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
PACKAGE DRAWING AND DIMENSIONS  
USPN-4, Units: mm  
SOT-25, Units: mm  
USPN-4 Reference Pattern Layout, Units: mm  
SSOT-24, Units: mm  
USP-4 Reference Metal Mask Design  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
9
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
MARKING  
USPN-4  
Å- Represents product series and output configuration  
MARK  
F
H
OUTPUT CONFIGURATION  
CMOS  
PRODUCT SERIES  
IXD5127Cxxxxx-G  
IXD5127Nxxxxx-G  
N-channel  
Ç - Represents detect voltage  
MARK DETECT VOLTAGE(V) MARK DETECT VOLTAGE(V) MARK DETECT VOLTAGE(V)  
A
B
C
D
E
F
1.5  
1.7  
1.9  
2.1  
2.3  
2.5  
2.7  
1.6  
1.8  
2.0  
2.2  
2.4  
2.6  
2.8  
K
L
2.9  
3.1  
3.3  
3.5  
3.7  
3.9  
4.1  
3.0  
3.2  
3.4  
3.6  
3.8  
4.0  
4.2  
T
U
V
X
Y
Z
0
4.3  
4.5  
4.7  
4.9  
5.1  
5.3  
5.5  
4.4  
4.6  
4.8  
5.0  
5.2  
5.4  
-
M
N
P
R
S
H
É- Represents detect voltage range and release delay time/detect state output logic  
MARK  
DETECT VOLTAGE RELEASE DELAY TIME/OUTPUT LOGIC  
PRODUCT SERIES  
A
B
C
D
E
F
H
K
L
M
N
P
R
S
T
U
V
X
Y
Z
50 ms/Active Low  
100 ms/Active Low  
200 ms/Active Low  
400 ms/Active Low  
800 ms/Active Low  
50 ms/Active High  
100 ms/Active High  
200 ms/Active High  
400 ms/Active High  
800 ms/Active High  
50 ms/Active Low  
100 ms/Active Low  
200 ms/Active Low  
400 ms/Active Low  
800 ms/Active Low  
50 ms/Active High  
100 ms/Active High  
200 ms/Active High  
400 ms/Active High  
800 ms/Active High  
IXD5127x15Axx-G – IXD5127x55Axx-G  
IXD5127x15Bxx-G – IXD5127x55Bxx-G  
IXD5127x15Cxx-G – IXD5127x55Cxx-G  
IXD5127x15Dxx-G – IXD5127x55Dxx-G  
IXD5127x15Exx-G – IXD5127x55Exx-G  
IXD5127x15Fxx-G – IXD5127x55Fxx-G  
IXD5127x15Gxx-G – IXD5127x55Gxx-G  
IXD5127x15Hxx-G – IXD5127x55Hxx-G  
IXD5127x15Jxx-G – IXD5127x55Jxx-G  
IXD5127x15Kxx-G – IXD5127x55Kxx-G  
IXD5127x16Axx-G – IXD5127x54Axx-G  
IXD5127x16Bxx-G – IXD5127x54Bxx-G  
IXD5127x16Cxx-G – IXD5127x54Cxx-G  
IXD5127x16Dxx-G – IXD5127x54Dxx-G  
IXD5127x16Exx-G – IXD5127x54Exx-G  
IXD5127x16Fxx-G – IXD5127x54Fxx-G  
IXD5127x16Gxx-G – IXD5127x54Gxx-G  
IXD5127x16Hxx-G – IXD5127x54Hxx-G  
IXD5127x16Jxx-G – IXD5127x54Jxx-G  
IXD5127x16Kxx-G – IXD5127x54Kxx-G  
Odd Value  
Even Value  
Ñ - Represents production lot number  
0 to 9, A to Z, and inverted 0 to 9, A to Z repeated. (G, I, J, O, Q, W excluded.)  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
10  
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
MARKING (CONTINUED)  
Products  
with  
CMOS  
output  
configuration are shipped in the  
package with the orientation bar on  
the top (a), while products with N-  
channel configuration are shipped with  
orientation bar on the bottom (b).  
SSOT-24  
Å - Represents product series and detect voltage range/output configuration  
OUTPUT  
CONFIGURATION  
DETECT  
VOLTAGE  
RELEASE DELAY  
TIME/OUTPUT LOGIC  
MARK  
PRODUCT SERIES  
5
6
7
8
9
50 ms/Active Low  
100 ms/Active Low  
200 ms/Active Low  
400 ms/Active Low  
800 ms/Active Low  
50 ms/Active High  
100 ms/Active High  
200 ms/Active High  
400 ms/Active High  
800 ms/Active High  
50 ms/Active Low  
100 ms/Active Low  
200 ms/Active Low  
400 ms/Active Low  
800 ms/Active Low  
50 ms/Active High  
100 ms/Active High  
200 ms/Active High  
400 ms/Active High  
800 ms/Active High  
50 ms/Active Low  
100 ms/Active Low  
200 ms/Active Low  
400 ms/Active Low  
800 ms/Active Low  
50 ms/Active High  
100 ms/Active High  
200 ms/Active High  
400 ms/Active High  
800 ms/Active High  
50 ms/Active Low  
100 ms/Active Low  
200 ms/Active Low  
400 ms/Active Low  
800 ms/Active Low  
50 ms/Active High  
100 ms/Active High  
200 ms/Active High  
400 ms/Active High  
800 ms/Active High  
IXD5127x15Axx-G – IXD5127x55Axx-G  
IXD5127x15Bxx-G – IXD5127x55Bxx-G  
IXD5127x15Cxx-G – IXD5127x55Cxx-G  
IXD5127x15Dxx-G – IXD5127x55Dxx-G  
IXD5127x15Exx-G – IXD5127x55Exx-G  
IXD5127x15Fxx-G – IXD5127x55Fxx-G  
IXD5127x15Gxx-G – IXD5127x55Gxx-G  
IXD5127x15Hxx-G – IXD5127x55Hxx-G  
IXD5127x15Jxx-G – IXD5127x55Jxx-G  
IXD5127x15Kxx-G – IXD5127x55Kxx-G  
IXD5127x16Axx-G – IXD5127x54Axx-G  
IXD5127x16Bxx-G – IXD5127x54Bxx-G  
IXD5127x16Cxx-G – IXD5127x54Cxx-G  
IXD5127x16Dxx-G – IXD5127x54Dxx-G  
IXD5127x16Exx-G – IXD5127x54Exx-G  
IXD5127x16Fxx-G – IXD5127x54Fxx-G  
IXD5127x16Gxx-G – IXD5127x54Gxx-G  
IXD5127x16Hxx-G – IXD5127x54Hxx-G  
IXD5127x16Jxx-G – IXD5127x54Jxx-G  
IXD5127x16Kxx-G – IXD5127x54Kxx-G  
IXD5127x15Axx-G – IXD5127x55Axx-G  
IXD5127x15Bxx-G – IXD5127x55Bxx-G  
IXD5127x15Cxx-G – IXD5127x55Cxx-G  
IXD5127x15Dxx-G – IXD5127x55Dxx-G  
IXD5127x15Exx-G – IXD5127x55Exx-G  
IXD5127x15Fxx-G – IXD5127x55Fxx-G  
IXD5127x15Gxx-G – IXD5127x55Gxx-G  
IXD5127x15Hxx-G – IXD5127x55Hxx-G  
IXD5127x15Jxx-G – IXD5127x55Jxx-G  
IXD5127x15Kxx-G – IXD5127x55Kxx-G  
IXD5127x16Axx-G – IXD5127x54Axx-G  
IXD5127x16Bxx-G – IXD5127x54Bxx-G  
IXD5127x16Cxx-G – IXD5127x54Cxx-G  
IXD5127x16Dxx-G – IXD5127x54Dxx-G  
IXD5127x16Exx-G – IXD5127x54Exx-G  
IXD5127x16Fxx-G – IXD5127x54Fxx-G  
IXD5127x16Gxx-G – IXD5127x54Gxx-G  
IXD5127x16Hxx-G – IXD5127x54Hxx-G  
IXD5127x16Jxx-G – IXD5127x54Jxx-G  
IXD5127x16Kxx-G – IXD5127x54Kxx-G  
Odd Value  
Even Value  
Odd Value  
Even Value  
A
B
C
D
E
F
H
K
N
P
R
S
T
U
V
0
1
2
3
4
5
6
7
8
CMOS  
9
N-channel  
A
B
C
D
E
F
H
K
L
M
Ç - Represents detect voltage  
MARK DETECT VOLTAGE(V) MARK DETECT VOLTAGE(V) MARK DETECT VOLTAGE(V)  
A
B
C
D
E
F
1.5  
1.7  
1.9  
2.1  
2.3  
2.5  
2.7  
1.6  
1.8  
2.0  
2.2  
2.4  
2.6  
2.8  
K
L
2.9  
3.1  
3.3  
3.5  
3.7  
3.9  
4.1  
3.0  
3.2  
3.4  
3.6  
3.8  
4.0  
4.2  
T
U
V
X
Y
Z
0
4.3  
4.5  
4.7  
4.9  
5.1  
5.3  
5.5  
4.4  
4.6  
4.8  
5.0  
5.2  
5.4  
-
M
N
P
R
S
H
ÉÑ - Represents production lot number: 01～09, 0A～0Z, 11～9Z, A1～A9, AA～AZ、B1～ZZ repeated.  
(G, I, J, O, Q, W excluded.)  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
11  
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
MARKING (CONTINUED)  
SOT-25  
Å- Represents product series and output configuration  
MARK  
5
6
OUTPUT CONFIGURATION  
CMOS  
PRODUCT SERIES  
IXD5127Cxxxxx-G  
IXD5127Nxxxxx-G  
N-channel  
Ç - Represents detect voltage  
MARK DETECT VOLTAGE(V) MARK DETECT VOLTAGE(V) MARK DETECT VOLTAGE(V)  
A
B
C
D
E
F
1.5  
1.7  
1.9  
2.1  
2.3  
2.5  
2.7  
1.6  
1.8  
2.0  
2.2  
2.4  
2.6  
2.8  
K
L
2.9  
3.1  
3.3  
3.5  
3.7  
3.9  
4.1  
3.0  
3.2  
3.4  
3.6  
3.8  
4.0  
4.2  
T
U
V
X
Y
Z
0
4.3  
4.5  
4.7  
4.9  
5.1  
5.3  
5.5  
4.4  
4.6  
4.8  
5.0  
5.2  
5.4  
-
M
N
P
R
S
H
É - Represents detect voltage range and release delay time/detect state output logic  
MARK  
DETECT VOLTAGE RELEASE DELAY TIME/OUTPUT LOGIC  
PRODUCT SERIES  
A
B
C
D
E
F
H
K
L
M
N
P
R
S
T
U
V
X
Y
Z
50 ms/Active Low  
100 ms/Active Low  
200 ms/Active Low  
400 ms/Active Low  
800 ms/Active Low  
50 ms/Active High  
100 ms/Active High  
200 ms/Active High  
400 ms/Active High  
800 ms/Active High  
50 ms/Active Low  
100 ms/Active Low  
200 ms/Active Low  
400 ms/Active Low  
800 ms/Active Low  
50 ms/Active High  
100 ms/Active High  
200 ms/Active High  
400 ms/Active High  
800 ms/Active High  
IXD5127x15Axx-G – IXD5127x55Axx-G  
IXD5127x15Bxx-G – IXD5127x55Bxx-G  
IXD5127x15Cxx-G – IXD5127x55Cxx-G  
IXD5127x15Dxx-G – IXD5127x55Dxx-G  
IXD5127x15Exx-G – IXD5127x55Exx-G  
IXD5127x15Fxx-G – IXD5127x55Fxx-G  
IXD5127x15Gxx-G – IXD5127x55Gxx-G  
IXD5127x15Hxx-G – IXD5127x55Hxx-G  
IXD5127x15Jxx-G – IXD5127x55Jxx-G  
IXD5127x15Kxx-G – IXD5127x55Kxx-G  
IXD5127x16Axx-G – IXD5127x54Axx-G  
IXD5127x16Bxx-G – IXD5127x54Bxx-G  
IXD5127x16Cxx-G – IXD5127x54Cxx-G  
IXD5127x16Dxx-G – IXD5127x54Dxx-G  
IXD5127x16Exx-G – IXD5127x54Exx-G  
IXD5127x16Fxx-G – IXD5127x54Fxx-G  
IXD5127x16Gxx-G – IXD5127x54Gxx-G  
IXD5127x16Hxx-G – IXD5127x54Hxx-G  
IXD5127x16Jxx-G – IXD5127x54Jxx-G  
IXD5127x16Kxx-G – IXD5127x54Kxx-G  
Odd Value  
Even Value  
ÑÖ - Represents production lot number 01～09, 0A～0Z, 11～9Z, A1～A9, AA～AZ、B1～ZZ repeated.  
(G, I, J, O, Q, W excluded.)  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
12  
Doc. No. IXD5127_DS, Rev. N0  
IXD5127  
Warranty and Use  
IXYS CORP. MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY  
PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD  
PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH  
USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.  
IXYS Corp. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended  
to support or sustain life, or for any other application in which the failure of the IXYS Corp. product could create a situation where personal injury or death may occur.  
IXYS Corp. reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance  
Information" or "Preliminary" and other products described herein may not be in production or offered for sale.  
IXYS Corp. advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor  
applications and may not be complete.  
IXYS Corp.  
1590 Buckeye Dr.  
Milpitas, CA 95035-7418  
Phone: 408. 457.9000  
Fax: 408. 496.0222  
Document No:IXD5127_DS  
Revision:  
N0  
http://www.ixys.com  
Issue date:  
2/12/2014  
© 2014 IXYS Corp.  
Characteristics subject to change without notice  
13  
Doc. No. IXD5127_DS, Rev. N0  
厂商 型号 描述 页数 下载

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