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5V2528PGGI

型号：

5V2528PGGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

9 页

PDF大小：

155 K

下载PDF手册
2.5V / 3.3V PHASE-LOCK  
LOOP CLOCK DRIVER  
IDT5V2528/A  
NRND  
ZERO DELAY BUFFER  
NOT RECOMMENDED FOR NEW DESIGNS  
PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power  
supply pins.  
FEATURES:  
• Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ  
• 1:10 fanout  
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of the ten  
outputs,uptosevenmaybeconfiguredfor2.5Vor3.3VLVTTLoutputs. Thenumber  
of 2.5V outputs is controlled by 3-level input signals G_Ctrl and T_Ctrl, and by  
connectingtheappropriateVDDQ pinsto2.5Vor3.3V. The3-levelinputsignalsmay  
be hard-wired to high-mid-low levels. Output signal duty cycles are adjusted to  
50 percent, independent of the duty cycle at CLK. The outputs can be enabled or  
disabledviatheG_Ctrl input.WhentheG_Ctrlinputismidorhigh,theoutputsswitch  
inphaseandfrequencywithCLK;whentheG_Ctrlislow,alloutputs(exceptFBOUT)  
are disabled to the logic-low state.  
UnlikemanyproductscontainingPLLs,theIDT5V2528doesnotrequireexternal  
RCnetworks. TheloopfilterforthePLLisincludedon-chip, minimizingcomponent  
count, board space, and cost.  
BecauseitisbasedonPLLcircuitry,theIDT5V2528requiresastabilizationtime  
toachievephaselockofthefeedbacksignaltothereferencesignal.Thisstabilization  
timeisrequired,followingpowerupandapplicationofafixed-frequency,fixed-phase  
signal at CLK, as well as following any changes to the PLL reference or feedback  
signals. ThePLLcanbebypassedfortestpurposesbystrappingAVDDtoground.  
• 3-level inputs for output control  
• External feedback (FBIN) pin is used to synchronize the  
outputs to the clock input signal  
• No external RC network required for PLL loop stability  
• Configurable 2.5V or 3.3V LVTTL outputs  
• tPD Phase Error at 100MHz to 166MHz: ±150ps  
• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps  
• Spread spectrum compatible  
• Operating Frequency:  
-
Std: 25MHz to 140MHz  
- A: 25MHz to 167MHz  
• Available in TSSOP package  
• NOT RECOMMENDED FOR NEW DESIGNS  
DESCRIPTION:  
The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock loop  
(PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase,  
thefeedback(FBOUT)outputtotheclock(CLK)inputsignal.TheIDT5V2528inputs,  
FUNCTIONALBLOCKDIAGRAM  
28  
G_Ctrl  
3
1
T_Ctrl  
TY0, VDDQ pin 4  
26  
TY1, VDDQ pin 25  
24  
TY2, VDDQ pin 25  
MODE  
SELECT  
17  
TY3, VDDQ pin 15  
16  
TY4, VDDQ pin 15  
13  
TY5, VDDQ pin 11  
12  
TY6, VDDQ pin 11  
10  
6
7
TY7, VDDQ pin 11  
CLK  
PLL  
20  
Y0, VDD pin 21  
FBIN  
AVDD  
19  
Y1, VDD pin 21  
5
22  
FBOUT, VDD pin 21  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
MAY 2013  
INDUSTRIAL TEMPERATURE RANGE  
1
c
2013 Integrated Device Technology, Inc.  
DSC 5971/12  
IDT5V2528/A  
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER  
INDUSTRIAL TEMPERATURE RANGE  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
Rating  
Max.  
–0.5to+4.6  
–0.5to+5.5  
–0.5to  
Unit  
V
VDD, VDDQ, AVDD  
SupplyVoltageRange  
InputVoltageRange  
T_Ctrl  
GND  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
G_Ctrl  
GND  
TY1  
(2)  
VI  
V
2
(2)  
VO  
VoltageRangeappliedtoany  
V
3
output in the HIGH or LOW state VDD+0.5  
TY0  
IIK (VI < 0)  
InputClampCurrent  
OutputClampCurrent  
–50  
mA  
mA  
VDDQ  
4
VDDQ  
TY2  
IOK  
±50  
AVDD  
CLK  
5
(VO < 0 or VO > VDD)  
6
GND  
FBOUT  
VDD  
IO  
ContinuousOutputCurrent  
±50  
mA  
FBIN  
AGND  
GND  
TY7  
7
(VO = 0 to VDD)  
VDD or GND  
TSTG  
8
ContinuousCurrent  
±200  
–65to+150  
+150  
mA  
°C  
°C  
9
Y0  
StorageTemperatureRange  
JunctionTemperature  
10  
11  
Y1  
TJ  
NOTES:  
VDDQ  
GND  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
TY6  
TY5  
12  
13  
17  
16  
TY3  
TY4  
GND  
14  
15  
VDDQ  
2. The input and output negative-voltage ratings may be exceeded if the input and output  
clamp-current ratings are observed.  
3. The maximum package power dissipation is calculated using a junction temperature  
TSSOP  
TOP VIEW  
of 150°C and a board trace length of 750 mils.  
CAPACITANCE(1)  
Symbol  
Description  
Input Capacitance  
VI = VDD or GND  
Min  
Typ.  
Max. Unit  
CIN  
—
5
—
pF  
pF  
pF  
CO  
CL  
Output Capacitance  
VI = VDD or GND  
—
6
—
Load Capacitance 2.5V outputs  
3.3V outputs  
—
—
20  
30  
—
—
NOTE:  
1. Unused inputs must be held HIGH or LOW to prevent them from floating.  
RECOMMENDEDOPERATINGRANGE  
Symbol  
Description  
Min.  
Typ.  
Max.  
Unit  
V
(1)  
VDD, AVDD  
Power Supply Voltage  
Power Supply Voltage  
3
3.3  
3.6  
(1)  
VDDQ  
2.5VOutputs  
3.3VOutputs  
2.3  
3
2.5  
3.3  
2.7  
3.6  
V
TA  
AmbientOperatingTemperature  
–40  
+25  
+85  
°C  
NOTE:  
1. All power supplies should operate in tandem. If VDD or VDDQ is at a maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.  
2
IDT5V2528/A  
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER  
INDUSTRIAL TEMPERATURE RANGE  
PINDESCRIPTION  
Terminal  
Name  
CLK(1)  
FBIN  
No.  
6
Type  
Description  
Clockinput  
I
7
I
Feedbackinput  
G_Ctrl(2)  
28  
3-level  
3-levelinputfor2.5V/3.3VOutputSelect/Outputbankenable. When G_CtrlisLOW,alloutputsexceptFBOUTaredisabled  
to a logic-LOW state. When G_Ctrl is MID or HIGH, all outputs are enabled and switch at the same frequency as CLK (see  
OUTPUT SELECTION table).  
T_Ctrl(2)  
FBOUT  
TY(7:0)  
1
3-level  
3-level input for 2.5V / 3.3V Output Select (see OUTPUT SELECTION table)  
Feedbackoutput  
22  
3, 10, 12, 13,  
16, 17, 24, 26  
19,20  
O
O
2.5Vor3.3VClockoutputs. 1,2,3,5,or7oftheseoutputsmaybeselectedas2.5Voutputs(seeOUTPUTSELECTIONtable).  
Y(1:0)  
O
3.3V Clock Outputs  
(3)  
AVDD  
5
Power  
Ground  
Power  
Power  
Ground  
3.3V Analog power supply. AVDD provides the power reference for the analog circuitry.  
AGND  
VDD  
8
Analogground. AGNDprovidesthegroundreferencefortheanalogcircuitry.  
21  
3.3V Power supply  
VDDQ  
GND  
4, 11, 15, 25  
2, 9, 14, 18  
23,27  
2.5V or 3.3V Power supply for TY outputs  
Ground  
NOTES:  
1. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time of 1ms  
is required for the PLL to phase lock the feedback signal to the reference signal.  
2. 3-level inputs will float to MID logic level if left unconnected.  
3. AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the outputs.  
(1)  
STATIC FUNCTION TABLE (AVDD = 0V)  
OUTPUTSELECTION  
Inputs  
T_Ctrl  
X
Outputs  
VDDQ  
Configuration  
Pin 4 (2.5V)  
Pins 11, 15, 25 (3.3V)  
Pin 25 (2.5V)  
Pins 4, 11, 15 (3.3V)  
Pins 4, 25 (2.5V)  
Pins 11, 15 (3.3V)  
Pins 4, 15, 25 (2.5V)  
Pin 11 (3.3V)  
Pins 11, 15, 25 (2.5V)  
Pin 4 (3.3V)  
Pins 4, 11, 15, 25 (3.3V)  
G_Ctrl  
CLK  
TY(7:0)  
Y(1:0)  
FBOUT  
G_Ctrl  
T_Ctrl  
TY(7:0)  
L
L
L
H
H
L
L
H
L
L
H
L
M
L
TY0(2.5V)  
X
H
H
TY1 - TY7 (3.3V)  
TY1,TY2(2.5V)  
TY0, TY3 - TY7 (3.3V)  
TY0 - TY2 (2.5V)  
TY3 - TY7 (3.3V)  
TY0 - TY4 (2.5V)  
TY5 - TY7 (3.3V)  
TY1 - TY7 (2.5V)  
TY0 (3.3V)  
see  
M
M
H
H
H
M
H
L
OUTPUT SELECTION  
table  
L
L
L
L
running  
running  
running  
running  
NOTE:  
1. AVDD should be powered up along with VDD, before setting AVDD to ground, to put the  
control pins in a valid state.  
M
H
TYo - TY7 (3.3V)  
DYNAMIC FUNCTION TABLE (AVDD = 3.3V)  
Inputs  
T_Ctrl  
X
Outputs  
Y(1:0)  
G_Ctrl  
L
L
CLK  
L
H
TY(7:0)  
L
L
FBOUT  
L
L
L
L
H
L
X
see OUTPUT  
L
L
SELECTION table  
H
H
H
H
3
IDT5V2528/A  
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER  
INDUSTRIAL TEMPERATURE RANGE  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
Symbol  
VIK  
Parameter  
Test Conditions  
Min.  
Typ.(1)  
Max  
Unit  
V
InputClampVoltage  
Input HIGH Level  
II = -18mA  
- 1.2  
VIH  
CLK, FBIN  
2
V
VIL  
InputLOWLevel  
CLK, FBIN  
0.8  
V
VIHH  
VIMM  
VILL  
VOH  
Input HIGH Voltage Level(2)  
Input MID Voltage Level(2)  
InputLOWVoltageLevel(2)  
Output HIGH Voltage Level  
(3.3VOutputs)  
3-Level Inputs Only  
3-Level Inputs Only  
3-Level Inputs Only  
IOH = -100μA  
IOH = -12mA  
IOH = -100μA  
IOH = -12mA  
IOL = 100μA  
IOL = 12mA  
VDD - 0.6  
V
VDD/2 - 0.3  
VDD/2 + 0.3  
0.6  
V
V
VDD - 0.2  
2.4  
V
VOH  
VOL  
VOL  
I3  
Output HIGH Voltage Level  
(2.5VOutputs)  
VDD - 0.1  
2
V
V
OutputLOWVoltageLevel  
(3.3VOutputs)  
0.2  
0.4  
OutputLOWVoltageLevel  
(2.5VOutputs)  
IOL = 100μA  
IOL = 12mA  
0.1  
V
0.4  
3-LevelInputDCCurrent  
(G_Ctrl,T_Ctrl)  
VIN = VDD  
HIGH Level  
MID Level  
LOW Level  
+200  
+50  
VIN = VDD/2  
–50  
μA  
μA  
VIN = GND  
–200  
II  
InputCurrent  
VI = VDD or GND  
±5  
NOTES:  
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.  
2. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias floating inputs to VDD/2. If these inputs are switched, the function and timing of  
the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.  
POWERSUPPLYCHARACTERISTICS  
Symbol  
IDDPD  
IDDA  
Parameter  
Test Conditions  
Typ.(1)  
8
Max  
40  
Unit  
μA  
mA  
Power Down Supply Current  
AVDD Supply Current  
VDD = 3.6, VDDQ = 2.7V / 3.3V, AVDD = 0V  
VDD = AVDD = 3.6V, VDDQ = 2.7V / 3.3V, CLK = 0 or VDD  
3.5  
10  
IDD  
Dynamic Power Supply Current VDD = AVDD = 3.6V, VDDQ = 2.7V / 3.3V, CL = 0pF  
500  
15  
—
μA/MHz  
VDD = AVDD = VDDQ = 3.6V  
—
IDDD  
Dynamic Power Supply  
CurrentperOutput  
CL = 30pF, CLK = 100MHz  
mA  
VDD = AVDD = 3.6V, VDDQ = 2.7V  
CL = 20pF, CLK = 100MHz  
12  
—
NOTE:  
1. For nominal voltage and temperature.  
4
IDT5V2528/A  
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER  
INDUSTRIAL TEMPERATURE RANGE  
INPUT TIMING REQUIREMENTS OVER OPERATING RANGE  
5V2528  
5V2528A  
Min  
25  
Max  
140  
60%  
1
Min  
25  
Max  
167  
60%  
1
Units  
fCLOCK  
tLOCK  
Clockfrequency  
MHz  
Input clock duty cycle  
Stabilizationtime(1)  
40%  
40%  
ms  
NOTE:  
1.Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference  
signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are  
not applicable.  
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 5V2528(1)  
Symbol  
Parameter(2)  
Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-133MHz)  
Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (133MHz)  
OutputSkewbetween3.3VOutputs  
Min.  
–150  
–50  
—
—
—
Typ.  
Max.  
150  
50  
Unit  
ps  
ps  
ps  
ps  
ps  
ps  
%
tPHASEerror  
tPHASE error-jitter(3)  
—
—
—
—
—
—
(4)  
tSK1(0)  
150  
150  
200  
75  
(4)  
tSK2(0)  
OutputSkewbetween2.5VOutputs  
(4,5)  
tSK3(0)  
Output Skew between 2.5V and 3.3V Outputs  
Cycle-to-CycleOutputJitter(Peak-to-Peak)at133MHz  
Duty Cycle  
tJ  
–75  
45  
—
55  
tR  
tF  
tR  
tF  
Output Rise Time for 3.3V Outputs (20% to 80%)  
Output Fall Time for 3.3V Outputs (20% to 80%)  
Output Rise Time for 2.5V Outputs (20% to 80%)  
Output Fall Time for 2.5V Outputs (20% to 80%)  
0.8  
0.8  
0.5  
0.5  
—
—
—
—
2.1  
2.1  
1.5  
1.5  
ns  
ns  
ns  
ns  
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 5V2528A(1)  
Symbol  
Parameter(2)  
Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-166MHz)  
Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (166MHz)  
OutputSkewbetween3.3VOutputs  
Min.  
–150  
–50  
—
—
—
—
–75  
45  
Typ.  
—
Max.  
150  
50  
Unit  
ps  
tPHASEerror  
tPHASE error-jitter(3)  
—
—
—
—
—
—
ps  
(4)  
tSK1(0)  
150  
150  
200  
250  
75  
ps  
(4)  
tSK2(0)  
OutputSkewbetween2.5VOutputs  
ps  
(4,5)  
tSK3(0)  
Output Skew between 2.5V and 3.3V Outputs 25MHz to 133MHz  
133MHz to 166MHz  
ps  
tJ  
Cycle-to-CycleOutputJitter(Peak-to-Peak)at166MHz  
Duty Cycle  
ps  
%
—
55  
tR  
tF  
tR  
tF  
Output Rise Time for 3.3V Outputs (20% to 80%)  
Output Fall Time for 3.3V Outputs (20% to 80%)  
Output Rise Time for 2.5V Outputs (20% to 80%)  
Output Fall Time for 2.5V Outputs (20% to 80%)  
0.8  
0.8  
0.5  
0.5  
—
—
—
—
2.1  
2.1  
1.5  
1.5  
ns  
ns  
ns  
ns  
NOTES:  
1. All parameters are measured with the following load conditions: 30pF || 500Ω for 3.3V outputs and 20pF || 500Ω for 2.5V outputs.  
2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.  
3. Phase error does not include jitter.  
4. All skew parameters are only valid for equal loading of all outputs.  
5. Measured for VDDQ = 2.3V and 3V, 2.5V and 3.3V, or 2.7V and 3.6V.  
5
IDT5V2528/A  
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER  
INDUSTRIAL TEMPERATURE RANGE  
TEST CIRCUIT AND VOLTAGE WAVEFORMS  
From Output  
Under Test  
From Output  
Under Test  
500  
500  
CL=30pF(2)  
CL=20pF(2)  
Test Circuit for 3.3V Outputs  
Test Circuit for 2.5V Outputs  
VDD/2  
CLK  
VDD/2  
tPHASE ERROR  
FBIN  
Y, TY  
CL  
CLK  
80%  
20%  
FBOUT  
or  
Any Y, TY (3.3V)  
VDDQ/2  
tR  
tF  
tSK3(o)  
tF  
IDT5V2528/A  
500  
on each Y,  
TY output  
(2)  
VDDQ/2  
VDDQ/2  
tSK1(o)  
FBOUT  
Any Y, TY (3.3V)  
FBIN  
(4)  
CF  
500  
PCBTRACE  
80%  
20%  
VDDQ/2  
Any TY (2.5V)  
Any TY (2.5V)  
tR  
VDDQ/2  
VDDQ/2  
tSK2(o)  
PHASE ERROR AND SKEW CALCULATIONS(3,4)  
NOTES:  
1. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz ZO = 50Ω, tR ≤ 1.2 ns, tF ≤ 1.2 ns.  
2. CL includes probe and jig capacitance.  
3. The outputs are measured one at a time with one transition per measurement.  
4. Phase error measurements require equal loading at outputs Y, TY, and FBOUT. CF = CL – CFBIN – CPCBtrace; CFBIN ≅ 5pF.  
6
IDT5V2528/A  
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER  
INDUSTRIAL TEMPERATURE RANGE  
ORDERINGINFORMATION  
IDT  
XXXXX  
XX  
X
Device Type Package Package  
I
-40ºC to +85ºC (Industrial)  
PGG  
TSSOP - Green  
5V2528  
5V2528A  
2.5V / 3.3V Phase-Lock Loop Clock Driver  
7
IDT5V2528/A  
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER  
INDUSTRIAL TEMPERATURE RANGE  
REVISIONHISTORY  
Rev  
Table  
Page  
Discription of Change  
Date  
A
1
NRND - Not Recommended for New Designs  
5/16/13  
8
IDT5V2528/A  
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER  
INDUSTRIAL TEMPERATURE RANGE  
We’ve Got Your Timing Solution.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
Sales  
Tech Support  
netcom@idt.com  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information  
in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether  
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This  
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their  
respective third party owners.  
Copyright 2013. All rights reserved.  
9
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 		5V2305NRI 2.5V至3.3V的高性能时钟缓冲器[ 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER ] 10 页

IDT

 		5V2305NRI8 2.5V至3.3V的高性能时钟缓冲器[ 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER ] 10 页

IDT

 		5V2305PGGI 2.5V至3.3V的高性能时钟缓冲器[ 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER ] 10 页

IDT

 		5V2305PGGI8 2.5V至3.3V的高性能时钟缓冲器[ 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER ] 10 页

IDT

 		5V2305PGI 2.5V至3.3V的高性能时钟缓冲器[ 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER ] 10 页

IDT

 		5V2305PGI8 2.5V至3.3V的高性能时钟缓冲器[ 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER ] 10 页

IDT

 		5V2305S [ High-Performance 1 to 5 Clock Buffer ] 10 页

IDT

 		5V2305SNTGK [ High-Performance 1 to 5 Clock Buffer ] 10 页

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