P R O D U C T B R I E F
The "Interworking Element for 8 E1/T1 lines"
(IWE8), PXB 4220 and PXB 4221 are members of
Infineon" ATM Chipset. Together with framing and
line interface components (e.g. Infineon's
QuadFALC PEB 22554) the IWE8 serves as gate-
way between Asynchronous Transfer Mode (ATM)
networks and timeslot based PDH networks.
The IWE8 is a single chip multiservice device that
integrates ATM cell handling and TDM circuit to
ATM cell interworking in E1/T1 applications. Each
of the 8 E1 or T1 input and output ports can be
configured independently to operate in ATM Mode
or AAL Mode. It is a very flexible solution support-
ing multiple services with a minimum of devices.
Features
- Structured T1/E1 N x 64 kbit/s
service
- Channel Associated Signalling
(CAS)
■ Inverse Multiplexing over ATM
IWE8
(IMA) interface
■ Full duplex ATM Packetizer/
■ 8 generic framer interfaces with
integrated transmit clock selec-
tor supporting
Depacketizer for 8 E1/T1
highways
- Partially filled cells with pro-
grammable filling thresholds
- Reassembly buffer can com-
pensate up to +/- 4 ms Cell
Delay Variation (CDV)
- Statistics counters per chan-
nel for lost/misinserted/errored
cells etc.
- Internal clock recovery circuit
using Synchronous Residual
Time Stamp (SRTS) or Adap-
tive Clock Method (ACM) for
unstructured CES ports.
Optionally, it's possible to
order the PXB 4221 device,
which comes without SRTS
clock recovery.
■ Configurable to T1 or E1 mode
- Synchronous Mode (SYM)
- Generic Interface Mode (GIM)
- FALC Mode (FAM): Glue-less
interface for Infineon's Framer
and Line Interface Compo-
nents (FALC)
- Echo Canceller Mode (EC):
ATM cells are duplicated
internally and transmitted via
two framer ports
via external pin
■ 8 T1/E1 ports configurable inde-
pendently to ATM or AAL Mode
■ ATM Mode:
- ATM cell mapping into PDH
according to ITU-T G.804
- B-ISDN User-Network
Interface
- Physical Layer Opera-
tion at 1544 kbit/s and
2048 kbit/s according to
ITU-T I.432.3
■ UTOPIA industry standard
interface:
- Level 2 in slave mode; 8 data,
5 address lines
- Level 1 in master/slave mode
- UTOPIA clock up to 38.88 MHz
■ AAL Mode (PXB 4220/4221):
- AAL1 according to
ITU-T I.363.1 or transparent
without any adaptation layer
overhead (AAL0)
I W E 8
P X B 4 2 2 0 / 4 2 2 1
N e v e r s t o p t h i n k i n g .
